From b2d811e57bae26ce43e9116cbde6ff845ade5f28 Mon Sep 17 00:00:00 2001 From: FuChao Date: Sun, 22 Aug 2021 21:54:43 +0800 Subject: [PATCH] add Vango V85xxp project --- .gitee/PULL_REQUEST_TEMPLATE.zh-CN.md | 23 +- .../V85X3P_Lib_V1.1/Eclipse_Kill.bat | 11 + .../ADC/ADC_AC_DMA/ECLIPSE/startup_target.S | 478 +++ .../ADC/ADC_AC_DMA/ECLIPSE/template/.cproject | 226 + .../ADC/ADC_AC_DMA/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC/ADC_AC_DMA/EWARM/startup_target.s | 500 +++ .../ADC/ADC_AC_DMA/EWARM/target_flash.icf | 31 + .../ADC/ADC_AC_DMA/EWARM/template.ewd | 2741 ++++++++++++ .../ADC/ADC_AC_DMA/EWARM/template.ewp | 2007 +++++++++ .../ADC/ADC_AC_DMA/EWARM/template.eww | 10 + .../Examples/ADC/ADC_AC_DMA/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_AC_DMA/Inc/main.h | 27 + .../Examples/ADC/ADC_AC_DMA/Inc/target_isr.h | 63 + .../Examples/ADC/ADC_AC_DMA/Inc/v_stdio.h | 19 + .../ADC/ADC_AC_DMA/MDK-ARM/startup_target.s | 451 ++ .../ADC/ADC_AC_DMA/MDK-ARM/template.uvoptx | 677 +++ .../ADC/ADC_AC_DMA/MDK-ARM/template.uvprojx | 658 +++ .../ADC/ADC_AC_DMA/MDK-ARMv4/startup_target.s | 451 ++ .../ADC/ADC_AC_DMA/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC/ADC_AC_DMA/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_AC_DMA/Src/main.c | 189 + .../Examples/ADC/ADC_AC_DMA/Src/target_isr.c | 304 ++ .../Examples/ADC/ADC_AC_DMA/Src/v_stdio.c | 54 + .../ADC/ADC_BAT/ECLIPSE/startup_target.S | 478 +++ .../ADC/ADC_BAT/ECLIPSE/template/.cproject | 226 + .../ADC/ADC_BAT/ECLIPSE/template/.project | 183 + .../ADC_BAT/ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/settings/template.Debug.cspy.bat | 40 + .../EWARM/settings/template.Debug.driver.xcl | 39 + .../EWARM/settings/template.Debug.general.xcl | 13 + .../ADC/ADC_BAT/EWARM/settings/template.crun | 16 + .../ADC/ADC_BAT/EWARM/settings/template.dbgdt | 5 + .../ADC/ADC_BAT/EWARM/settings/template.dni | 24 + .../ADC/ADC_BAT/EWARM/settings/template.wsdt | 156 + .../ADC/ADC_BAT/EWARM/settings/template.wspos | 2 + .../ADC/ADC_BAT/EWARM/startup_target.s | 500 +++ .../ADC/ADC_BAT/EWARM/target_flash.icf | 31 + .../Examples/ADC/ADC_BAT/EWARM/template.ewd | 2741 ++++++++++++ .../Examples/ADC/ADC_BAT/EWARM/template.ewp | 2007 +++++++++ .../Examples/ADC/ADC_BAT/EWARM/template.eww | 10 + .../Examples/ADC/ADC_BAT/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_BAT/Inc/main.h | 27 + .../Examples/ADC/ADC_BAT/Inc/target_isr.h | 63 + .../Examples/ADC/ADC_BAT/Inc/v_stdio.h | 19 + .../ADC/ADC_BAT/MDK-ARM/startup_target.s | 451 ++ .../ADC/ADC_BAT/MDK-ARM/template.uvoptx | 677 +++ .../ADC/ADC_BAT/MDK-ARM/template.uvprojx | 658 +++ .../ADC/ADC_BAT/MDK-ARMv4/startup_target.s | 451 ++ .../ADC/ADC_BAT/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC/ADC_BAT/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_BAT/Src/main.c | 205 + .../Examples/ADC/ADC_BAT/Src/target_isr.c | 304 ++ .../Examples/ADC/ADC_BAT/Src/v_stdio.c | 54 + .../ADC/ADC_BAT_Auto/ECLIPSE/startup_target.S | 478 +++ .../ADC_BAT_Auto/ECLIPSE/template/.cproject | 226 + .../ADC_BAT_Auto/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC/ADC_BAT_Auto/EWARM/startup_target.s | 500 +++ .../ADC/ADC_BAT_Auto/EWARM/target_flash.icf | 31 + .../ADC/ADC_BAT_Auto/EWARM/template.ewd | 2741 ++++++++++++ .../ADC/ADC_BAT_Auto/EWARM/template.ewp | 2007 +++++++++ .../ADC/ADC_BAT_Auto/EWARM/template.eww | 10 + .../Examples/ADC/ADC_BAT_Auto/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_BAT_Auto/Inc/main.h | 27 + .../ADC/ADC_BAT_Auto/Inc/target_isr.h | 63 + .../Examples/ADC/ADC_BAT_Auto/Inc/v_stdio.h | 19 + .../ADC/ADC_BAT_Auto/MDK-ARM/startup_target.s | 451 ++ .../ADC/ADC_BAT_Auto/MDK-ARM/template.uvoptx | 677 +++ .../ADC/ADC_BAT_Auto/MDK-ARM/template.uvprojx | 658 +++ .../ADC_BAT_Auto/MDK-ARMv4/startup_target.s | 451 ++ .../ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC_BAT_Auto/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_BAT_Auto/Src/main.c | 169 + .../ADC/ADC_BAT_Auto/Src/target_isr.c | 304 ++ .../Examples/ADC/ADC_BAT_Auto/Src/v_stdio.c | 54 + .../ADC_BAT_Manual/ECLIPSE/startup_target.S | 478 +++ .../ADC_BAT_Manual/ECLIPSE/template/.cproject | 226 + .../ADC_BAT_Manual/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC/ADC_BAT_Manual/EWARM/startup_target.s | 500 +++ .../ADC/ADC_BAT_Manual/EWARM/target_flash.icf | 31 + .../ADC/ADC_BAT_Manual/EWARM/template.ewd | 2741 ++++++++++++ .../ADC/ADC_BAT_Manual/EWARM/template.ewp | 2007 +++++++++ .../ADC/ADC_BAT_Manual/EWARM/template.eww | 10 + .../ADC/ADC_BAT_Manual/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_BAT_Manual/Inc/main.h | 27 + .../ADC/ADC_BAT_Manual/Inc/target_isr.h | 63 + .../Examples/ADC/ADC_BAT_Manual/Inc/v_stdio.h | 19 + .../ADC_BAT_Manual/MDK-ARM/startup_target.s | 451 ++ .../ADC_BAT_Manual/MDK-ARM/template.uvoptx | 677 +++ .../ADC_BAT_Manual/MDK-ARM/template.uvprojx | 658 +++ .../ADC_BAT_Manual/MDK-ARMv4/startup_target.s | 451 ++ .../ADC_BAT_Manual/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC_BAT_Manual/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_BAT_Manual/Src/main.c | 165 + .../ADC/ADC_BAT_Manual/Src/target_isr.c | 304 ++ .../Examples/ADC/ADC_BAT_Manual/Src/v_stdio.c | 54 + .../ADC/ADC_DC/ECLIPSE/startup_target.S | 478 +++ .../ADC/ADC_DC/ECLIPSE/template/.cproject | 226 + .../ADC/ADC_DC/ECLIPSE/template/.project | 183 + .../ADC_DC/ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC/ADC_DC/EWARM/startup_target.s | 500 +++ .../ADC/ADC_DC/EWARM/target_flash.icf | 31 + .../Examples/ADC/ADC_DC/EWARM/template.ewd | 2741 ++++++++++++ .../Examples/ADC/ADC_DC/EWARM/template.ewp | 2007 +++++++++ .../Examples/ADC/ADC_DC/EWARM/template.eww | 10 + .../Examples/ADC/ADC_DC/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_DC/Inc/main.h | 27 + .../Examples/ADC/ADC_DC/Inc/target_isr.h | 63 + .../Examples/ADC/ADC_DC/Inc/v_stdio.h | 19 + .../ADC/ADC_DC/MDK-ARM/startup_target.s | 451 ++ .../ADC/ADC_DC/MDK-ARM/template.uvoptx | 677 +++ .../ADC/ADC_DC/MDK-ARM/template.uvprojx | 658 +++ .../ADC/ADC_DC/MDK-ARMv4/startup_target.s | 451 ++ .../ADC/ADC_DC/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC/ADC_DC/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_DC/Src/main.c | 173 + .../Examples/ADC/ADC_DC/Src/target_isr.c | 304 ++ .../Examples/ADC/ADC_DC/Src/v_stdio.c | 54 + .../ADC/ADC_THD/ECLIPSE/startup_target.S | 478 +++ .../ADC/ADC_THD/ECLIPSE/template/.cproject | 226 + .../ADC/ADC_THD/ECLIPSE/template/.project | 183 + .../ADC_THD/ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC/ADC_THD/EWARM/startup_target.s | 500 +++ .../ADC/ADC_THD/EWARM/target_flash.icf | 31 + .../Examples/ADC/ADC_THD/EWARM/template.ewd | 2741 ++++++++++++ .../Examples/ADC/ADC_THD/EWARM/template.ewp | 2007 +++++++++ .../Examples/ADC/ADC_THD/EWARM/template.eww | 10 + .../Examples/ADC/ADC_THD/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_THD/Inc/main.h | 27 + .../Examples/ADC/ADC_THD/Inc/target_isr.h | 63 + .../Examples/ADC/ADC_THD/Inc/v_stdio.h | 19 + .../ADC/ADC_THD/MDK-ARM/startup_target.s | 451 ++ .../ADC/ADC_THD/MDK-ARM/template.uvoptx | 682 +++ .../ADC/ADC_THD/MDK-ARM/template.uvprojx | 658 +++ .../ADC/ADC_THD/MDK-ARMv4/startup_target.s | 451 ++ .../ADC/ADC_THD/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC/ADC_THD/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_THD/Src/main.c | 261 ++ .../Examples/ADC/ADC_THD/Src/target_isr.c | 344 ++ .../Examples/ADC/ADC_THD/Src/v_stdio.c | 54 + .../ADC_Temperature/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ADC_Temperature/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC_Temperature/EWARM/startup_target.s | 500 +++ .../ADC_Temperature/EWARM/target_flash.icf | 31 + .../ADC/ADC_Temperature/EWARM/template.ewd | 2741 ++++++++++++ .../ADC/ADC_Temperature/EWARM/template.ewp | 2007 +++++++++ .../ADC/ADC_Temperature/EWARM/template.eww | 10 + .../ADC/ADC_Temperature/Inc/lib_conf.h | 66 + .../Examples/ADC/ADC_Temperature/Inc/main.h | 27 + .../ADC/ADC_Temperature/Inc/target_isr.h | 63 + .../ADC/ADC_Temperature/Inc/v_stdio.h | 19 + .../ADC_Temperature/MDK-ARM/startup_target.s | 451 ++ .../ADC_Temperature/MDK-ARM/template.uvoptx | 669 +++ .../ADC_Temperature/MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../ADC_Temperature/MDK-ARMv4/template.uvopt | 705 ++++ .../ADC_Temperature/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/ADC/ADC_Temperature/Src/main.c | 188 + .../ADC/ADC_Temperature/Src/target_isr.c | 304 ++ .../ADC/ADC_Temperature/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../ADC_Temperature_Auto/EWARM/template.ewd | 2741 ++++++++++++ .../ADC_Temperature_Auto/EWARM/template.ewp | 2007 +++++++++ .../ADC_Temperature_Auto/EWARM/template.eww | 10 + .../ADC/ADC_Temperature_Auto/Inc/lib_conf.h | 66 + .../ADC/ADC_Temperature_Auto/Inc/main.h | 27 + .../ADC/ADC_Temperature_Auto/Inc/target_isr.h | 63 + .../ADC/ADC_Temperature_Auto/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 669 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../ADC/ADC_Temperature_Auto/Src/main.c | 159 + .../ADC/ADC_Temperature_Auto/Src/target_isr.c | 304 ++ .../ADC/ADC_Temperature_Auto/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../ADC_Temperature_DC/EWARM/startup_target.s | 500 +++ .../ADC_Temperature_DC/EWARM/target_flash.icf | 31 + .../ADC/ADC_Temperature_DC/EWARM/template.ewd | 2741 ++++++++++++ .../ADC/ADC_Temperature_DC/EWARM/template.ewp | 2007 +++++++++ .../ADC/ADC_Temperature_DC/EWARM/template.eww | 10 + .../ADC/ADC_Temperature_DC/Inc/lib_conf.h | 66 + .../ADC/ADC_Temperature_DC/Inc/main.h | 27 + .../ADC/ADC_Temperature_DC/Inc/target_isr.h | 63 + .../ADC/ADC_Temperature_DC/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 669 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../ADC/ADC_Temperature_DC/Src/main.c | 272 ++ .../ADC/ADC_Temperature_DC/Src/target_isr.c | 304 ++ .../ADC/ADC_Temperature_DC/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../ADC_Temperature_Manual/EWARM/template.ewd | 2741 ++++++++++++ .../ADC_Temperature_Manual/EWARM/template.ewp | 2007 +++++++++ .../ADC_Temperature_Manual/EWARM/template.eww | 10 + .../ADC/ADC_Temperature_Manual/Inc/lib_conf.h | 66 + .../ADC/ADC_Temperature_Manual/Inc/main.h | 27 + .../ADC_Temperature_Manual/Inc/target_isr.h | 63 + .../ADC/ADC_Temperature_Manual/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 669 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../ADC/ADC_Temperature_Manual/Src/main.c | 155 + .../ADC_Temperature_Manual/Src/target_isr.c | 304 ++ .../ADC/ADC_Temperature_Manual/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 203 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../Bootloader_0x0_IAP/EWARM/startup_target.s | 500 +++ .../Bootloader_0x0_IAP/EWARM/target_flash.icf | 31 + .../Bootloader_0x0_IAP/EWARM/template.ewd | 2741 ++++++++++++ .../Bootloader_0x0_IAP/EWARM/template.ewp | 2019 +++++++++ .../Bootloader_0x0_IAP/EWARM/template.eww | 10 + .../Bootloader_0x0_IAP/Inc/common.h | 66 + .../Bootloader_0x0_IAP/Inc/lib_conf.h | 66 + .../Bootloader/Bootloader_0x0_IAP/Inc/main.h | 32 + .../Bootloader_0x0_IAP/Inc/target_isr.h | 97 + .../Bootloader_0x0_IAP/Inc/v_stdio.h | 19 + .../Bootloader_0x0_IAP/Inc/ymodem.h | 52 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 691 +++ .../MDK-ARM/template.uvprojx | 678 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 769 ++++ .../MDK-ARMv4/template.uvproj | 604 +++ .../Bootloader_0x0_IAP/Src/common.c | 411 ++ .../Bootloader_0x0_IAP/Src/download.c | 62 + .../Bootloader/Bootloader_0x0_IAP/Src/main.c | 161 + .../Bootloader_0x0_IAP/Src/target_isr.c | 540 +++ .../Bootloader_0x0_IAP/Src/upload.c | 46 + .../Bootloader_0x0_IAP/Src/v_stdio.c | 54 + .../Bootloader_0x0_IAP/Src/ymodem.c | 629 +++ .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../Bootloader_0x4000_APP/EWARM/template.ewd | 2741 ++++++++++++ .../Bootloader_0x4000_APP/EWARM/template.ewp | 2007 +++++++++ .../Bootloader_0x4000_APP/EWARM/template.eww | 10 + .../Bootloader_0x4000_APP/Inc/lib_conf.h | 66 + .../Bootloader_0x4000_APP/Inc/main.h | 30 + .../Bootloader_0x4000_APP/Inc/target_isr.h | 63 + .../Bootloader_0x4000_APP/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 647 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Bootloader_0x4000_APP/Src/main.c | 133 + .../Bootloader_0x4000_APP/Src/target_isr.c | 309 ++ .../Bootloader_0x4000_APP/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../CMP_ExtSignalToBGP/EWARM/startup_target.s | 500 +++ .../CMP_ExtSignalToBGP/EWARM/target_flash.icf | 31 + .../CMP/CMP_ExtSignalToBGP/EWARM/template.ewd | 2741 ++++++++++++ .../CMP/CMP_ExtSignalToBGP/EWARM/template.ewp | 2007 +++++++++ .../CMP/CMP_ExtSignalToBGP/EWARM/template.eww | 10 + .../CMP/CMP_ExtSignalToBGP/Inc/lib_conf.h | 66 + .../CMP/CMP_ExtSignalToBGP/Inc/main.h | 27 + .../CMP/CMP_ExtSignalToBGP/Inc/target_isr.h | 63 + .../CMP/CMP_ExtSignalToBGP/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 627 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../CMP/CMP_ExtSignalToBGP/Src/main.c | 124 + .../CMP/CMP_ExtSignalToBGP/Src/target_isr.c | 308 ++ .../CMP/CMP_ExtSignalToBGP/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../CMP_TwoExtSignals/EWARM/startup_target.s | 500 +++ .../CMP_TwoExtSignals/EWARM/target_flash.icf | 31 + .../CMP/CMP_TwoExtSignals/EWARM/template.ewd | 2741 ++++++++++++ .../CMP/CMP_TwoExtSignals/EWARM/template.ewp | 2007 +++++++++ .../CMP/CMP_TwoExtSignals/EWARM/template.eww | 10 + .../CMP/CMP_TwoExtSignals/Inc/lib_conf.h | 66 + .../Examples/CMP/CMP_TwoExtSignals/Inc/main.h | 27 + .../CMP/CMP_TwoExtSignals/Inc/target_isr.h | 63 + .../CMP/CMP_TwoExtSignals/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../CMP_TwoExtSignals/MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Examples/CMP/CMP_TwoExtSignals/Src/main.c | 130 + .../CMP/CMP_TwoExtSignals/Src/target_isr.c | 308 ++ .../CMP/CMP_TwoExtSignals/Src/v_stdio.c | 54 + .../CMP_WakeUp_Sleep/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../CMP_WakeUp_Sleep/EWARM/startup_target.s | 500 +++ .../CMP_WakeUp_Sleep/EWARM/target_flash.icf | 31 + .../CMP/CMP_WakeUp_Sleep/EWARM/template.ewd | 2741 ++++++++++++ .../CMP/CMP_WakeUp_Sleep/EWARM/template.ewp | 2007 +++++++++ .../CMP/CMP_WakeUp_Sleep/EWARM/template.eww | 10 + .../CMP/CMP_WakeUp_Sleep/Inc/lib_conf.h | 66 + .../Examples/CMP/CMP_WakeUp_Sleep/Inc/main.h | 27 + .../CMP/CMP_WakeUp_Sleep/Inc/target_isr.h | 63 + .../CMP/CMP_WakeUp_Sleep/Inc/v_stdio.h | 19 + .../CMP_WakeUp_Sleep/MDK-ARM/startup_target.s | 451 ++ .../CMP_WakeUp_Sleep/MDK-ARM/template.uvoptx | 639 +++ .../CMP_WakeUp_Sleep/MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../CMP_WakeUp_Sleep/MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Examples/CMP/CMP_WakeUp_Sleep/Src/main.c | 140 + .../CMP/CMP_WakeUp_Sleep/Src/target_isr.c | 307 ++ .../CMP/CMP_WakeUp_Sleep/Src/v_stdio.c | 54 + .../CRYPT/CRYPT_Add/ECLIPSE/startup_target.S | 478 +++ .../CRYPT_Add/ECLIPSE/template/.cproject | 226 + .../CRYPT/CRYPT_Add/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../CRYPT/CRYPT_Add/EWARM/startup_target.s | 500 +++ .../CRYPT/CRYPT_Add/EWARM/target_flash.icf | 31 + .../CRYPT/CRYPT_Add/EWARM/template.ewd | 2741 ++++++++++++ .../CRYPT/CRYPT_Add/EWARM/template.ewp | 2007 +++++++++ .../CRYPT/CRYPT_Add/EWARM/template.eww | 10 + .../Examples/CRYPT/CRYPT_Add/Inc/lib_conf.h | 66 + .../Examples/CRYPT/CRYPT_Add/Inc/main.h | 27 + .../Examples/CRYPT/CRYPT_Add/Inc/target_isr.h | 63 + .../Examples/CRYPT/CRYPT_Add/Inc/v_stdio.h | 19 + .../CRYPT/CRYPT_Add/MDK-ARM/startup_target.s | 451 ++ .../CRYPT/CRYPT_Add/MDK-ARM/template.uvoptx | 621 +++ .../CRYPT/CRYPT_Add/MDK-ARM/template.uvprojx | 634 +++ .../CRYPT_Add/MDK-ARMv4/startup_target.s | 451 ++ .../CRYPT/CRYPT_Add/MDK-ARMv4/template.uvopt | 705 ++++ .../CRYPT/CRYPT_Add/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/CRYPT/CRYPT_Add/Src/main.c | 108 + .../Examples/CRYPT/CRYPT_Add/Src/target_isr.c | 303 ++ .../Examples/CRYPT/CRYPT_Add/Src/v_stdio.c | 54 + .../CRYPT_ECC256Signatures/EWARM/IAR_Kill.bat | 8 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../CRYPT_ECC256Signatures/EWARM/template.ewd | 2741 ++++++++++++ .../CRYPT_ECC256Signatures/EWARM/template.ewp | 2019 +++++++++ .../CRYPT_ECC256Signatures/EWARM/template.eww | 10 + .../CRYPT_ECC256Signatures/Inc/lib_conf.h | 66 + .../CRYPT/CRYPT_ECC256Signatures/Inc/main.h | 30 + .../CRYPT_ECC256Signatures/Inc/target_isr.h | 63 + .../CRYPT_ECC256Signatures/Inc/v_stdio.h | 19 + .../CRYPT_ECC256Signatures/Src/asm_arm.inc | 822 ++++ .../Src/curve-specific.inc | 1247 ++++++ .../CRYPT/CRYPT_ECC256Signatures/Src/main.c | 143 + .../Src/platform-specific.inc | 86 + .../CRYPT_ECC256Signatures/Src/target_isr.c | 304 ++ .../CRYPT/CRYPT_ECC256Signatures/Src/types.h | 108 + .../CRYPT/CRYPT_ECC256Signatures/Src/uECC.c | 1882 +++++++++ .../CRYPT/CRYPT_ECC256Signatures/Src/uECC.h | 364 ++ .../CRYPT_ECC256Signatures/Src/uECC_vli.h | 173 + .../CRYPT_ECC256Signatures/Src/v_stdio.c | 38 + .../Cortex/BitBand/ECLIPSE/startup_target.S | 478 +++ .../Cortex/BitBand/ECLIPSE/template/.cproject | 226 + .../Cortex/BitBand/ECLIPSE/template/.project | 183 + .../BitBand/ECLIPSE/template/Target_FLASH.ld | 183 + .../Cortex/BitBand/EWARM/startup_target.s | 500 +++ .../Cortex/BitBand/EWARM/target_flash.icf | 31 + .../Cortex/BitBand/EWARM/template.ewd | 2741 ++++++++++++ .../Cortex/BitBand/EWARM/template.ewp | 2007 +++++++++ .../Cortex/BitBand/EWARM/template.eww | 10 + .../Examples/Cortex/BitBand/Inc/lib_conf.h | 66 + .../Examples/Cortex/BitBand/Inc/main.h | 27 + .../Examples/Cortex/BitBand/Inc/target_isr.h | 63 + .../Examples/Cortex/BitBand/Inc/v_stdio.h | 19 + .../Cortex/BitBand/MDK-ARM/startup_target.s | 451 ++ .../Cortex/BitBand/MDK-ARM/template.uvoptx | 639 +++ .../Cortex/BitBand/MDK-ARM/template.uvprojx | 658 +++ .../Cortex/BitBand/MDK-ARMv4/startup_target.s | 451 ++ .../Cortex/BitBand/MDK-ARMv4/template.uvopt | 705 ++++ .../Cortex/BitBand/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/Cortex/BitBand/Src/main.c | 104 + .../Examples/Cortex/BitBand/Src/target_isr.c | 305 ++ .../Examples/Cortex/BitBand/Src/v_stdio.c | 54 + .../DMA/DMA_AES/ECLIPSE/startup_target.S | 478 +++ .../DMA/DMA_AES/ECLIPSE/template/.cproject | 226 + .../DMA/DMA_AES/ECLIPSE/template/.project | 183 + .../DMA_AES/ECLIPSE/template/Target_FLASH.ld | 183 + .../DMA/DMA_AES/EWARM/startup_target.s | 500 +++ .../DMA/DMA_AES/EWARM/target_flash.icf | 31 + .../Examples/DMA/DMA_AES/EWARM/template.ewd | 2741 ++++++++++++ .../Examples/DMA/DMA_AES/EWARM/template.ewp | 2007 +++++++++ .../Examples/DMA/DMA_AES/EWARM/template.eww | 10 + .../Examples/DMA/DMA_AES/Inc/lib_conf.h | 66 + .../Examples/DMA/DMA_AES/Inc/main.h | 27 + .../Examples/DMA/DMA_AES/Inc/target_isr.h | 63 + .../Examples/DMA/DMA_AES/Inc/v_stdio.h | 19 + .../DMA/DMA_AES/MDK-ARM/startup_target.s | 451 ++ .../DMA/DMA_AES/MDK-ARM/template.uvoptx | 639 +++ .../DMA/DMA_AES/MDK-ARM/template.uvprojx | 658 +++ .../DMA/DMA_AES/MDK-ARMv4/startup_target.s | 451 ++ .../DMA/DMA_AES/MDK-ARMv4/template.uvopt | 705 ++++ .../DMA/DMA_AES/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/DMA/DMA_AES/Src/main.c | 176 + .../Examples/DMA/DMA_AES/Src/target_isr.c | 303 ++ .../Examples/DMA/DMA_AES/Src/v_stdio.c | 54 + .../DMA_FlashToRAM/ECLIPSE/startup_target.S | 478 +++ .../DMA_FlashToRAM/ECLIPSE/template/.cproject | 226 + .../DMA_FlashToRAM/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../DMA/DMA_FlashToRAM/EWARM/startup_target.s | 500 +++ .../DMA/DMA_FlashToRAM/EWARM/target_flash.icf | 31 + .../DMA/DMA_FlashToRAM/EWARM/template.ewd | 2741 ++++++++++++ .../DMA/DMA_FlashToRAM/EWARM/template.ewp | 2007 +++++++++ .../DMA/DMA_FlashToRAM/EWARM/template.eww | 10 + .../DMA/DMA_FlashToRAM/Inc/lib_conf.h | 66 + .../Examples/DMA/DMA_FlashToRAM/Inc/main.h | 30 + .../DMA/DMA_FlashToRAM/Inc/target_isr.h | 63 + .../Examples/DMA/DMA_FlashToRAM/Inc/v_stdio.h | 19 + .../DMA_FlashToRAM/MDK-ARM/startup_target.s | 451 ++ .../DMA_FlashToRAM/MDK-ARM/template.uvoptx | 682 +++ .../DMA_FlashToRAM/MDK-ARM/template.uvprojx | 658 +++ .../DMA_FlashToRAM/MDK-ARMv4/startup_target.s | 451 ++ .../DMA_FlashToRAM/MDK-ARMv4/template.uvopt | 705 ++++ .../DMA_FlashToRAM/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/DMA/DMA_FlashToRAM/Src/main.c | 152 + .../DMA/DMA_FlashToRAM/Src/target_isr.c | 308 ++ .../Examples/DMA/DMA_FlashToRAM/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../DMA_ISO7816_Transmit/EWARM/template.ewd | 2741 ++++++++++++ .../DMA_ISO7816_Transmit/EWARM/template.ewp | 2007 +++++++++ .../DMA_ISO7816_Transmit/EWARM/template.eww | 10 + .../DMA/DMA_ISO7816_Transmit/Inc/lib_conf.h | 66 + .../DMA/DMA_ISO7816_Transmit/Inc/main.h | 29 + .../DMA/DMA_ISO7816_Transmit/Inc/target_isr.h | 63 + .../DMA/DMA_ISO7816_Transmit/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../DMA/DMA_ISO7816_Transmit/Src/main.c | 156 + .../DMA/DMA_ISO7816_Transmit/Src/target_isr.c | 306 ++ .../DMA/DMA_ISO7816_Transmit/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../DMA_MemoryToPeripheral_Timer/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../DMA_MemoryToPeripheral_Timer/Src/main.c | 145 + .../Src/target_isr.c | 303 ++ .../Src/v_stdio.c | 54 + .../DMA_SPI_Transmit/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../DMA_SPI_Transmit/EWARM/startup_target.s | 500 +++ .../DMA_SPI_Transmit/EWARM/target_flash.icf | 31 + .../DMA/DMA_SPI_Transmit/EWARM/template.ewd | 2741 ++++++++++++ .../DMA/DMA_SPI_Transmit/EWARM/template.ewp | 2007 +++++++++ .../DMA/DMA_SPI_Transmit/EWARM/template.eww | 10 + .../DMA/DMA_SPI_Transmit/Inc/lib_conf.h | 66 + .../Examples/DMA/DMA_SPI_Transmit/Inc/main.h | 27 + .../DMA/DMA_SPI_Transmit/Inc/target_isr.h | 63 + .../DMA/DMA_SPI_Transmit/Inc/v_stdio.h | 19 + .../DMA_SPI_Transmit/MDK-ARM/startup_target.s | 451 ++ .../DMA_SPI_Transmit/MDK-ARM/template.uvoptx | 639 +++ .../DMA_SPI_Transmit/MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../DMA_SPI_Transmit/MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Examples/DMA/DMA_SPI_Transmit/Src/main.c | 132 + .../DMA/DMA_SPI_Transmit/Src/target_isr.c | 303 ++ .../DMA/DMA_SPI_Transmit/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../DMA_UART_TransmitIT/EWARM/template.ewd | 2741 ++++++++++++ .../DMA_UART_TransmitIT/EWARM/template.ewp | 2007 +++++++++ .../DMA_UART_TransmitIT/EWARM/template.eww | 10 + .../DMA/DMA_UART_TransmitIT/Inc/lib_conf.h | 66 + .../DMA/DMA_UART_TransmitIT/Inc/main.h | 30 + .../DMA/DMA_UART_TransmitIT/Inc/target_isr.h | 63 + .../DMA/DMA_UART_TransmitIT/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../DMA/DMA_UART_TransmitIT/Src/main.c | 153 + .../DMA/DMA_UART_TransmitIT/Src/target_isr.c | 313 ++ .../DMA/DMA_UART_TransmitIT/Src/v_stdio.c | 54 + .../Flash_Program/ECLIPSE/startup_target.S | 478 +++ .../Flash_Program/ECLIPSE/template/.cproject | 226 + .../Flash_Program/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../Flash_Program/EWARM/startup_target.s | 500 +++ .../Flash_Program/EWARM/target_flash.icf | 31 + .../Flash/Flash_Program/EWARM/template.ewd | 2741 ++++++++++++ .../Flash/Flash_Program/EWARM/template.ewp | 2007 +++++++++ .../Flash/Flash_Program/EWARM/template.eww | 10 + .../Flash/Flash_Program/Inc/lib_conf.h | 66 + .../Examples/Flash/Flash_Program/Inc/main.h | 27 + .../Flash/Flash_Program/Inc/target_isr.h | 63 + .../Flash/Flash_Program/Inc/v_stdio.h | 19 + .../Flash_Program/MDK-ARM/startup_target.s | 451 ++ .../Flash_Program/MDK-ARM/template.uvoptx | 694 ++++ .../Flash_Program/MDK-ARM/template.uvprojx | 658 +++ .../Flash_Program/MDK-ARMv4/startup_target.s | 451 ++ .../Flash_Program/MDK-ARMv4/template.uvopt | 705 ++++ .../Flash_Program/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/Flash/Flash_Program/Src/main.c | 158 + .../Flash/Flash_Program/Src/target_isr.c | 309 ++ .../Flash/Flash_Program/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../Flash_Protection_UARTProtocol/Inc/main.h | 29 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 695 ++++ .../MDK-ARM/template.uvprojx | 652 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Flash_Protection_UARTProtocol/Src/main.c | 280 ++ .../Src/target_isr.c | 306 ++ .../Src/v_stdio.c | 54 + .../GPIO/GPIOA_EXIT/ECLIPSE/startup_target.S | 478 +++ .../GPIOA_EXIT/ECLIPSE/template/.cproject | 226 + .../GPIO/GPIOA_EXIT/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../GPIO/GPIOA_EXIT/EWARM/startup_target.s | 500 +++ .../GPIO/GPIOA_EXIT/EWARM/target_flash.icf | 31 + .../GPIO/GPIOA_EXIT/EWARM/template.ewd | 2741 ++++++++++++ .../GPIO/GPIOA_EXIT/EWARM/template.ewp | 2007 +++++++++ .../GPIO/GPIOA_EXIT/EWARM/template.eww | 10 + .../Examples/GPIO/GPIOA_EXIT/Inc/lib_conf.h | 66 + .../Examples/GPIO/GPIOA_EXIT/Inc/main.h | 27 + .../Examples/GPIO/GPIOA_EXIT/Inc/target_isr.h | 63 + .../Examples/GPIO/GPIOA_EXIT/Inc/v_stdio.h | 19 + .../GPIO/GPIOA_EXIT/MDK-ARM/startup_target.s | 451 ++ .../GPIO/GPIOA_EXIT/MDK-ARM/template.uvoptx | 621 +++ .../GPIO/GPIOA_EXIT/MDK-ARM/template.uvprojx | 634 +++ .../GPIOA_EXIT/MDK-ARMv4/startup_target.s | 451 ++ .../GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvopt | 705 ++++ .../GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/GPIO/GPIOA_EXIT/Src/main.c | 88 + .../Examples/GPIO/GPIOA_EXIT/Src/target_isr.c | 308 ++ .../Examples/GPIO/GPIOA_EXIT/Src/v_stdio.c | 54 + .../GPIOA_WakeUp/ECLIPSE/startup_target.S | 478 +++ .../GPIOA_WakeUp/ECLIPSE/template/.cproject | 226 + .../GPIOA_WakeUp/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../GPIO/GPIOA_WakeUp/EWARM/startup_target.s | 500 +++ .../GPIO/GPIOA_WakeUp/EWARM/target_flash.icf | 31 + .../GPIO/GPIOA_WakeUp/EWARM/template.ewd | 2741 ++++++++++++ .../GPIO/GPIOA_WakeUp/EWARM/template.ewp | 2007 +++++++++ .../GPIO/GPIOA_WakeUp/EWARM/template.eww | 10 + .../Examples/GPIO/GPIOA_WakeUp/Inc/lib_conf.h | 66 + .../Examples/GPIO/GPIOA_WakeUp/Inc/main.h | 27 + .../GPIO/GPIOA_WakeUp/Inc/target_isr.h | 63 + .../Examples/GPIO/GPIOA_WakeUp/Inc/v_stdio.h | 19 + .../GPIOA_WakeUp/MDK-ARM/startup_target.s | 451 ++ .../GPIO/GPIOA_WakeUp/MDK-ARM/template.uvoptx | 621 +++ .../GPIOA_WakeUp/MDK-ARM/template.uvprojx | 634 +++ .../GPIOA_WakeUp/MDK-ARMv4/startup_target.s | 451 ++ .../GPIOA_WakeUp/MDK-ARMv4/template.uvopt | 705 ++++ .../GPIOA_WakeUp/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/GPIO/GPIOA_WakeUp/Src/main.c | 135 + .../GPIO/GPIOA_WakeUp/Src/target_isr.c | 309 ++ .../Examples/GPIO/GPIOA_WakeUp/Src/v_stdio.c | 54 + .../GPIO/GPIO_Toggle/ECLIPSE/startup_target.S | 478 +++ .../GPIO_Toggle/ECLIPSE/template/.cproject | 226 + .../GPIO_Toggle/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../GPIO/GPIO_Toggle/EWARM/startup_target.s | 500 +++ .../GPIO/GPIO_Toggle/EWARM/target_flash.icf | 31 + .../GPIO/GPIO_Toggle/EWARM/template.ewd | 2741 ++++++++++++ .../GPIO/GPIO_Toggle/EWARM/template.ewp | 2007 +++++++++ .../GPIO/GPIO_Toggle/EWARM/template.eww | 10 + .../Examples/GPIO/GPIO_Toggle/Inc/lib_conf.h | 66 + .../Examples/GPIO/GPIO_Toggle/Inc/main.h | 27 + .../GPIO/GPIO_Toggle/Inc/target_isr.h | 63 + .../Examples/GPIO/GPIO_Toggle/Inc/v_stdio.h | 19 + .../GPIO/GPIO_Toggle/MDK-ARM/startup_target.s | 451 ++ .../GPIO/GPIO_Toggle/MDK-ARM/template.uvoptx | 639 +++ .../GPIO/GPIO_Toggle/MDK-ARM/template.uvprojx | 658 +++ .../GPIO_Toggle/MDK-ARMv4/startup_target.s | 451 ++ .../GPIO/GPIO_Toggle/MDK-ARMv4/template.uvopt | 705 ++++ .../GPIO_Toggle/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/GPIO/GPIO_Toggle/Src/main.c | 103 + .../GPIO/GPIO_Toggle/Src/target_isr.c | 303 ++ .../Examples/GPIO/GPIO_Toggle/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../I2C_EEPROM_AT24C1024_100KClock/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../I2C_EEPROM_AT24C1024_100KClock/Src/main.c | 148 + .../Src/target_isr.c | 303 ++ .../Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../I2C_EEPROM_AT24C256_100KClock/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../I2C_EEPROM_AT24C256_100KClock/Src/main.c | 147 + .../Src/target_isr.c | 303 ++ .../Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../I2C_EEPROM_AT24C256_1MClock/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../I2C_EEPROM_AT24C256_1MClock/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../I2C_EEPROM_AT24C256_1MClock/Src/main.c | 168 + .../Src/target_isr.c | 303 ++ .../I2C_EEPROM_AT24C256_1MClock/Src/v_stdio.c | 54 + .../ISO7816_Transmit/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../ISO7816_Transmit/EWARM/startup_target.s | 500 +++ .../ISO7816_Transmit/EWARM/target_flash.icf | 31 + .../ISO7816_Transmit/EWARM/template.ewd | 2741 ++++++++++++ .../ISO7816_Transmit/EWARM/template.ewp | 2007 +++++++++ .../ISO7816_Transmit/EWARM/template.eww | 10 + .../ISO7816/ISO7816_Transmit/Inc/lib_conf.h | 66 + .../ISO7816/ISO7816_Transmit/Inc/main.h | 29 + .../ISO7816/ISO7816_Transmit/Inc/target_isr.h | 63 + .../ISO7816/ISO7816_Transmit/Inc/v_stdio.h | 19 + .../ISO7816_Transmit/MDK-ARM/startup_target.s | 451 ++ .../ISO7816_Transmit/MDK-ARM/template.uvoptx | 639 +++ .../ISO7816_Transmit/MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../ISO7816_Transmit/MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../ISO7816/ISO7816_Transmit/Src/main.c | 120 + .../ISO7816/ISO7816_Transmit/Src/target_isr.c | 304 ++ .../ISO7816/ISO7816_Transmit/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../LCD_D1135_DisplayNumber/Inc/lib_conf.h | 66 + .../LCD/LCD_D1135_DisplayNumber/Inc/main.h | 27 + .../LCD_D1135_DisplayNumber/Inc/target_isr.h | 63 + .../LCD/LCD_D1135_DisplayNumber/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../LCD/LCD_D1135_DisplayNumber/Src/main.c | 235 ++ .../LCD_D1135_DisplayNumber/Src/target_isr.c | 303 ++ .../LCD/LCD_D1135_DisplayNumber/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../LCD_TS_DH_3541_DisplayNumber/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 656 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../LCD_TS_DH_3541_DisplayNumber/Src/main.c | 345 ++ .../Src/target_isr.c | 303 ++ .../Src/v_stdio.c | 54 + .../POWER/AVCCLV_IT/ECLIPSE/startup_target.S | 478 +++ .../POWER/AVCCLV_IT/EWARM/startup_target.s | 500 +++ .../POWER/AVCCLV_IT/EWARM/target_flash.icf | 31 + .../POWER/AVCCLV_IT/EWARM/template.ewd | 2741 ++++++++++++ .../POWER/AVCCLV_IT/EWARM/template.ewp | 2007 +++++++++ .../POWER/AVCCLV_IT/EWARM/template.eww | 10 + .../Examples/POWER/AVCCLV_IT/Inc/lib_conf.h | 66 + .../Examples/POWER/AVCCLV_IT/Inc/main.h | 27 + .../Examples/POWER/AVCCLV_IT/Inc/target_isr.h | 63 + .../Examples/POWER/AVCCLV_IT/Inc/v_stdio.h | 19 + .../POWER/AVCCLV_IT/MDK-ARM/startup_target.s | 451 ++ .../POWER/AVCCLV_IT/MDK-ARM/template.uvoptx | 638 +++ .../POWER/AVCCLV_IT/MDK-ARM/template.uvprojx | 652 +++ .../AVCCLV_IT/MDK-ARMv4/startup_target.s | 451 ++ .../POWER/AVCCLV_IT/MDK-ARMv4/template.uvopt | 705 ++++ .../POWER/AVCCLV_IT/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/POWER/AVCCLV_IT/Src/main.c | 107 + .../Examples/POWER/AVCCLV_IT/Src/target_isr.c | 309 ++ .../Examples/POWER/AVCCLV_IT/Src/v_stdio.c | 54 + .../VDDAlarm_IT/ECLIPSE/startup_target.S | 478 +++ .../VDDAlarm_IT/ECLIPSE/template/.cproject | 226 + .../VDDAlarm_IT/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../POWER/VDDAlarm_IT/EWARM/startup_target.s | 500 +++ .../POWER/VDDAlarm_IT/EWARM/target_flash.icf | 31 + .../POWER/VDDAlarm_IT/EWARM/template.ewd | 2741 ++++++++++++ .../POWER/VDDAlarm_IT/EWARM/template.ewp | 2007 +++++++++ .../POWER/VDDAlarm_IT/EWARM/template.eww | 10 + .../Examples/POWER/VDDAlarm_IT/Inc/lib_conf.h | 66 + .../Examples/POWER/VDDAlarm_IT/Inc/main.h | 27 + .../POWER/VDDAlarm_IT/Inc/target_isr.h | 63 + .../Examples/POWER/VDDAlarm_IT/Inc/v_stdio.h | 19 + .../VDDAlarm_IT/MDK-ARM/startup_target.s | 451 ++ .../POWER/VDDAlarm_IT/MDK-ARM/template.uvoptx | 621 +++ .../VDDAlarm_IT/MDK-ARM/template.uvprojx | 634 +++ .../VDDAlarm_IT/MDK-ARMv4/startup_target.s | 451 ++ .../VDDAlarm_IT/MDK-ARMv4/template.uvopt | 705 ++++ .../VDDAlarm_IT/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/POWER/VDDAlarm_IT/Src/main.c | 106 + .../POWER/VDDAlarm_IT/Src/target_isr.c | 309 ++ .../Examples/POWER/VDDAlarm_IT/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../PWM_16BitsBaseTimer_IT/EWARM/template.ewd | 2741 ++++++++++++ .../PWM_16BitsBaseTimer_IT/EWARM/template.ewp | 2007 +++++++++ .../PWM_16BitsBaseTimer_IT/EWARM/template.eww | 10 + .../PWM/PWM_16BitsBaseTimer_IT/Inc/lib_conf.h | 66 + .../PWM/PWM_16BitsBaseTimer_IT/Inc/main.h | 27 + .../PWM_16BitsBaseTimer_IT/Inc/target_isr.h | 63 + .../PWM/PWM_16BitsBaseTimer_IT/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../PWM/PWM_16BitsBaseTimer_IT/Src/main.c | 110 + .../PWM_16BitsBaseTimer_IT/Src/target_isr.c | 310 ++ .../PWM/PWM_16BitsBaseTimer_IT/Src/v_stdio.c | 54 + .../PWM/PWM_Capture/ECLIPSE/startup_target.S | 478 +++ .../PWM_Capture/ECLIPSE/template/.cproject | 226 + .../PWM/PWM_Capture/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../PWM/PWM_Capture/EWARM/startup_target.s | 500 +++ .../PWM/PWM_Capture/EWARM/target_flash.icf | 31 + .../PWM/PWM_Capture/EWARM/template.ewd | 2741 ++++++++++++ .../PWM/PWM_Capture/EWARM/template.ewp | 2007 +++++++++ .../PWM/PWM_Capture/EWARM/template.eww | 10 + .../Examples/PWM/PWM_Capture/Inc/lib_conf.h | 66 + .../Examples/PWM/PWM_Capture/Inc/main.h | 27 + .../Examples/PWM/PWM_Capture/Inc/target_isr.h | 63 + .../Examples/PWM/PWM_Capture/Inc/v_stdio.h | 19 + .../PWM/PWM_Capture/MDK-ARM/startup_target.s | 451 ++ .../PWM/PWM_Capture/MDK-ARM/template.uvoptx | 621 +++ .../PWM/PWM_Capture/MDK-ARM/template.uvprojx | 634 +++ .../PWM_Capture/MDK-ARMv4/startup_target.s | 451 ++ .../PWM/PWM_Capture/MDK-ARMv4/template.uvopt | 705 ++++ .../PWM/PWM_Capture/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/PWM/PWM_Capture/Src/main.c | 138 + .../Examples/PWM/PWM_Capture/Src/target_isr.c | 319 ++ .../Examples/PWM/PWM_Capture/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../PWM_CompareOutput/EWARM/startup_target.s | 500 +++ .../PWM_CompareOutput/EWARM/target_flash.icf | 31 + .../PWM/PWM_CompareOutput/EWARM/template.ewd | 2741 ++++++++++++ .../PWM/PWM_CompareOutput/EWARM/template.ewp | 2007 +++++++++ .../PWM/PWM_CompareOutput/EWARM/template.eww | 10 + .../PWM/PWM_CompareOutput/Inc/lib_conf.h | 66 + .../Examples/PWM/PWM_CompareOutput/Inc/main.h | 27 + .../PWM/PWM_CompareOutput/Inc/target_isr.h | 63 + .../PWM/PWM_CompareOutput/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../PWM_CompareOutput/MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Examples/PWM/PWM_CompareOutput/Src/main.c | 139 + .../PWM/PWM_CompareOutput/Src/target_isr.c | 303 ++ .../PWM/PWM_CompareOutput/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../PowerConsumption_Idle_RTCCLK/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 639 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../PowerConsumption_Idle_RTCCLK/Src/main.c | 136 + .../Src/target_isr.c | 303 ++ .../Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../PowerConsumption_Sleep/EWARM/template.ewd | 2741 ++++++++++++ .../PowerConsumption_Sleep/EWARM/template.ewp | 2007 +++++++++ .../PowerConsumption_Sleep/EWARM/template.eww | 10 + .../PowerConsumption_Sleep/Inc/lib_conf.h | 66 + .../PowerConsumption_Sleep/Inc/main.h | 27 + .../PowerConsumption_Sleep/Inc/target_isr.h | 63 + .../PowerConsumption_Sleep/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../PowerConsumption_Sleep/Src/main.c | 111 + .../PowerConsumption_Sleep/Src/target_isr.c | 303 ++ .../PowerConsumption_Sleep/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../RTC_ManualCalibration/EWARM/template.ewd | 2741 ++++++++++++ .../RTC_ManualCalibration/EWARM/template.ewp | 2007 +++++++++ .../RTC_ManualCalibration/EWARM/template.eww | 10 + .../RTC/RTC_ManualCalibration/Inc/lib_conf.h | 67 + .../RTC/RTC_ManualCalibration/Inc/main.h | 27 + .../RTC_ManualCalibration/Inc/target_isr.h | 63 + .../RTC/RTC_ManualCalibration/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 680 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../RTC/RTC_ManualCalibration/Src/main.c | 265 ++ .../RTC_ManualCalibration/Src/target_isr.c | 305 ++ .../RTC/RTC_ManualCalibration/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../RTC_MulSecMin_WakeUpSleep/Inc/lib_conf.h | 66 + .../RTC/RTC_MulSecMin_WakeUpSleep/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../RTC_MulSecMin_WakeUpSleep/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 639 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../RTC/RTC_MulSecMin_WakeUpSleep/Src/main.c | 157 + .../Src/target_isr.c | 304 ++ .../RTC_MulSecMin_WakeUpSleep/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../RTC_PLLDividerOutput_1Hz/Inc/lib_conf.h | 66 + .../RTC/RTC_PLLDividerOutput_1Hz/Inc/main.h | 27 + .../RTC_PLLDividerOutput_1Hz/Inc/target_isr.h | 63 + .../RTC_PLLDividerOutput_1Hz/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 639 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../RTC/RTC_PLLDividerOutput_1Hz/Src/main.c | 90 + .../RTC_PLLDividerOutput_1Hz/Src/target_isr.c | 303 ++ .../RTC_PLLDividerOutput_1Hz/Src/v_stdio.c | 54 + .../RTC_SubSecAlarm/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../RTC_SubSecAlarm/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../RTC_SubSecAlarm/EWARM/startup_target.s | 500 +++ .../RTC_SubSecAlarm/EWARM/target_flash.icf | 31 + .../RTC/RTC_SubSecAlarm/EWARM/template.ewd | 2741 ++++++++++++ .../RTC/RTC_SubSecAlarm/EWARM/template.ewp | 2007 +++++++++ .../RTC/RTC_SubSecAlarm/EWARM/template.eww | 10 + .../RTC/RTC_SubSecAlarm/Inc/lib_conf.h | 66 + .../Examples/RTC/RTC_SubSecAlarm/Inc/main.h | 27 + .../RTC/RTC_SubSecAlarm/Inc/target_isr.h | 63 + .../RTC/RTC_SubSecAlarm/Inc/v_stdio.h | 19 + .../RTC_SubSecAlarm/MDK-ARM/startup_target.s | 451 ++ .../RTC_SubSecAlarm/MDK-ARM/template.uvoptx | 639 +++ .../RTC_SubSecAlarm/MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../RTC_SubSecAlarm/MDK-ARMv4/template.uvopt | 705 ++++ .../RTC_SubSecAlarm/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/RTC/RTC_SubSecAlarm/Src/main.c | 155 + .../RTC/RTC_SubSecAlarm/Src/target_isr.c | 309 ++ .../RTC/RTC_SubSecAlarm/Src/v_stdio.c | 54 + .../SD612_CRC_Test/ECLIPSE/startup_target.S | 478 +++ .../SD612_CRC_Test/ECLIPSE/template/.cproject | 226 + .../SD612_CRC_Test/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../SD612_CRC_Test/EWARM/startup_target.s | 500 +++ .../SD612_CRC_Test/EWARM/target_flash.icf | 31 + .../SD612/SD612_CRC_Test/EWARM/template.ewd | 2741 ++++++++++++ .../SD612/SD612_CRC_Test/EWARM/template.ewp | 2007 +++++++++ .../SD612/SD612_CRC_Test/EWARM/template.eww | 10 + .../SD612/SD612_CRC_Test/Inc/lib_conf.h | 66 + .../Examples/SD612/SD612_CRC_Test/Inc/main.h | 27 + .../SD612/SD612_CRC_Test/Inc/target_isr.h | 63 + .../SD612/SD612_CRC_Test/Inc/v_stdio.h | 19 + .../SD612_CRC_Test/MDK-ARM/startup_target.s | 451 ++ .../SD612_CRC_Test/MDK-ARM/template.uvoptx | 656 +++ .../SD612_CRC_Test/MDK-ARM/template.uvprojx | 658 +++ .../SD612_CRC_Test/MDK-ARMv4/startup_target.s | 451 ++ .../SD612_CRC_Test/MDK-ARMv4/template.uvopt | 705 ++++ .../SD612_CRC_Test/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/SD612/SD612_CRC_Test/Src/main.c | 235 ++ .../SD612/SD612_CRC_Test/Src/target_isr.c | 303 ++ .../SD612/SD612_CRC_Test/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 188 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2010 +++++++++ .../EWARM/template.eww | 10 + .../Inc/FM25Q32.h | 65 + .../Inc/lib_conf.h | 66 + .../Inc/main.h | 29 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 633 +++ .../MDK-ARM/template.uvprojx | 639 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 721 ++++ .../MDK-ARMv4/template.uvproj | 589 +++ .../Src/FM25Q32.c | 723 ++++ .../Src/main.c | 89 + .../Src/target_isr.c | 304 ++ .../Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../SPI_TransmitIT_SSUnused/Inc/lib_conf.h | 66 + .../SPI/SPI_TransmitIT_SSUnused/Inc/main.h | 36 + .../SPI_TransmitIT_SSUnused/Inc/target_isr.h | 63 + .../SPI/SPI_TransmitIT_SSUnused/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../SPI/SPI_TransmitIT_SSUnused/Src/main.c | 143 + .../SPI_TransmitIT_SSUnused/Src/target_isr.c | 315 ++ .../SPI/SPI_TransmitIT_SSUnused/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../Inc/lib_conf.h | 66 + .../Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 639 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../Src/main.c | 165 + .../Src/target_isr.c | 303 ++ .../Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../SysTick_24BitsBaseTimer_IT/Inc/lib_conf.h | 66 + .../SysTick_24BitsBaseTimer_IT/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../SysTick_24BitsBaseTimer_IT/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../SysTick_24BitsBaseTimer_IT/Src/main.c | 101 + .../Src/target_isr.c | 306 ++ .../SysTick_24BitsBaseTimer_IT/Src/v_stdio.c | 54 + .../SysTick_Delay_IT/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../SysTick_Delay_IT/EWARM/startup_target.s | 500 +++ .../SysTick_Delay_IT/EWARM/target_flash.icf | 31 + .../SysTick_Delay_IT/EWARM/template.ewd | 2741 ++++++++++++ .../SysTick_Delay_IT/EWARM/template.ewp | 2007 +++++++++ .../SysTick_Delay_IT/EWARM/template.eww | 10 + .../SysTick/SysTick_Delay_IT/Inc/lib_conf.h | 66 + .../SysTick/SysTick_Delay_IT/Inc/main.h | 27 + .../SysTick/SysTick_Delay_IT/Inc/target_isr.h | 63 + .../SysTick/SysTick_Delay_IT/Inc/v_stdio.h | 19 + .../SysTick_Delay_IT/MDK-ARM/startup_target.s | 451 ++ .../SysTick_Delay_IT/MDK-ARM/template.uvoptx | 621 +++ .../SysTick_Delay_IT/MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../SysTick_Delay_IT/MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../SysTick/SysTick_Delay_IT/Src/main.c | 122 + .../SysTick/SysTick_Delay_IT/Src/target_isr.c | 307 ++ .../SysTick/SysTick_Delay_IT/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../SysTick_Delay_Polling/EWARM/template.ewd | 2741 ++++++++++++ .../SysTick_Delay_Polling/EWARM/template.ewp | 2007 +++++++++ .../SysTick_Delay_Polling/EWARM/template.eww | 10 + .../SysTick_Delay_Polling/Inc/lib_conf.h | 66 + .../SysTick/SysTick_Delay_Polling/Inc/main.h | 27 + .../SysTick_Delay_Polling/Inc/target_isr.h | 63 + .../SysTick_Delay_Polling/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 639 +++ .../MDK-ARM/template.uvprojx | 658 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../SysTick/SysTick_Delay_Polling/Src/main.c | 117 + .../SysTick_Delay_Polling/Src/target_isr.c | 303 ++ .../SysTick_Delay_Polling/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../TMR_32BitsBaseTimer_IT/EWARM/template.ewd | 2741 ++++++++++++ .../TMR_32BitsBaseTimer_IT/EWARM/template.ewp | 2007 +++++++++ .../TMR_32BitsBaseTimer_IT/EWARM/template.eww | 10 + .../TMR_32BitsBaseTimer_IT/Inc/lib_conf.h | 66 + .../TIMER/TMR_32BitsBaseTimer_IT/Inc/main.h | 27 + .../TMR_32BitsBaseTimer_IT/Inc/target_isr.h | 63 + .../TMR_32BitsBaseTimer_IT/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../TIMER/TMR_32BitsBaseTimer_IT/Src/main.c | 107 + .../TMR_32BitsBaseTimer_IT/Src/target_isr.c | 309 ++ .../TMR_32BitsBaseTimer_IT/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../EWARM/template.ewd | 2741 ++++++++++++ .../EWARM/template.ewp | 2007 +++++++++ .../EWARM/template.eww | 10 + .../TMR_ExternalClockSource_IT/Inc/lib_conf.h | 66 + .../TMR_ExternalClockSource_IT/Inc/main.h | 27 + .../Inc/target_isr.h | 63 + .../TMR_ExternalClockSource_IT/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../TMR_ExternalClockSource_IT/Src/main.c | 112 + .../Src/target_isr.c | 310 ++ .../TMR_ExternalClockSource_IT/Src/v_stdio.c | 54 + .../TinyADC/TinyADC/ECLIPSE/startup_target.S | 478 +++ .../TinyADC/ECLIPSE/template/.cproject | 226 + .../TinyADC/TinyADC/ECLIPSE/template/.project | 183 + .../TinyADC/ECLIPSE/template/Target_FLASH.ld | 183 + .../TinyADC/TinyADC/EWARM/startup_target.s | 500 +++ .../TinyADC/TinyADC/EWARM/target_flash.icf | 31 + .../TinyADC/TinyADC/EWARM/template.ewd | 2741 ++++++++++++ .../TinyADC/TinyADC/EWARM/template.ewp | 2007 +++++++++ .../TinyADC/TinyADC/EWARM/template.eww | 10 + .../Examples/TinyADC/TinyADC/Inc/lib_conf.h | 67 + .../Examples/TinyADC/TinyADC/Inc/main.h | 27 + .../Examples/TinyADC/TinyADC/Inc/target_isr.h | 63 + .../Examples/TinyADC/TinyADC/Inc/v_stdio.h | 19 + .../TinyADC/TinyADC/MDK-ARM/startup_target.s | 451 ++ .../TinyADC/TinyADC/MDK-ARM/template.uvoptx | 621 +++ .../TinyADC/TinyADC/MDK-ARM/template.uvprojx | 634 +++ .../TinyADC/MDK-ARMv4/startup_target.s | 451 ++ .../TinyADC/TinyADC/MDK-ARMv4/template.uvopt | 705 ++++ .../TinyADC/TinyADC/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/TinyADC/TinyADC/Src/main.c | 135 + .../Examples/TinyADC/TinyADC/Src/target_isr.c | 309 ++ .../Examples/TinyADC/TinyADC/Src/v_stdio.c | 54 + .../UART_StdPrint/ECLIPSE/startup_target.S | 478 +++ .../UART_StdPrint/ECLIPSE/template/.cproject | 226 + .../UART_StdPrint/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../UART/UART_StdPrint/EWARM/startup_target.s | 500 +++ .../UART/UART_StdPrint/EWARM/target_flash.icf | 31 + .../UART/UART_StdPrint/EWARM/template.ewd | 2741 ++++++++++++ .../UART/UART_StdPrint/EWARM/template.ewp | 2007 +++++++++ .../UART/UART_StdPrint/EWARM/template.eww | 10 + .../UART/UART_StdPrint/Inc/lib_conf.h | 66 + .../Examples/UART/UART_StdPrint/Inc/main.h | 27 + .../UART/UART_StdPrint/Inc/target_isr.h | 63 + .../Examples/UART/UART_StdPrint/Inc/v_stdio.h | 19 + .../UART_StdPrint/MDK-ARM/startup_target.s | 451 ++ .../UART_StdPrint/MDK-ARM/template.uvoptx | 621 +++ .../UART_StdPrint/MDK-ARM/template.uvprojx | 634 +++ .../UART_StdPrint/MDK-ARMv4/startup_target.s | 451 ++ .../UART_StdPrint/MDK-ARMv4/template.uvopt | 705 ++++ .../UART_StdPrint/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/UART/UART_StdPrint/Src/main.c | 91 + .../UART/UART_StdPrint/Src/target_isr.c | 304 ++ .../Examples/UART/UART_StdPrint/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../EWARM/startup_target.s | 500 +++ .../EWARM/target_flash.icf | 31 + .../UART_Tranmit_300bps/EWARM/template.ewd | 2741 ++++++++++++ .../UART_Tranmit_300bps/EWARM/template.ewp | 2007 +++++++++ .../UART_Tranmit_300bps/EWARM/template.eww | 10 + .../UART/UART_Tranmit_300bps/Inc/lib_conf.h | 66 + .../UART/UART_Tranmit_300bps/Inc/main.h | 27 + .../UART/UART_Tranmit_300bps/Inc/target_isr.h | 63 + .../UART/UART_Tranmit_300bps/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../UART/UART_Tranmit_300bps/Src/main.c | 105 + .../UART/UART_Tranmit_300bps/Src/target_isr.c | 304 ++ .../UART/UART_Tranmit_300bps/Src/v_stdio.c | 54 + .../UART_Tranmit_IT/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../UART_Tranmit_IT/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../UART_Tranmit_IT/EWARM/startup_target.s | 500 +++ .../UART_Tranmit_IT/EWARM/target_flash.icf | 31 + .../UART/UART_Tranmit_IT/EWARM/template.ewd | 2741 ++++++++++++ .../UART/UART_Tranmit_IT/EWARM/template.ewp | 2007 +++++++++ .../UART/UART_Tranmit_IT/EWARM/template.eww | 10 + .../UART/UART_Tranmit_IT/Inc/lib_conf.h | 66 + .../Examples/UART/UART_Tranmit_IT/Inc/main.h | 27 + .../UART/UART_Tranmit_IT/Inc/target_isr.h | 63 + .../UART/UART_Tranmit_IT/Inc/v_stdio.h | 19 + .../UART_Tranmit_IT/MDK-ARM/startup_target.s | 451 ++ .../UART_Tranmit_IT/MDK-ARM/template.uvoptx | 638 +++ .../UART_Tranmit_IT/MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../UART_Tranmit_IT/MDK-ARMv4/template.uvopt | 705 ++++ .../UART_Tranmit_IT/MDK-ARMv4/template.uvproj | 584 +++ .../Examples/UART/UART_Tranmit_IT/Src/main.c | 122 + .../UART/UART_Tranmit_IT/Src/target_isr.c | 328 ++ .../UART/UART_Tranmit_IT/Src/v_stdio.c | 54 + .../ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../UART_Transmit_IrDA/EWARM/startup_target.s | 500 +++ .../UART_Transmit_IrDA/EWARM/target_flash.icf | 31 + .../UART_Transmit_IrDA/EWARM/template.ewd | 2741 ++++++++++++ .../UART_Transmit_IrDA/EWARM/template.ewp | 2007 +++++++++ .../UART_Transmit_IrDA/EWARM/template.eww | 10 + .../UART/UART_Transmit_IrDA/Inc/lib_conf.h | 66 + .../UART/UART_Transmit_IrDA/Inc/main.h | 27 + .../UART/UART_Transmit_IrDA/Inc/target_isr.h | 63 + .../UART/UART_Transmit_IrDA/Inc/v_stdio.h | 19 + .../MDK-ARM/startup_target.s | 451 ++ .../MDK-ARM/template.uvoptx | 621 +++ .../MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../UART/UART_Transmit_IrDA/Src/main.c | 95 + .../UART/UART_Transmit_IrDA/Src/target_isr.c | 304 ++ .../UART/UART_Transmit_IrDA/Src/v_stdio.c | 54 + .../U32K_Receive_IT/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../U32K_Receive_IT/ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../U32K_Receive_IT/EWARM/startup_target.s | 500 +++ .../U32K_Receive_IT/EWARM/target_flash.icf | 31 + .../U32K_Receive_IT/EWARM/template.ewd | 2741 ++++++++++++ .../U32K_Receive_IT/EWARM/template.ewp | 2007 +++++++++ .../U32K_Receive_IT/EWARM/template.eww | 10 + .../UART32K/U32K_Receive_IT/Inc/lib_conf.h | 66 + .../UART32K/U32K_Receive_IT/Inc/main.h | 32 + .../UART32K/U32K_Receive_IT/Inc/target_isr.h | 63 + .../UART32K/U32K_Receive_IT/Inc/v_stdio.h | 19 + .../U32K_Receive_IT/MDK-ARM/startup_target.s | 451 ++ .../U32K_Receive_IT/MDK-ARM/template.uvoptx | 621 +++ .../U32K_Receive_IT/MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../U32K_Receive_IT/MDK-ARMv4/template.uvopt | 705 ++++ .../U32K_Receive_IT/MDK-ARMv4/template.uvproj | 584 +++ .../UART32K/U32K_Receive_IT/Src/main.c | 127 + .../UART32K/U32K_Receive_IT/Src/target_isr.c | 322 ++ .../UART32K/U32K_Receive_IT/Src/v_stdio.c | 54 + .../U32K_WakeUpSleep/ECLIPSE/startup_target.S | 478 +++ .../ECLIPSE/template/.cproject | 226 + .../ECLIPSE/template/.project | 183 + .../ECLIPSE/template/Target_FLASH.ld | 183 + .../U32K_WakeUpSleep/EWARM/startup_target.s | 500 +++ .../U32K_WakeUpSleep/EWARM/target_flash.icf | 31 + .../U32K_WakeUpSleep/EWARM/template.ewd | 2741 ++++++++++++ .../U32K_WakeUpSleep/EWARM/template.ewp | 2007 +++++++++ .../U32K_WakeUpSleep/EWARM/template.eww | 10 + .../UART32K/U32K_WakeUpSleep/Inc/lib_conf.h | 66 + .../UART32K/U32K_WakeUpSleep/Inc/main.h | 33 + .../UART32K/U32K_WakeUpSleep/Inc/target_isr.h | 63 + .../UART32K/U32K_WakeUpSleep/Inc/v_stdio.h | 19 + .../U32K_WakeUpSleep/MDK-ARM/startup_target.s | 451 ++ .../U32K_WakeUpSleep/MDK-ARM/template.uvoptx | 621 +++ .../U32K_WakeUpSleep/MDK-ARM/template.uvprojx | 634 +++ .../MDK-ARMv4/startup_target.s | 451 ++ .../U32K_WakeUpSleep/MDK-ARMv4/template.uvopt | 705 ++++ .../MDK-ARMv4/template.uvproj | 584 +++ .../UART32K/U32K_WakeUpSleep/Src/main.c | 151 + .../UART32K/U32K_WakeUpSleep/Src/target_isr.c | 322 ++ .../UART32K/U32K_WakeUpSleep/Src/v_stdio.c | 54 + bsp/Vango-V85xxp/V85X3P_Lib_V1.1/IAR_Kill.bat | 8 + .../CMSIS/CMSIS_Include/cmsis_armcc.h | 865 ++++ .../CMSIS/CMSIS_Include/cmsis_armclang.h | 1869 +++++++++ .../CMSIS/CMSIS_Include/cmsis_compiler.h | 266 ++ .../Libraries/CMSIS/CMSIS_Include/cmsis_gcc.h | 2085 ++++++++++ .../CMSIS/CMSIS_Include/cmsis_iccarm.h | 935 +++++ .../CMSIS/CMSIS_Include/cmsis_version.h | 39 + .../CMSIS/CMSIS_Include/core_armv8mbl.h | 1918 +++++++++ .../CMSIS/CMSIS_Include/core_armv8mml.h | 2927 +++++++++++++ .../Libraries/CMSIS/CMSIS_Include/core_cm0.h | 949 +++++ .../CMSIS/CMSIS_Include/core_cm0plus.h | 1083 +++++ .../Libraries/CMSIS/CMSIS_Include/core_cm1.h | 976 +++++ .../Libraries/CMSIS/CMSIS_Include/core_cm23.h | 1993 +++++++++ .../Libraries/CMSIS/CMSIS_Include/core_cm3.h | 1941 +++++++++ .../Libraries/CMSIS/CMSIS_Include/core_cm33.h | 3002 ++++++++++++++ .../Libraries/CMSIS/CMSIS_Include/core_cm4.h | 2129 ++++++++++ .../Libraries/CMSIS/CMSIS_Include/core_cm7.h | 2671 ++++++++++++ .../CMSIS/CMSIS_Include/core_sc000.h | 1022 +++++ .../CMSIS/CMSIS_Include/core_sc300.h | 1915 +++++++++ .../Libraries/CMSIS/CMSIS_Include/mpu_armv7.h | 270 ++ .../Libraries/CMSIS/CMSIS_Include/mpu_armv8.h | 333 ++ .../CMSIS/CMSIS_Include/tz_context.h | 70 + .../Libraries/CMSIS/device/lib_CodeRAM.c | 33 + .../Libraries/CMSIS/device/lib_LoadNVR.c | 700 ++++ .../Libraries/CMSIS/device/lib_cortex.c | 198 + .../Libraries/CMSIS/device/system_target.c | 81 + .../Libraries/CMSIS/include/lib_CodeRAM.h | 35 + .../Libraries/CMSIS/include/lib_LoadNVR.h | 235 ++ .../Libraries/CMSIS/include/lib_cortex.h | 49 + .../Libraries/CMSIS/include/system_target.h | 41 + .../Libraries/CMSIS/include/target.h | 2799 +++++++++++++ .../Libraries/CMSIS/include/type_def.h | 120 + .../Libraries/Config/ECLIPSE/Target_FLASH.ld | 183 + .../Libraries/Config/ECLIPSE/startup_target.S | 478 +++ .../Config/ECLIPSE/startup_target_noload.S | 477 +++ .../Libraries/Config/EWARM/startup_target.s | 500 +++ .../Config/EWARM/startup_target_noload.s | 499 +++ .../Libraries/Config/EWARM/target_flash.icf | 31 + .../Libraries/Config/MDK-ARM/startup_target.s | 451 ++ .../Config/MDK-ARM/startup_target_noload.s | 451 ++ .../Config/MDK-ARMv4/startup_target.s | 451 ++ .../Config/MDK-ARMv4/startup_target_noload.s | 451 ++ .../Libraries/Lib_Driver/inc/lib_adc.h | 313 ++ .../Libraries/Lib_Driver/inc/lib_adc_tiny.h | 81 + .../Libraries/Lib_Driver/inc/lib_ana.h | 118 + .../Libraries/Lib_Driver/inc/lib_clk.h | 339 ++ .../Libraries/Lib_Driver/inc/lib_cmp.h | 205 + .../Libraries/Lib_Driver/inc/lib_crypt.h | 107 + .../Libraries/Lib_Driver/inc/lib_dma.h | 267 ++ .../Libraries/Lib_Driver/inc/lib_flash.h | 159 + .../Libraries/Lib_Driver/inc/lib_gpio.h | 215 + .../Libraries/Lib_Driver/inc/lib_i2c.h | 164 + .../Libraries/Lib_Driver/inc/lib_iso7816.h | 174 + .../Libraries/Lib_Driver/inc/lib_lcd.h | 139 + .../Libraries/Lib_Driver/inc/lib_misc.h | 85 + .../Libraries/Lib_Driver/inc/lib_pmu.h | 367 ++ .../Libraries/Lib_Driver/inc/lib_pwm.h | 258 ++ .../Libraries/Lib_Driver/inc/lib_rtc.h | 226 + .../Libraries/Lib_Driver/inc/lib_spi.h | 212 + .../Libraries/Lib_Driver/inc/lib_tmr.h | 68 + .../Libraries/Lib_Driver/inc/lib_u32k.h | 160 + .../Libraries/Lib_Driver/inc/lib_uart.h | 172 + .../Libraries/Lib_Driver/inc/lib_version.h | 36 + .../Libraries/Lib_Driver/inc/lib_wdt.h | 47 + .../Libraries/Lib_Driver/src/lib_adc.c | 988 +++++ .../Libraries/Lib_Driver/src/lib_adc_tiny.c | 176 + .../Libraries/Lib_Driver/src/lib_ana.c | 160 + .../Libraries/Lib_Driver/src/lib_clk.c | 674 +++ .../Libraries/Lib_Driver/src/lib_cmp.c | 583 +++ .../Libraries/Lib_Driver/src/lib_crypt.c | 226 + .../Libraries/Lib_Driver/src/lib_dma.c | 473 +++ .../Libraries/Lib_Driver/src/lib_flash.c | 441 ++ .../Libraries/Lib_Driver/src/lib_gpio.c | 437 ++ .../Libraries/Lib_Driver/src/lib_i2c.c | 694 ++++ .../Libraries/Lib_Driver/src/lib_iso7816.c | 405 ++ .../Libraries/Lib_Driver/src/lib_lcd.c | 255 ++ .../Libraries/Lib_Driver/src/lib_misc.c | 255 ++ .../Libraries/Lib_Driver/src/lib_pmu.c | 1214 ++++++ .../Libraries/Lib_Driver/src/lib_pwm.c | 530 +++ .../Libraries/Lib_Driver/src/lib_rtc.c | 793 ++++ .../Libraries/Lib_Driver/src/lib_spi.c | 429 ++ .../Libraries/Lib_Driver/src/lib_tmr.c | 178 + .../Libraries/Lib_Driver/src/lib_u32k.c | 309 ++ .../Libraries/Lib_Driver/src/lib_uart.c | 372 ++ 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487 +++ .../libcpu/arm/cortex-m7/context_gcc.S | 245 ++ .../libcpu/arm/cortex-m7/context_iar.S | 253 ++ .../libcpu/arm/cortex-m7/context_rvds.S | 253 ++ .../rtthread/libcpu/arm/cortex-m7/cpu_cache.c | 89 + .../rtthread/libcpu/arm/cortex-m7/cpuport.c | 487 +++ .../rtthread/libcpu/arm/cortex-r4/armv7.h | 56 + .../libcpu/arm/cortex-r4/context_ccs.asm | 260 ++ .../libcpu/arm/cortex-r4/context_gcc.S | 251 ++ .../EWARM/rtthread/libcpu/arm/cortex-r4/cpu.c | 95 + .../rtthread/libcpu/arm/cortex-r4/interrupt.c | 106 + .../rtthread/libcpu/arm/cortex-r4/stack.c | 83 + .../libcpu/arm/cortex-r4/start_ccs.asm | 552 +++ .../rtthread/libcpu/arm/cortex-r4/start_gcc.S | 486 +++ .../rtthread/libcpu/arm/cortex-r4/trap.c | 148 + .../libcpu/arm/cortex-r4/vector_ccs.asm | 34 + .../libcpu/arm/cortex-r4/vector_gcc.S | 39 + .../libcpu/risc-v/bumblebee/interrupt_gcc.S | 129 + .../libcpu/risc-v/common/context_gcc.S | 212 + .../rtthread/libcpu/risc-v/common/cpuport.c | 129 + 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.../template/EWARM/rtthread/src/idle.c | 281 ++ .../template/EWARM/rtthread/src/ipc.c | 2328 +++++++++++ .../template/EWARM/rtthread/src/irq.c | 113 + .../template/EWARM/rtthread/src/kservice.c | 1397 +++++++ .../template/EWARM/rtthread/src/mem.c | 698 ++++ .../template/EWARM/rtthread/src/memheap.c | 717 ++++ .../template/EWARM/rtthread/src/mempool.c | 454 ++ .../template/EWARM/rtthread/src/object.c | 518 +++ .../template/EWARM/rtthread/src/scheduler.c | 437 ++ .../template/EWARM/rtthread/src/slab.c | 937 +++++ .../template/EWARM/rtthread/src/thread.c | 802 ++++ .../template/EWARM/rtthread/src/timer.c | 721 ++++ .../template/template/EWARM/startup_target.s | 500 +++ .../template/template/EWARM/target_flash.icf | 31 + .../template/template/EWARM/template.ewd | 2741 ++++++++++++ .../template/template/EWARM/template.ewp | 2069 +++++++++ .../template/template/EWARM/template.eww | 10 + .../template/template/Inc/lib_conf.h | 66 + .../Project_RT/template/template/Inc/main.h | 27 + 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bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvproj create mode 100644 bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/main.c create mode 100644 bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/target_isr.c create mode 100644 bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/v_stdio.c create mode 100644 bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Tmp_Kill.bat create mode 100644 bsp/Vango-V85xxp/V85X3P_Lib_V1.1/keil_Kill.bat diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md index b64136d96d..4df34e2e1b 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md @@ -1,11 +1,8 @@ ## 拉å–/åˆå¹¶è¯·æ±‚æ述： [ -这段方括å·é‡Œçš„内容是您**必须填写并替æ¢æŽ‰**的，å¦åˆ™PRä¸å¯èƒ½è¢«åˆå¹¶ã€‚**方括å·å¤–é¢çš„内容ä¸éœ€è¦ä¿®æ”¹ï¼Œä½†è¯·ä»”细阅读。** - -请在这里填写您的PRæ述，å¯ä»¥åŒ…括以下之一的内容：为什么æ交这份PR；解决的问题是什么，你的解决方案是什么； - -并确认并列出已ç»åœ¨ä»€ä¹ˆæƒ…况或æ¿å¡ä¸Šè¿›è¡Œäº†æµ‹è¯•ã€‚ +添加Vango V85xxp 对应RT-thread，实机测试OK，使用keil编译。 +åŽç»­æ·»åŠ gcc版本rt-thread é€‚é… ] 以下的内容ä¸åº”该在æ交PR时的message修改，修改下述message，PR会被直接关闭。请在æ交PRåŽï¼Œæµè§ˆå™¨æŸ¥çœ‹PR并对以下检查项é€é¡¹check，没问题åŽé€æ¡åœ¨é¡µé¢ä¸Šæ‰“钩。 @@ -14,17 +11,17 @@ 必须选择一项: -- [ ] 本拉å–/åˆå¹¶è¯·æ±‚是一个è‰ç¨¿ç‰ˆæœ¬ +- [x] 本拉å–/åˆå¹¶è¯·æ±‚是一个è‰ç¨¿ç‰ˆæœ¬ - [ ] 本拉å–/åˆå¹¶è¯·æ±‚是一个æˆç†Ÿç‰ˆæœ¬ ### 代ç è´¨é‡ï¼š 我在这个拉å–/åˆå¹¶è¯·æ±‚中已ç»è€ƒè™‘了: -- [ ] å·²ç»ä»”细查看过代ç æ”¹åŠ¨çš„对比 -- [ ] 代ç é£Žæ ¼æ­£ç¡®ï¼ŒåŒ…括缩进空格，命ååŠå…¶ä»–风格 -- [ ] 没有垃圾代ç ï¼Œä»£ç å°½é‡ç²¾ç®€ï¼Œä¸åŒ…å«`#if 0`代ç ï¼Œä¸åŒ…å«å·²ç»è¢«æ³¨é‡Šäº†çš„ä»£ç  -- [ ] 所有å˜æ›´å‡æœ‰åŽŸå› åŠåˆç†çš„，并且ä¸ä¼šå½±å“到其他软件组件代ç æˆ– -- [ ] 对难懂代ç å‡æ供对应的注释 -- [ ] 本拉å–/åˆå¹¶è¯·æ±‚代ç æ˜¯é«˜è´¨é‡çš„ -- [ ] 本拉å–/åˆå¹¶ç¬¦åˆ[RT-Thread代ç è§„范](../documentation/coding_style_cn.md) +- [x] å·²ç»ä»”细查看过代ç æ”¹åŠ¨çš„对比 +- [x] 代ç é£Žæ ¼æ­£ç¡®ï¼ŒåŒ…括缩进空格，命ååŠå…¶ä»–风格 +- [x] 没有垃圾代ç ï¼Œä»£ç å°½é‡ç²¾ç®€ï¼Œä¸åŒ…å«`#if 0`代ç ï¼Œä¸åŒ…å«å·²ç»è¢«æ³¨é‡Šäº†çš„ä»£ç  +- [x] 所有å˜æ›´å‡æœ‰åŽŸå› åŠåˆç†çš„，并且ä¸ä¼šå½±å“到其他软件组件代ç æˆ– +- [x] 对难懂代ç å‡æ供对应的注释 +- [x] 本拉å–/åˆå¹¶è¯·æ±‚代ç æ˜¯é«˜è´¨é‡çš„ +- [x] 本拉å–/åˆå¹¶ç¬¦åˆ[RT-Thread代ç è§„范](../documentation/coding_style_cn.md) diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Eclipse_Kill.bat b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Eclipse_Kill.bat new file mode 100644 index 0000000000..2165bccdc6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Eclipse_Kill.bat @@ -0,0 +1,11 @@ +@echo off + +for /r %%d in (.) do rd /s /q "%%d\.settings" 2>nul +for /r %%d in (.) do rd /s /q "%%d\Debug" 2>nul +for /r %%d in (.) do rd /s /q "%%d\JLink" 2>nul +for /r %%d in (.) do rd /s /q "%%d\Objects" 2>nul +for /r %%d in (.) do rd /s /q "%%d\Startup" 2>nul +for /r %%d in (.) do rd /s /q "%%d\StdDrivers" 2>nul +for /r %%d in (.) do rd /s /q "%%d\User" 2>nul + +exit diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.ewd @@ -0,0 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM 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+ + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..2b8eedbbbd --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/template.uvoptx @@ -0,0 +1,677 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + + 1 + 0 + 0X4001425c + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 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+ 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..5cbbcc7403 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 166 + 166 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/main.c new file mode 100644 index 0000000000..77074770aa --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/main.c @@ -0,0 +1,189 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; +volatile int16_t bsrc[256][4]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + DMA_InitType DMA_InitStruct; + GPIO_InitType InitStruct; + TMR_InitType TMR_InitStruct; + uint32_t i, nCount; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + InitStruct.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9|GPIO_Pin_10|GPIO_Pin_11; + GPIOA_Init(GPIOA, &InitStruct); + + /* Timer0 initialization: + - Clock source: internal clock(APB clock) + - Overflow interval: 1ms */ + TMR_DeInit(TMR0); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = CLK_GetPCLKFreq()/(128*50) - 1; + TMR_Init(TMR0, &TMR_InitStruct); + /* Enable Timer0 */ + TMR_Cmd(TMR0, ENABLE); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_AC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_2; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_TMR0; + ADC_InitStruct.Channel = ADC_CHANNEL_CH3 \ + | ADC_CHANNEL_CH4 \ + | ADC_CHANNEL_CH5 \ + | ADC_CHANNEL_CH6; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_CH3 \ + | ADC_CHANNEL_CH4 \ + | ADC_CHANNEL_CH5 \ + | ADC_CHANNEL_CH6; + + ADC_Init(&ADC_InitStruct); + + DMA_DeInit(DMA_CHANNEL_0); + DMA_InitStruct.SrcAddr = (uint32_t)&ANA->ADCDATADMA; + DMA_InitStruct.DestAddr = (uint32_t)&bsrc[0]; + DMA_InitStruct.FrameLen = 256 - 1; + DMA_InitStruct.PackLen = 4 - 1; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_InitStruct.ReqSrc = DMA_REQSRC_ADC; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FEND; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FIX; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_HWORD; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_0); + + DMA_Cmd(DMA_CHANNEL_0, ENABLE); + + ADC_Cmd(ENABLE); + + while(1) + { + if(DMA_GetINTStatus(DMA_INTSTS_C0FE)) + { + DMA_ClearINTStatus(DMA_INTSTS_C0FE); + break; + } + } + + DMA_Cmd(DMA_CHANNEL_0, DISABLE); + ADC_Cmd(DISABLE); + + + printf("CH3\tCH4\tCH5\tCH6\t\r\n"); + for (i=0; i<256; i++) + { + printf("%d\t", bsrc[i][0]); + printf("%d\t", bsrc[i][1]); + printf("%d\t", bsrc[i][2]); + printf("%d\r\n", bsrc[i][3]); + } + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_AC_DMA/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.cspy.bat b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.cspy.bat new file mode 100644 index 0000000000..798f69bc13 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"D:\ProgramFiles\IAR\common\bin\cspybat" -f "F:\10IC\02IC_SPVD\DriveLibrary\trunk\Project\Puma_Series\PumaA\V85X3P_Lib_V1.1\Examples\ADC\ADC_BAT\EWARM\settings\template.Debug.general.xcl" --backend -f "F:\10IC\02IC_SPVD\DriveLibrary\trunk\Project\Puma_Series\PumaA\V85X3P_Lib_V1.1\Examples\ADC\ADC_BAT\EWARM\settings\template.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"D:\ProgramFiles\IAR\common\bin\cspybat" -f "F:\10IC\02IC_SPVD\DriveLibrary\trunk\Project\Puma_Series\PumaA\V85X3P_Lib_V1.1\Examples\ADC\ADC_BAT\EWARM\settings\template.Debug.general.xcl" "--debug_file=%1" --backend -f "F:\10IC\02IC_SPVD\DriveLibrary\trunk\Project\Puma_Series\PumaA\V85X3P_Lib_V1.1\Examples\ADC\ADC_BAT\EWARM\settings\template.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.driver.xcl b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.driver.xcl new file mode 100644 index 0000000000..f4e544e7e0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.driver.xcl @@ -0,0 +1,39 @@ +"--endian=little" + +"--cpu=Cortex-M0" + +"--fpu=None" + +"-p" + +"D:\ProgramFiles\IAR\arm\CONFIG\debugger\VANGO\V85X3P.ddf" + +"--drv_verify_download" + +"--semihosting=none" + +"--device=V85X3P" + +"--multicore_nr_of_cores=1" + +"--jet_probe=cmsisdap" + +"--jet_standard_reset=2,300,200" + +"--reset_style=\"0,-,0,Disabled__no_reset_\"" + +"--reset_style=\"1,-,0,Software\"" + +"--reset_style=\"2,-,1,Hardware\"" + +"--reset_style=\"3,-,0,Core\"" + +"--reset_style=\"4,-,0,System\"" + +"--drv_interface=SWD" + +"--drv_catch_exceptions=0x7f0" + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.general.xcl b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.general.xcl new file mode 100644 index 0000000000..8a780c3cf4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.Debug.general.xcl @@ -0,0 +1,13 @@ +"D:\ProgramFiles\IAR\arm\bin\armproc.dll" + +"D:\ProgramFiles\IAR\arm\bin\armJET.dll" + +"F:\10IC\02IC_SPVD\DriveLibrary\trunk\Project\Puma_Series\PumaA\V85X3P_Lib_V1.1\Examples\ADC\ADC_BAT\EWARM\Debug\Exe\template.out" + +--plugin "D:\ProgramFiles\IAR\arm\bin\armbat.dll" + +--flash_loader "D:\ProgramFiles\IAR\arm\config\flashloader\VANGO\FlashV85X3P.board" + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.crun b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.crun new file mode 100644 index 0000000000..ef39dce8f4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.crun @@ -0,0 +1,16 @@ + + + + 1 + + + * + * + * + 0 + 1 + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.dbgdt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.dbgdt new file mode 100644 index 0000000000..e068f91d1e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.dbgdt @@ -0,0 +1,5 @@ + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.dni b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.dni new file mode 100644 index 0000000000..a76eab25fe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.dni @@ -0,0 +1,24 @@ +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Disassemble mode] +mode=0 +[Breakpoints2] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 +[PlDriver] +MemConfigValue=D:\ProgramFiles\IAR\arm\CONFIG\debugger\VANGO\V85X3P.ddf +[Jet] +DisableInterrupts=0 +MultiCoreRunAll=0 +[ArmDriver] +EnableCache=1 diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.wsdt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.wsdt new file mode 100644 index 0000000000..71ae0a563b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.wsdt @@ -0,0 +1,156 @@ + + + + + + template/Debug + + + + + + 20 + 1365 + + + + 124 + 27 + 27 + 27 + + + + 20 + 1023 + 273 + 68 + + + + + + + TabID-11804-16325 + Workspace + Workspace + + + template + template/User + + + + + 0 + + + + + TabID-22552-16329 + Debug Log + Debug-Log + + + + TabID-10235-16355 + Build + Build + + + + 1 + + + + + + TextEditor + $WS_DIR$\..\Src\main.c + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + 0 + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + + + + + + + + -2 + -2 + 457 + 198 + -2 + -2 + 200 + 200 + 140449 + 285714 + 140449 + 655714 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1426 + -2 + -2 + 1428 + 200 + 1002809 + 285714 + 140449 + 285714 + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.wspos b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.wspos new file mode 100644 index 0000000000..4c46fbc5b8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/settings/template.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 2102 182 3542 941 1 diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 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+ + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 0 + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..4cb5a9a386 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/template.uvoptx @@ -0,0 +1,677 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + + 1 + 0 + 0x80C00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + 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0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..cc285306ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..5cbbcc7403 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 166 + 166 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/main.c new file mode 100644 index 0000000000..f18696d438 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/main.c @@ -0,0 +1,205 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nResult; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_DC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_Init(&ADC_InitStruct); + + ADC_Cmd(ENABLE); + ADC_StartManual(); + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BAT1); + if(ADC_CalculateValue(ADC_5V_BAT1_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BAT1 is %.3fV.\t", (float)nResult/1000.0); + } + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC); + if(ADC_CalculateValue(ADC_5V_BATRTC_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BATRTC is %.3fV.\r\n", (float)nResult/1000.0); + } + } + + ADC_Cmd(DISABLE); + + /* ADC Init */ + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_SITV(1); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<32; ) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BAT1); + if(ADC_CalculateValue(ADC_5V_BAT1_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BAT1 is %.3fV.\t", (float)nResult/1000.0); + } + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC); + if(ADC_CalculateValue(ADC_5V_BATRTC_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BATRTC is %.3fV.\r\n", (float)nResult/1000.0); + } + } + else + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + + WDT_Clear(); + } + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + 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--- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/main.h new file mode 100644 index 0000000000..00abca75cd --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..73dbac0a41 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9cd514f3b4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/template.uvoptx @@ -0,0 +1,677 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + + 1 + 0 + 0x80C00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..cc285306ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..fd927bced6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 139 + 139 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/main.c new file mode 100644 index 0000000000..e67d353b7d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/main.c @@ -0,0 +1,169 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nResult; + + test_success = 0; + + Clock_Init(); + + Stdio_Init(); + printf("Start test.\r\n"); + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_DC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_InitStruct.Channel = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_SITV(1); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<32; ) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BAT1); + if(ADC_CalculateValue(ADC_5V_BAT1_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BAT1 is %.3fV.\t", (float)nResult/1000.0); + } + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC); + if(ADC_CalculateValue(ADC_5V_BATRTC_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BATRTC is %.3fV.\r\n", (float)nResult/1000.0); + } + } + else + { + ADC_SoftReset(&ADC_InitStruct); + } + WDT_Clear(); + } + + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Auto/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.ewd @@ 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+ + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/main.h new file mode 100644 index 0000000000..00abca75cd --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..4cb5a9a386 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/template.uvoptx @@ -0,0 +1,677 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + 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+ 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..cc285306ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..7734b83d14 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 134 + 134 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/main.c new file mode 100644 index 0000000000..2059c7716e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/main.c @@ -0,0 +1,165 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; +#include "target.h" // Device header + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nResult; + + test_success = 0; + + Clock_Init(); + + Stdio_Init(); + printf("Start test.\r\n"); + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_DC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_Init(&ADC_InitStruct); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<32; i++) + { + ADC_StartManual(); + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BAT1); + if(ADC_CalculateValue(ADC_5V_BAT1_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BAT1 is %.3fV.\t", (float)nResult/1000.0); + } + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC); + if(ADC_CalculateValue(ADC_5V_BATRTC_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BATRTC is %.3fV.\r\n", (float)nResult/1000.0); + } + } + } + + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_BAT_Manual/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + 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b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..aa0520dab8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/template.uvoptx @@ -0,0 +1,677 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + + 1 + 0 + 0x80C48 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..358f8e65ff --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 145 + 145 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..fd25a18c3c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/main.c new file mode 100644 index 0000000000..25cb43bc74 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/main.c @@ -0,0 +1,173 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + GPIO_InitType InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nResult; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + InitStruct.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_11; + GPIOA_Init(GPIOA, &InitStruct); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_DC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_2; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_InitStruct.Channel = ADC_CHANNEL_CH3|ADC_CHANNEL_CH6; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_CH3|ADC_CHANNEL_CH6; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_CH3; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_SITV(1); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<10; ) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_CH3); + if(ADC_CalculateValue(ADC_3V_ADCCHx_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("CH3 is %d, %.3fV\t", ADCData, (float)nResult/1000.0); + } + + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_CH6); + if(ADC_CalculateValue(ADC_3V_ADCCHx_NODIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("CH6 is %d, %.3fV\r\n", ADCData, (float)nResult/1000.0); + } + } + else + { + ADC_SoftReset(&ADC_InitStruct); + } + WDT_Clear(); + } + + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_DC/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 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+ + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 0 + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..f1d02e8ac6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/template.uvoptx @@ -0,0 +1,682 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + 7 + 1 + ADCData + + + + + 1 + 0 + 0x80C00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + 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+ + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..ec7f597d5f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 233 + 233 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/main.c new file mode 100644 index 0000000000..15e86a3e2c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/main.c @@ -0,0 +1,261 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + ADCTHD_InitType ADC_THDStruct; + GPIO_InitType InitStruct; + int16_t ADCData[4]; + int16_t nResult; + uint32_t nCount; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + InitStruct.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; + GPIOA_Init(GPIOA, &InitStruct); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_DC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_BAT1 \ + | ADC_CHANNEL_BATRTC \ + | ADC_CHANNEL_CH3 \ + | ADC_CHANNEL_CH4; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_BAT1 \ + | ADC_CHANNEL_BATRTC \ + | ADC_CHANNEL_CH3 \ + | ADC_CHANNEL_CH4; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_Init(&ADC_InitStruct); + + ADC_Cmd(ENABLE); + + /* Manual mode */ + ADC_StartManual(); + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + ADCData[0] = ADC_GetADCConversionValue(ADC_CHANNEL_BAT1); + if(ADC_CalculateValue(ADC_5V_BAT1_RESDIV, ADCData[0], &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BAT1 is 0x%X %.3fV.\r\n", ADCData[0], (float)nResult/1000.0); + } + ADCData[1] = ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC); + if(ADC_CalculateValue(ADC_5V_BATRTC_RESDIV, ADCData[1], &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BATRTC is 0x%X %.3fV.\r\n", ADCData[1], (float)nResult/1000.0); + } + ADCData[2] = ADC_GetADCConversionValue(ADC_CHANNEL_CH4); + if(ADC_CalculateValue(ADC_5V_ADCCHx_NODIV, ADCData[2], &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("CH4 is 0x%X %.3fC.\r\n", ADCData[2], (float)nResult/1000.0); + } + ADCData[3] = ADC_GetADCConversionValue(ADC_CHANNEL_CH3); + if(ADC_CalculateValue(ADC_5V_ADCCHx_NODIV, ADCData[3], &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("CH3 is 0x%X %.3fV.\r\n", ADCData[3], (float)nResult/1000.0); + } + } + + ADC_Cmd(DISABLE); + + ADC_THDStructInit(&ADC_THDStruct); + ADC_THDStruct.THDChannel = ADC_THDCHANNEL0; + ADC_THDStruct.THDSource = ADC_CHANNEL_BAT1; + ADC_THDStruct.TriggerSel = ADC_THDSEL_RISING; + ADC_THDStruct.LowerTHD = (ADCData[0]>>8)-0x10; + ADC_THDStruct.UpperTHD = (ADCData[0]>>8)+0x10; + if(ADC_THDStruct.UpperTHD&0x80) + { + ADC_THDStruct.UpperTHD = 0x7F; + } + ADC_THDInit(&ADC_THDStruct); + + ADC_THDStruct.THDChannel = ADC_THDCHANNEL1; + ADC_THDStruct.THDSource = ADC_CHANNEL_BATRTC; + ADC_THDStruct.TriggerSel = ADC_THDSEL_RISING; + ADC_THDStruct.LowerTHD = (ADCData[1]>>8)-0x10; + ADC_THDStruct.UpperTHD = (ADCData[1]>>8)+0x10; + if(ADC_THDStruct.UpperTHD&0x80) + { + ADC_THDStruct.UpperTHD = 0x7F; + } + ADC_THDInit(&ADC_THDStruct); + + ADC_THDStruct.THDChannel = ADC_THDCHANNEL2; + ADC_THDStruct.THDSource = ADC_CHANNEL_CH4; + ADC_THDStruct.TriggerSel = ADC_THDSEL_RISING; + ADC_THDStruct.LowerTHD = (ADCData[2]>>8)-0x10; + ADC_THDStruct.UpperTHD = (ADCData[2]>>8)+0x10; + if(ADC_THDStruct.UpperTHD&0x80) + { + ADC_THDStruct.UpperTHD = 0x7F; + } + ADC_THDInit(&ADC_THDStruct); + + ADC_THDStruct.THDChannel = ADC_THDCHANNEL3; + ADC_THDStruct.THDSource = ADC_CHANNEL_CH3; + ADC_THDStruct.TriggerSel = ADC_THDSEL_RISING; + ADC_THDStruct.LowerTHD = (ADCData[3]>>8)-0x10; + ADC_THDStruct.UpperTHD = (ADCData[3]>>8)+0x10; + if(ADC_THDStruct.UpperTHD&0x80) + { + ADC_THDStruct.UpperTHD = 0x7F; + } + ADC_THDInit(&ADC_THDStruct); + + /* Auto mode */ + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_SITV(1); + + ADC_ClearINTStatus(ADC_INTSTS_UPPER_TH3 | ADC_INTSTS_LOWER_TH3 \ + | ADC_INTSTS_UPPER_TH2 | ADC_INTSTS_LOWER_TH2 \ + | ADC_INTSTS_UPPER_TH1 | ADC_INTSTS_LOWER_TH1 \ + | ADC_INTSTS_UPPER_TH0 | ADC_INTSTS_LOWER_TH0); + ADC_INTConfig(ADC_INT_UPPER_TH3 | ADC_INT_LOWER_TH3 \ + | ADC_INT_UPPER_TH2 | ADC_INT_LOWER_TH2 \ + | ADC_INT_UPPER_TH1 | ADC_INT_LOWER_TH1 \ + | ADC_INT_UPPER_TH0 | ADC_INT_LOWER_TH0, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 0); + + ADC_LowerTHDCmd(ADC_THDCHANNEL0, ENABLE); + ADC_UpperTHDCmd(ADC_THDCHANNEL0, ENABLE); + ADC_LowerTHDCmd(ADC_THDCHANNEL1, ENABLE); + ADC_UpperTHDCmd(ADC_THDCHANNEL1, ENABLE); + ADC_LowerTHDCmd(ADC_THDCHANNEL2, ENABLE); + ADC_UpperTHDCmd(ADC_THDCHANNEL2, ENABLE); + ADC_LowerTHDCmd(ADC_THDCHANNEL3, ENABLE); + ADC_UpperTHDCmd(ADC_THDCHANNEL3, ENABLE); + ADC_Cmd(ENABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/target_isr.c new file mode 100644 index 0000000000..e5046cb0fa --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/target_isr.c @@ -0,0 +1,344 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if(ADC_GetINTStatus(ADC_INTSTS_UPPER_TH0)) + { + ADC_ClearINTStatus(ADC_INTSTS_UPPER_TH0); + printf("UPPER trigger, BAT1 ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_BAT1)); + } + if(ADC_GetINTStatus(ADC_INTSTS_LOWER_TH0)) + { + ADC_ClearINTStatus(ADC_INTSTS_LOWER_TH0); + printf("LOWER trigger, BAT1 ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_BAT1)); + } + if(ADC_GetINTStatus(ADC_INTSTS_UPPER_TH1)) + { + ADC_ClearINTStatus(ADC_INTSTS_UPPER_TH1); + printf("UPPER trigger,BATRTC ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC)); + } + if(ADC_GetINTStatus(ADC_INTSTS_LOWER_TH1)) + { + ADC_ClearINTStatus(ADC_INTSTS_LOWER_TH1); + printf("LOWER trigger, BATRTC ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC)); + } + if(ADC_GetINTStatus(ADC_INTSTS_UPPER_TH2)) + { + ADC_ClearINTStatus(ADC_INTSTS_UPPER_TH2); + printf("UPPER trigger,CH4 ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_CH4)); + } + if(ADC_GetINTStatus(ADC_INTSTS_LOWER_TH2)) + { + ADC_ClearINTStatus(ADC_INTSTS_LOWER_TH2); + printf("LOWER trigger, CH4 ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_CH4)); + } + if(ADC_GetINTStatus(ADC_INTSTS_UPPER_TH3)) + { + ADC_ClearINTStatus(ADC_INTSTS_UPPER_TH3); + printf("UPPER trigger, CH3 ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_CH3)); + } + if(ADC_GetINTStatus(ADC_INTSTS_LOWER_TH3)) + { + ADC_ClearINTStatus(ADC_INTSTS_LOWER_TH3); + printf("LOWER trigger, CH3 ADADATA: %X\r\n",ADC_GetADCConversionValue(ADC_CHANNEL_CH3)); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_THD/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.ewd 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..f469669280 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/template.uvoptx @@ -0,0 +1,669 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..cc285306ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..5998993593 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 151 + 151 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/main.c new file mode 100644 index 0000000000..7b0f7ff347 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/main.c @@ -0,0 +1,188 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nTemper; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_TEMP; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_LOW; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_TEMP; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_TEMP; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_NONE; + ADC_Init(&ADC_InitStruct); + + ADC_Cmd(ENABLE); + ADC_StartManual(); + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + if(ADC_CalculateValue(ADC_TEMP, ADCData, &nTemper)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("Temperature is %d %.2f.\r\n", ADCData, (float)nTemper/256.0); + } + } + + ADC_Cmd(DISABLE); + + /* ADC Init */ + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_SITV(1); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<16; ) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + if(ADC_CalculateValue(ADC_TEMP, ADCData, &nTemper)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("Temperature is %d %.2f.\r\n", ADCData, (float)nTemper/256.0); + } + } + else + { + ADC_SoftReset(&ADC_InitStruct); + } + WDT_Clear(); + } + + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..45174f819a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/template.uvoptx @@ -0,0 +1,669 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..cc285306ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..4628460529 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 129 + 129 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/main.c new file mode 100644 index 0000000000..395ee15df5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/main.c @@ -0,0 +1,159 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nTemper; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_TEMP; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_LOW; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_InitStruct.Channel = ADC_CHANNEL_TEMP; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_TEMP; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_NONE; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_SITV(1); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<16;) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + if(ADC_CalculateValue(ADC_TEMP, ADCData, &nTemper)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("Temperature is %d %.2f.\r\n", ADCData, (float)nTemper/256.0); + } + } + else + { + ADC_SoftReset(&ADC_InitStruct); + } + WDT_Clear(); + } + + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Auto/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..f469669280 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/template.uvoptx @@ -0,0 +1,669 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 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..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..e339b6c7c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 141 + 141 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 706 + 706 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/main.c new file mode 100644 index 0000000000..58adc49c0c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/main.c @@ -0,0 +1,272 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + GPIO_InitType InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nTemper, nResult; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + InitStruct.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_11; + GPIOA_Init(GPIOA, &InitStruct); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_TEMP; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_LOW; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_TEMP; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_TEMP; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_NONE; + ADC_Init(&ADC_InitStruct); + + ADC_Cmd(ENABLE); + ADC_StartManual(); + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + if(ADC_CalculateValue(ADC_TEMP, ADCData, &nTemper)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("Temperature is %d, %.2f.\r\n", ADCData, (float)nTemper/256.0); + } + } + + while(1) + { + ADC_Cmd(DISABLE); + /* ADC Init */ + ADC_InitStruct.Mode = ADC_MODE_TEMP; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_LOW; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_InitStruct.Channel = ADC_CHANNEL_TEMP; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_TEMP; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_NONE; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_ITV(RTC_ITV_62MS); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<16; ) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + if(ADC_CalculateValue(ADC_TEMP, ADCData, &nTemper)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("Temperature is %d, %.2f.\r\n", ADCData, (float)nTemper/256.0); + } + } + else + { + ADC_SoftReset(&ADC_InitStruct); + } + + WDT_Clear(); + } + + ADC_Cmd(DISABLE); + /* ADC Init */ + ADC_InitStruct.Mode = ADC_MODE_DC; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_ITVSITV; + ADC_InitStruct.Channel = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC|ADC_CHANNEL_CH3|ADC_CHANNEL_CH6; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_NONE; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_BAT1|ADC_CHANNEL_BATRTC; + ADC_Init(&ADC_InitStruct); + + RTC_WAKE_ITV(RTC_ITV_125MS); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<10; ) + { + /*WARIT SITV time reach */ + while(!RTC_GetINTStatus(RTC_INTSTS_ITVSITV)); + RTC_ClearINTStatus(RTC_INTSTS_ITVSITV); + + if(!ADC_WaitForAuto(DELAY_MS(100))) + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BAT1); + if(ADC_CalculateValue(ADC_5V_ADCCHx_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BAT1 is %d, %.3fV\t", ADCData, (float)nResult/1000.0); + } + + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_BATRTC); + if(ADC_CalculateValue(ADC_5V_ADCCHx_RESDIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("BATRTC is %d, %.3fV\t", ADCData, (float)nResult/1000.0); + } + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_CH3); + if(ADC_CalculateValue(ADC_5V_ADCCHx_NODIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("CH3 is %d, %.3fV\t", ADCData, (float)nResult/1000.0); + } + + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_CH6); + if(ADC_CalculateValue(ADC_5V_ADCCHx_NODIV, ADCData, &nResult)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("CH6 is %d, %.3fV\r\n", ADCData, (float)nResult/1000.0); + } + } + else + { + ADC_SoftReset(&ADC_InitStruct); + } + WDT_Clear(); + } + WDT_Clear(); + + ADC_Cmd(DISABLE); + + test_success = 1; + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_DC/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..f469669280 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/template.uvoptx @@ -0,0 +1,669 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + file + + + 2 + 1 + line + + + 3 + 1 + rtc_data2,0x10 + + + 4 + 1 + rtc_data1 + + + 5 + 1 + rtc_data3 + + + 6 + 1 + rtc_data4 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..cc285306ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..622d01f6c0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 125 + 125 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/main.c new file mode 100644 index 0000000000..8977db71e6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/main.c @@ -0,0 +1,155 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ADC_InitType ADC_InitStruct; + uint32_t i, nCount; + int16_t ADCData; + int16_t nTemper; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_TEMP; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_LOW; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_32; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_TEMP; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_TEMP; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_NONE; + ADC_Init(&ADC_InitStruct); + + ADC_Cmd(ENABLE); + + /* Get ADC Value */ + for(i=0; i<32; ) + { + ADC_StartManual(); + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + i++; + ADCData = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + if(ADC_CalculateValue(ADC_TEMP, ADCData, &nTemper)) + { + printf("NVR checksum error.\r\n"); + } + else + { + printf("Temperature is %d %.2f.\r\n", ADCData, (float)nTemper/256.0); + } + } + } + + ADC_Cmd(DISABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ADC/ADC_Temperature_Manual/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/.project new file mode 100644 index 0000000000..f4a6b67a83 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/.project @@ -0,0 +1,203 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/common.c + 1 + PARENT-2-PROJECT_LOC/Src/common.c + + + User/download.c + 1 + PARENT-2-PROJECT_LOC/Src/download.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/upload.c + 1 + PARENT-2-PROJECT_LOC/Src/upload.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + User/ymodem.c + 1 + PARENT-2-PROJECT_LOC/Src/ymodem.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..9bc781b399 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20002000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000100, LENGTH = 0x2000 - 0x100 +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x4000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/target_flash.icf new file mode 100644 index 0000000000..3a7d5bb021 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x00003FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000100; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.ewp new file mode 100644 index 0000000000..51c4b38715 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.ewp @@ -0,0 +1,2019 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Src\common.c + + + $PROJ_DIR$\..\Src\download.c + + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\upload.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + $PROJ_DIR$\..\Src\ymodem.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/common.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/common.h new file mode 100644 index 0000000000..543236f0be --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/common.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file common.h + * @author Application Team + * @version V4.3.0 + * @date 2018-09-04 + ****************************************************************************** + * @attention + ****************************************************************************** + */ + +#ifndef __COMMON_H +#define __COMMON_H + +#include "stdio.h" +#include "string.h" +#include "target.h" +#include "ymodem.h" + +typedef void (*pFunction)(void); + +#define FLASH_SERASE_KEY 0xAA5555AA +#define CMD_STRING_SIZE 128 +#define ApplicationAddress 0x00004000 +#define ISR_HAND_OFFSET 0x00000004 +#define BootIsrAddress 0x00000004 +#define PAGE_SIZE (0x400) /* 1024 byte */ +#define FLASH_SIZE (0x40000UL) + +//The size of file +#define FLASH_IMAGE_SIZE (uint32_t) (FLASH_SIZE - (ApplicationAddress - 0x0000000)) + +#define IS_AF(c) ((c >= 'A') && (c <= 'F')) +#define IS_af(c) ((c >= 'a') && (c <= 'f')) +#define IS_09(c) ((c >= '0') && (c <= '9')) +#define ISVALIDHEX(c) IS_AF(c) || IS_af(c) || IS_09(c) +#define ISVALIDDEC(c) IS_09(c) +#define CONVERTDEC(c) (c - '0') + +#define CONVERTHEX_alpha(c) (IS_AF(c) ? (c - 'A'+10) : (c - 'a'+10)) +#define CONVERTHEX(c) (IS_09(c) ? (c - '0') : CONVERTHEX_alpha(c)) + +#define SerialPutString(x) Serial_PutString((uint8_t*)(x)) + + +void Int2Str(uint8_t* str,int32_t intnum); +uint32_t Str2Int(uint8_t *inputstr,int32_t *intnum); +uint32_t GetIntegerInput(int32_t * num); +uint32_t SerialKeyPressed(uint8_t *key); +uint8_t GetKey(void); +void SerialPutChar(uint8_t c); +void Serial_PutString(uint8_t *s); +void GetInputString(uint8_t * buffP); +uint32_t FLASH_PagesMask(volatile uint32_t Size); +void FLASH_DisableWriteProtectionPages(void); +void Main_Menu(void); +void SerialDownload(void); +void SerialUpload(void); + +void FLASH_SectorEraseUnderUnlock(uint32_t SectorAddr); +void FLASH_ProgramOneWord(uint32_t Addr, uint32_t Word); +void FLASH_Unlock(void); +void FLASH_Lock(void); + +#endif /* __COMMON_H */ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/main.h new file mode 100644 index 0000000000..6d21721fdf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/main.h @@ -0,0 +1,32 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include +#include "common.h" + +void Delay_us(volatile uint32_t n); +void Delay_ms(volatile uint32_t n); + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/target_isr.h new file mode 100644 index 0000000000..0642b4d733 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/target_isr.h @@ -0,0 +1,97 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +#define RESET_HAND_OFFSET 0x4 +#define NMI_HAND_OFFSET 0x8 +#define HardFault_HAND_OFFSET 0xC +#define SVC_HAND_OFFSET 0x2C +#define PendSV_HAND_OFFSET 0x38 +#define SysTick_HAND_OFFSET 0x3C +#define PMU_HAND_OFFSET 0x40 +#define RTC_HAND_OFFSET 0x44 +#define U32K0_HAND_OFFSET 0x48 +#define U32K1_HAND_OFFSET 0x4C +#define I2C_HAND_OFFSET 0x50 +#define SPI1_HAND_OFFSET 0x54 +#define UART0_HAND_OFFSET 0x58 +#define UART1_HAND_OFFSET 0x5C +#define UART2_HAND_OFFSET 0x60 +#define UART3_HAND_OFFSET 0x64 +#define UART4_HAND_OFFSET 0x68 +#define UART5_HAND_OFFSET 0x6C +#define ESAM0_HAND_OFFSET 0x70 +#define ESAM1_HAND_OFFSET 0x74 +#define TMR0_HAND_OFFSET 0x78 +#define TMR1_HAND_OFFSET 0x7C +#define TMR2_HAND_OFFSET 0x80 +#define TMR3_HAND_OFFSET 0x84 +#define PWM0_HAND_OFFSET 0x88 +#define PWM1_HAND_OFFSET 0x8C +#define PWM2_HAND_OFFSET 0x90 +#define PWM3_HAND_OFFSET 0x94 +#define DMA_HAND_OFFSET 0x98 +#define FLASH_HAND_OFFSET 0x9C +#define ANA_HAND_OFFSET 0xA0 +#define SPI2_HAND_OFFSET 0xAC +#define SPI3_HAND_OFFSET 0xB0 + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/ymodem.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/ymodem.h new file mode 100644 index 0000000000..3627be2ec2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Inc/ymodem.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file ymodem.h + * @author Application Team + * @version V4.3.0 + * @date 2018-09-04 + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ +#ifndef _YMODEM_H_ +#define _YMODEM_H_ + +#include "stdint.h" + +/* Definitions ---------------------------------------------------------------*/ +#define PACKET_SEQNO_INDEX (1) +#define PACKET_SEQNO_COMP_INDEX (2) + +#define PACKET_HEADER (3) +#define PACKET_TRAILER (2) +#define PACKET_OVERHEAD (PACKET_HEADER + PACKET_TRAILER) +#define PACKET_SIZE (128) +#define PACKET_1K_SIZE (1024) + +#define FILE_NAME_LENGTH (256) +#define FILE_SIZE_LENGTH (16) + +#define SOH (0x01) //Start @ 128 byte +#define STX (0x02) //Start @ 1024 byte +#define EOT (0x04) //End +#define ACK (0x06) //Response +#define NAK (0x15) //No response +#define CA (0x18) //Aborted +#define CRC16 (0x43) //'C' == 0x43, 16-bit CRC + +#define ABORT1 (0x41) //'A' == 0x41, User aborted +#define ABORT2 (0x61) //'a' == 0x61, User aborted + +#define NAK_TIMEOUT (0x100000) +#define MAX_ERRORS (5) + +/*- Exported Function --------------------------------------------------------*/ +int32_t Ymodem_Receive (uint8_t *buf); +uint8_t Ymodem_Transmit (uint8_t *buf, const uint8_t* sendFileName, uint32_t sizeFile); + +#endif /* _YMODEM_H_ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..3c76305db6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..bd2c0e1f6b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/template.uvoptx @@ -0,0 +1,691 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO31 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + ..\Src\ymodem.c + ymodem.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + ..\Src\upload.c + upload.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + ..\Src\download.c + download.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + ..\Src\common.c + common.c + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 9 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 33 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 34 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 35 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..0243c66e2a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARM/template.uvprojx @@ -0,0 +1,678 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000100 + 0x1f00 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + ymodem.c + 1 + ..\Src\ymodem.c + + + upload.c + 1 + ..\Src\upload.c + + + download.c + 1 + ..\Src\download.c + + + common.c + 1 + ..\Src\common.c + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..3c76305db6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..e38e0b4d28 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/template.uvopt @@ -0,0 +1,769 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO31 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 4 + 0 + 19 + 45 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\common.c + common.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\download.c + download.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\upload.c + upload.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\ymodem.c + ymodem.c + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 9 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 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..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..63ad12d94b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/MDK-ARMv4/template.uvproj @@ -0,0 +1,604 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000100 + 0x1f00 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + common.c + 1 + ..\Src\common.c + + + download.c + 1 + ..\Src\download.c + + + upload.c + 1 + ..\Src\upload.c + + + ymodem.c + 1 + ..\Src\ymodem.c + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/common.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/common.c new file mode 100644 index 0000000000..2bc9121144 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/common.c @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file common.c + * @author Application Team + * @version V1.0.0 + * @date 2019-10-28 + ****************************************************************************** + * @attention + ****************************************************************************** + */ +#include "common.h" + +pFunction Jump_To_Application; +uint32_t JumpAddress; + +extern uint32_t FlashDestination; +extern volatile uint32_t g_bAppRun; + +/** + * @brief Integer switch to string. + * @inparam intnum. + * @outparam str + * @retval None. +**/ +void Int2Str(uint8_t* str, int32_t intnum) +{ + uint32_t i, j ; + uint32_t Div = 1000000000; + uint32_t Status = 0; + + for (i = 0; i < 10; i++) + { + j = 0; + str[j++] = (intnum / Div) + 48; + + intnum = intnum % Div; + Div /= 10; + if ((str[j-1] == '0') & (Status == 0)) + { + j = 0; + } + else + { + Status++; + } + } +} + +/** + * @brief String switch to integer. + * @inparam inputstr: + * @outparam intnum£º + * @retval 0: Error. + 1£ºCorrect. +**/ +uint32_t Str2Int(uint8_t *inputstr, int32_t *intnum) +{ + uint32_t i = 0, res = 0; + uint32_t val = 0; + + if (inputstr[0] == '0' && (inputstr[1] == 'x' || inputstr[1] == 'X')) + { + if (inputstr[2] == '\0') + { + return 0; + } + for (i = 2; i < 11; i++) + { + if (inputstr[i] == '\0') + { + *intnum = val; + res = 1; + break; + } + if (ISVALIDHEX(inputstr[i])) + { + val = (val << 4) + CONVERTHEX(inputstr[i]); + } + else + { + res = 0; + break; + } + } + + if (i >= 11) + { + res = 0; + } + } + else + { + for (i = 0; i < 11; i++) + { + if (inputstr[i] == '\0') + { + *intnum = val; + res = 1; + break; + } + else if ((inputstr[i] == 'k' || inputstr[i] == 'K') && (i > 0)) + { + val = val << 10; + *intnum = val; + res = 1; + break; + } + else if ((inputstr[i] == 'm' || inputstr[i] == 'M') && (i > 0)) + { + val = val << 20; + *intnum = val; + res = 1; + break; + } + else if (ISVALIDDEC(inputstr[i])) + { + val = val * 10 + CONVERTDEC(inputstr[i]); + } + else + { + res = 0; + break; + } + } + if (i >= 11) + { + res = 0; + } + } + + return res; +} + +/** + * @brief Get an integer from the HyperTerminal. + * @inparam num + * @outparam intnum: + * @retval 0: Abort by user. + 1£ºCorrect. +**/ +uint32_t GetIntegerInput(int32_t * num) +{ + uint8_t inputstr[16]; + + while (1) + { + GetInputString(inputstr); + if (inputstr[0] == '\0') continue; + if ((inputstr[0] == 'a' || inputstr[0] == 'A') && inputstr[1] == '\0') + { + SerialPutString("User Cancelled \r\n"); + return 0; + } + + if (Str2Int(inputstr, num) == 0) + { + SerialPutString("Error, Input again: \r\n"); + } + else + { + return 1; + } + } +} + + +/** + * @brief Test whether the terminal has buttons pressed. + * @inparam key. + * @outparam None. + * @retval 0: Error. + 1£ºCorrect. +**/ +uint32_t SerialKeyPressed(uint8_t *key) +{ + if (UART5->STATE&UART_STATE_RXFULL) + { + *key = (uint8_t)UART5->DATA; + return 1; + } + else + { + return 0; + } +} + + +/** + * @brief GetKey. + * @inparam None. + * @outparam None. + * @retval The key of user pressed. +**/ +uint8_t GetKey(void) +{ + uint8_t key = 0; + + // Wait for key be pressed + while (1) + { + if (SerialKeyPressed((uint8_t*)&key)) + { + break; + } + } + return key; +} + + +/** + * @brief Send a character by serial port. + * @inparam C: The character you should send. + * @outparam None. + * @retval None. +**/ +void SerialPutChar(uint8_t c) +{ + UART5->DATA = c; + /* wait for transmit done */ + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE |= UART_STATE_TXDONE; +} + +/** + * @brief Send strings by serial port. + * @inparam s: The string need to send. + * @outparam None. + * @retval None. +**/ +void Serial_PutString(uint8_t *s) +{ + while (*s != '\0') + { + SerialPutChar(*s); + s++; + } +} + +/** + * @brief Get a string from serial port. + * @inparam *s. + * @outparam None. + * @retval None. +**/ +void GetInputString(uint8_t * buffP) +{ + uint32_t bytes_read = 0; + uint8_t c = 0; + do + { + c = GetKey(); + if (c == '\r') + break; + if (c == '\b')// Backspace °´¼ü + { + if (bytes_read > 0) + { + SerialPutString("\b \b"); + bytes_read --; + } + continue; + } + if (bytes_read >= CMD_STRING_SIZE ) + { + SerialPutString("Command string size overflow\r\n"); + bytes_read = 0; + continue; + } + if (c >= 0x20 && c <= 0x7E) + { + buffP[bytes_read++] = c; + SerialPutChar(c); + } + } + while (1); + SerialPutString(("\n\r")); + buffP[bytes_read] = '\0'; +} + +/** + * @brief Calculate the number of Falsh page. + * @inparam Size: Length of file. + * @outparam None. + * @retval The number of Falsh page. +**/ +uint32_t FLASH_PagesMask(volatile uint32_t Size) +{ + uint32_t pagenumber = 0x0; + uint32_t size = Size; + + if ((size % PAGE_SIZE) != 0) + { + pagenumber = (size / PAGE_SIZE) + 1; + } + else + { + pagenumber = size / PAGE_SIZE; + } + return pagenumber; +} + + +/** + * @brief Main_Menu. + * @inparam None. + * @outparam None. + * @retval None. +**/ + void Main_Menu(void) +{ + uint8_t key = 0; + + while (1) + { + SerialPutString("================== Main Menu ==========================\r\n\n"); + SerialPutString(" Download Image To the Target Internal Flash ------- 1\r\n\n"); + SerialPutString(" Upload Image From the Target Internal Flash ------- 2\r\n\n"); + SerialPutString(" Execute The New Program --------------------------- 3\r\n\n"); + + if ((FLASH->PASS) == 0) + { + SerialPutString(" Disable the write protection --------------------- 4\r\n\n"); + } + + SerialPutString("========================================================\r\n\n"); + + key = GetKey(); + + if (key == 0x31) + { + /* Download user application in the Flash */ + SerialDownload(); + } + else if (key == 0x32) + { + /* Upload user application from the Flash */ + SerialUpload(); + } + else if (key == 0x33) + { + g_bAppRun = 1; + SerialPutString("Execute user Program\r\n\n"); + JumpAddress = *(__IO uint32_t*) (ApplicationAddress + 4); + + Jump_To_Application = (pFunction) JumpAddress; + /*Initial stack pointer of user code*/ + __set_MSP(*(__IO uint32_t*) ApplicationAddress); + Jump_To_Application(); + } + + else if ((key == 0x34) && ((FLASH->PASS) == 0)) + { + /*Unlock FLASH*/ + FLASH_Unlock(); + } + else + { + if ((FLASH->PASS) != 0) + { + SerialPutString("Invalid number! ==> The number should be either 1, 2 or 3\r\n\n\n"); + } + else + { + SerialPutString("Invalid number! ==> The number should be either 1, 2, 3 or 4\r\n\n\n"); + } + } + } +} +/** + * @brief Erase FLASH sector. + * @param SectorAddr: sector address. + * @retval None + */ +void FLASH_SectorEraseUnderUnlock(uint32_t SectorAddr) +{ + FLASH->PGADDR = SectorAddr; + FLASH->SERASE = FLASH_SERASE_KEY; + while (FLASH->SERASE != 0); +} + +/** + * @brief FLASH one word progarm . + * @param Addr: program address + Word: word to write + * @retval None + */ +void FLASH_ProgramOneWord(uint32_t Addr, uint32_t Word) +{ + FLASH->PGADDR = Addr; + FLASH->PGDATA = Word; +} + +/** + * @brief Unlock FLASH. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + FLASH->PASS = 0x55AAAA55; +} + +/** + * @brief Lock FLASH. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + FLASH->PASS = 0; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/download.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/download.c new file mode 100644 index 0000000000..9d0657755a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/download.c @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file download.c + * @author Application Team + * @version V1.0.0 + * @date 2019-10-28 + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +#include "common.h" + +extern uint8_t file_name[FILE_NAME_LENGTH]; +uint8_t tab_1024[1024] = +{ + 0 +}; + +/** + * @brief Receive file via Serial. + * @inparam None. + * @outparam None. + * @retval None. +**/ +void SerialDownload(void) +{ + int32_t Size = 0; + + SerialPutString("Waiting for the file to be sent ... (press 'a' to abort)\n\r"); + Size = Ymodem_Receive(&tab_1024[0]); + if (Size > 0) + { + SerialPutString("\r\n IAP Completed Successfully!\r\n"); +// SerialPutString("Name: "); +// SerialPutString(file_name); +// Int2Str(Number, Size); +// SerialPutString("\n\r Size: "); +// SerialPutString(Number); +// SerialPutString(" Bytes\r\n"); +// SerialPutString("--------------------------------\r\n"); + } + else if (Size == -1) + { + SerialPutString("\n\n\rThe image size is too large!\n\r"); + } + else if (Size == -2) + { + SerialPutString("\n\n\rVerification failed!\n\r"); + } + else if (Size == -3) + { + SerialPutString("\r\n\nAborted by user.\n\r"); + } + else + { + SerialPutString("\n\rFailed to receive the file!\n\r"); + } +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/main.c new file mode 100644 index 0000000000..46a03ec992 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/main.c @@ -0,0 +1,161 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +volatile unsigned char test_success; + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +#define FLASH_PASS_KEY +extern pFunction Jump_To_Application; +extern uint32_t JumpAddress; +volatile uint32_t g_bAppRun; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +void Delay_us(volatile uint32_t n) +{ + while (n--) + { + __NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP(); + __NOP();__NOP(); + } +} + +void Delay_ms(volatile uint32_t n) +{ + while (n--) + { + Delay_us(971); + } +} + +/** + * @brief Jump to APP. + * @param None. + * @retval None. +**/ +static void JumpToApp(void) +{ + /*Jedge the stack address£º0x200000000~0x20007FFF*/ + if (((*(__IO uint32_t*)ApplicationAddress) & 0x2FFF80000 ) == 0x20000000) + { + SerialPutString("Execute user Program!\r\n\n"); + + /*Jump to the user code*/ + JumpAddress = *(__IO uint32_t*) (ApplicationAddress + 4); + Jump_To_Application = (pFunction) JumpAddress; + + /*Set stack top value of user code as current stack top value */ + __set_MSP(*(__IO uint32_t*) ApplicationAddress); + + Jump_To_Application(); + } + else + { + SerialPutString("no user Program\r\n\n"); + Main_Menu(); + } +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + uint8_t key; + + test_success = 0; + + Clock_Init(); + + test_success = 1; + + /*unlock Flash*/ + FLASH_Unlock(); + + /*Configure UART5*/ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN|UART_CTRL_RXEN; + + Delay_ms(500); + /*If UART receive '5', excute IAP program*/ + SerialKeyPressed(&key); + if (key == 0x35) + { + g_bAppRun = 0; + Main_Menu(); + } + /*Else, there will excute user code*/ + else + { + g_bAppRun = 1; + /*Jump to user code*/ + JumpToApp(); + } + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/target_isr.c new file mode 100644 index 0000000000..60614301d9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/target_isr.c @@ -0,0 +1,540 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern volatile uint32_t g_bAppRun; +typedef void (*pFun)(void); + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + NMI_HAND_OFFSET)); + (*p)(); + } + else + { + //Bootloader + } +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + pFun p; + + SerialPutString("\nEnter IAP HardFault!\n\r"); + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + HardFault_HAND_OFFSET)); + (*p)(); + } + else + { + while (1) + { + } + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + SVC_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + PendSV_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + SysTick_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + PMU_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + RTC_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + U32K0_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + U32K1_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + I2C_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + SPI1_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + UART0_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + UART1_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + UART2_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + UART3_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + UART4_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + UART5_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + ESAM0_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + ESAM1_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + TMR0_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + TMR1_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + TMR2_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + TMR3_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + PWM0_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + PWM1_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + PWM2_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + PWM3_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + DMA_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + FLASH_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + ANA_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + SPI2_HAND_OFFSET)); + (*p)(); + } +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ + pFun p; + + if (g_bAppRun) + { + p = (pFun)(*(__IO uint32_t*)(ApplicationAddress + SPI3_HAND_OFFSET)); + (*p)(); + } +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/upload.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/upload.c new file mode 100644 index 0000000000..78d6479744 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/upload.c @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file upload.c + * @author Application Team + * @version V1.0.0 + * @date 2019-10-28 + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +#include "common.h" + +/** + * @brief Upload file via Serial. + * @param None. + * @retval None. +**/ +void SerialUpload(void) +{ + uint32_t status = 0; + SerialPutString("\n\n\rSelect Receive File ... (press any key to abort)\n\r"); + +//GetKey(); + if ( GetKey()== CRC16) + { + //Ymodem_Transmit's return value is 0, function successed + status = Ymodem_Transmit((uint8_t*)ApplicationAddress, (const uint8_t*)"UploadedFlashImage.bin", FLASH_IMAGE_SIZE); + + if (status != 0) + { + SerialPutString("\n\rError occured while Transmitting File\n\r"); + } + else + { + SerialPutString("\n\rFile Trasmitted Successfully \n\r"); + } + } + else + { + SerialPutString("\r\n\nAborted by user.\n\r"); + } +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/ymodem.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/ymodem.c new file mode 100644 index 0000000000..01423c1fb1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x0_IAP/Src/ymodem.c @@ -0,0 +1,629 @@ +/** + ****************************************************************************** + * @file ymodem.c + * @author Application Team + * @version V1.0.0 + * @date 2019-10-28 + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +#include "target.h" +#include "common.h" +#include "ymodem.h" + +uint8_t file_name[FILE_NAME_LENGTH]; + +// User App Flash offset +uint32_t FlashDestination = ApplicationAddress; +uint16_t PageSize = PAGE_SIZE; +uint32_t EraseCounter = 0x0; +uint32_t NbrOfPage = 0; + +uint32_t RamSource; +extern uint8_t tab_1024[1024]; + +/** + * @brief Receive one byte. + * @param c: the pointer to receive data. + timeout: + * @retal 0£ºFunction succesed. + -1£ºTime-out occured. +**/ +static int32_t Receive_Byte (uint8_t *c, uint32_t timeout) +{ + while (timeout-- > 0) + { + if (SerialKeyPressed(c) == 1) + { + return 0; + } + } + return -1; +} + + +/** + * @brief Receive package. + * @param data £ºthe pointer of datas + length£ºthe length of datas + timeout £º + * @retal 0: Function successed + -1: Time-out occured or datas error + 1: Be canced +**/ +static int32_t Receive_Packet (uint8_t *data, int32_t *length, uint32_t timeout) +{ + uint16_t i, packet_size; + uint8_t c; + *length = 0; + if (Receive_Byte(&c, timeout) != 0) + { + return -1; + } + switch (c) + { + case SOH: + packet_size = PACKET_SIZE; + break; + case STX: + packet_size = PACKET_1K_SIZE; + break; + case EOT: + return 0; + case CA: + if ((Receive_Byte(&c, timeout) == 0) && (c == CA)) + { + *length = -1; + return 0; + } + else + { + return -1; + } + case ABORT1: + case ABORT2: + return 1; + default: + return -1; + } + *data = c; + for (i = 1; i < (packet_size + PACKET_OVERHEAD); i ++) + { + if (Receive_Byte(data + i, timeout) != 0) //·¢ËͶ˳¬Ê± + { + return -1; + } + } + if (data[PACKET_SEQNO_INDEX] != ((data[PACKET_SEQNO_COMP_INDEX] ^ 0xff) & 0xff)) //°ü±àÂëºÅÓëÆä·´Âë²»Ò»Ö + { + return -1; + } + *length = packet_size; + return 0; +} + +/** + * @brief Receive file via ymodem + * @param buf: pointer of file + * @retal The size of file +**/ +int32_t Ymodem_Receive (uint8_t *buf) +{ + uint8_t packet_data[PACKET_1K_SIZE + PACKET_OVERHEAD]; + uint8_t file_size[FILE_SIZE_LENGTH]; + uint8_t *file_ptr, *buf_ptr; + int32_t i, j; + int32_t packet_length, session_done, file_done, packets_received, errors, session_begin, size = 0; + + FlashDestination = ApplicationAddress; + + for (session_done = 0, errors = 0, session_begin = 0; ;) + { + for (packets_received = 0, file_done = 0, buf_ptr = buf; ;) + { + switch (Receive_Packet(packet_data, &packet_length, NAK_TIMEOUT)) + { + case 0: + errors = 0; + switch (packet_length) + { + // Be cancled + case - 1: + SerialPutChar(ACK); + return 0; + //Transfer aborted + case 0: + SerialPutChar(ACK); + file_done = 1; + break; + // Package transfer + default: + if ((packet_data[PACKET_SEQNO_INDEX] & 0xff) != (packets_received & 0xff)) + { + SerialPutChar(NAK); + } + else + { + if (packets_received == 0) + { + // Package of file-name + if (packet_data[PACKET_HEADER] != 0) + { + for (i = 0, file_ptr = packet_data + PACKET_HEADER; (*file_ptr != 0) && (i < FILE_NAME_LENGTH);) + { + file_name[i++] = *file_ptr++; + } + file_name[i++] = '\0'; + for (i = 0, file_ptr ++; (*file_ptr != ' ') && (i < FILE_SIZE_LENGTH);) + { + file_size[i++] = *file_ptr++; + } + file_size[i++] = '\0'; + + // The size of package + Str2Int(file_size, &size); + + // Transfer end + if (size > (FLASH_SIZE - 1)) + { + SerialPutChar(CA); + SerialPutChar(CA); + return -1; + } + + NbrOfPage = FLASH_PagesMask(size); + + // Flash erase + for (EraseCounter = 0; EraseCounter < NbrOfPage; EraseCounter++) + { + FLASH_SectorEraseUnderUnlock(FlashDestination + (PageSize * EraseCounter)); + } + SerialPutChar(ACK); + SerialPutChar(CRC16); + } + // Has no file + else + { + SerialPutChar(ACK); + file_done = 1; + session_done = 1; + break; + } + } + // Package + else + { + memcpy(buf_ptr, packet_data + PACKET_HEADER, packet_length); + RamSource = (uint32_t)buf; + for (j = 0; (j < packet_length) && (FlashDestination < ApplicationAddress + size); j += 4) + { + // Flash program + FLASH_ProgramOneWord(FlashDestination, *(uint32_t*)RamSource); + + if (*(uint32_t*)FlashDestination != *(uint32_t*)RamSource) + { + // end + SerialPutChar(CA); + SerialPutChar(CA); + return -2; + } + FlashDestination += 4; + RamSource += 4; + } + SerialPutChar(ACK); + } + packets_received ++; + session_begin = 1; + } + } + break; + case 1: + SerialPutChar(CA); + SerialPutChar(CA); + return -3; + default: + if (session_begin > 0) + { + errors ++; + } + if (errors > MAX_ERRORS) + { + SerialPutChar(CA); + SerialPutChar(CA); + return 0; + } + SerialPutChar(CRC16); + break; + } + if (file_done != 0) + { + break; + } + } + if (session_done != 0) + { + break; + } + } + return (int32_t)size; +} + +/** + * @brief Check response + * @param c + * @retal 0 +**/ +int32_t Ymodem_CheckResponse(uint8_t c) +{ + return 0; +} + +/** + * @brief Initial packet + * @param data + fileName + length + * @retal None +**/ +void Ymodem_PrepareIntialPacket(uint8_t *data, const uint8_t* fileName, uint32_t *length) +{ + uint16_t i, j; + uint8_t file_ptr[10]; + + data[0] = SOH; + data[1] = 0x00; + data[2] = 0xff; + for (i = 0; ((fileName[i] != '\0') && (i < FILE_NAME_LENGTH)); i++) + { + data[i + PACKET_HEADER] = fileName[i]; + } + + data[i + PACKET_HEADER] = 0x00; + + Int2Str (file_ptr, *length); + for (j =0, i = i + PACKET_HEADER + 1; file_ptr[j] != '\0' ; ) + { + data[i++] = file_ptr[j++]; + } + + for (j = i; j < PACKET_SIZE + PACKET_HEADER; j++) + { + data[j] = 0; + } +} + +/** + * @brief Prepare packet + * @param SourceBuf£º + data£º + pktNo £º + sizeBlk £º + * @retal None +**/ +void Ymodem_PreparePacket(uint8_t *SourceBuf, uint8_t *data, uint8_t pktNo, uint32_t sizeBlk) +{ + uint16_t i, size, packetSize; + uint8_t* file_ptr; + + packetSize = sizeBlk >= PACKET_1K_SIZE ? PACKET_1K_SIZE : PACKET_SIZE; + size = sizeBlk < packetSize ? sizeBlk :packetSize;//sizeBlk<=packetsize size = sizeBlk, ize=packetsize + + if (packetSize == PACKET_1K_SIZE) + { + data[0] = STX; + } + else + { + data[0] = SOH; + } + data[1] = pktNo; + data[2] = (~pktNo); + file_ptr = SourceBuf; + + for (i = PACKET_HEADER; i < size + PACKET_HEADER; i++) + { + data[i] = *file_ptr++; + } + if ( size <= packetSize) + { + for (i = size + PACKET_HEADER; i < packetSize + PACKET_HEADER; i++) + { + data[i] = 0x1A; // end + } + } +} + +/** + * @brief Update CRC + * @param crcIn + byte + * @retal CRC value +**/ +uint16_t UpdateCRC16(uint16_t crcIn, uint8_t byte) +{ + uint32_t crc = crcIn; + uint32_t in = byte|0x100; + do + { + crc <<= 1; + in <<= 1; + if (in&0x100) + ++crc; + if (crc&0x10000) + crc ^= 0x1021; + } + while (!(in&0x10000)); + return crc&0xffffu; +} + +/** + * @brief Cal CRC value + * @param data + size + * @retal CRC value +**/ +uint16_t Cal_CRC16(const uint8_t* data, uint32_t size) +{ + uint32_t crc = 0; + const uint8_t* dataEnd = data+size; + while (data> 8); + SerialPutChar(tempCRC & 0xFF); + } + else + { + tempCheckSum = CalChecksum (&packet_data[3], PACKET_SIZE); + SerialPutChar(tempCheckSum); + } + + if (Receive_Byte(&receivedC[0], 1000000) == 0) + { + receivedC[1]=receivedC[0]; + if(Receive_Byte(&receivedC[0], 1000000) == 0) + { + if ((receivedC[1] == ACK)&&(receivedC[0]==CRC16)) + { + // packet be transferred + ackReceived = 1; + } + } + } + else + { + errors++; + } + } while (!ackReceived && (errors < 0x0A)); + + if (errors >= 0x0A) + { + return errors; + } + + + buf_ptr = buf; + size = sizeFile; + blkNumber = 0x01; + + // 2. Send 1024 byte datas + while (size) + { + // Prepare next packet + Ymodem_PreparePacket(buf_ptr, &packet_data[0], blkNumber, size); + ackReceived = 0; + receivedC[0]= 0; + errors = 0; + + do + { + // Send next packet + if (size >= PACKET_1K_SIZE) + { + pktSize = PACKET_1K_SIZE; + } + else + { + pktSize = PACKET_SIZE; + } + Ymodem_SendPacket(packet_data, pktSize + PACKET_HEADER); + // Send CRC checksum + if (CRC16_F) + { + tempCRC = Cal_CRC16(&packet_data[3], pktSize); + SerialPutChar(tempCRC >> 8); + SerialPutChar(tempCRC & 0xFF); + } + else + { + tempCheckSum = CalChecksum (&packet_data[3], pktSize); + //SerialPutChar(tempCheckSum); + SerialPutChar(tempCheckSum); + } + + // Wait for response + if ((Receive_Byte(&receivedC[0], 100000) == 0) && (receivedC[0] == ACK)) + { + ackReceived = 1; + if (size > pktSize) + { + buf_ptr += pktSize; + size -= pktSize; + if (blkNumber == (FLASH_IMAGE_SIZE/1024)) + { + return 0xFF; // Error + } + else + { + blkNumber++; + } + } + else + { + buf_ptr += pktSize; + size = 0; + } + } + else + { + errors++; + } + } while (!ackReceived && (errors < 0x0A)); + + // Return error + if (errors >= 0x0A) + { + return errors; + } + } + + // 3. Send EOT + ackReceived = 0; + receivedC[0] = 0x00; + errors = 0; + do + { + SerialPutChar(EOT); + // Send (EOT); + // Wait for response + if ((Receive_Byte(&receivedC[0], 10000) == 0) && receivedC[0] == ACK) + { + ackReceived = 1; + } + else + { + errors++; + } + } while (!ackReceived && (errors < 0x0A)); + + if (errors >= 0x0A) + { + return errors; + } + + // Prepare last packet, SOH 00 FF NUL[128] CRC CRC + ackReceived = 0; + receivedC[0] = 0x00; + errors = 0; + + packet_data[0] = SOH; + packet_data[1] = 0x00; + packet_data [2] = 0xFF; + + for (i = PACKET_HEADER; i < (PACKET_SIZE + PACKET_HEADER); i++) + { + packet_data[i] = 0x00; + } + + do + { + // Send datas' packet + Ymodem_SendPacket(packet_data, PACKET_SIZE + PACKET_HEADER); + // Send CRC checksum + tempCRC = Cal_CRC16(&packet_data[3], PACKET_SIZE); + SerialPutChar(tempCRC >> 8); + SerialPutChar(tempCRC & 0xFF); + + // Wait for response + if (Receive_Byte(&receivedC[0], 10000) == 0) + { + if (receivedC[0] == ACK) + { + ackReceived = 1; + } + } + else + { + errors++; + } + } while (!ackReceived && (errors < 0x0A)); + + // Return error + if (errors >= 0x0A) + { + return errors; + } + + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..ac38593e72 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 0 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..e5d9231dc4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x8000 - 0x2000 +FLASH (rx) : ORIGIN = 0x00004000, LENGTH = 0x80000 - 0x4000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/startup_target.s new file mode 100644 index 0000000000..56a1163207 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 0 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/target_flash.icf new file mode 100644 index 0000000000..4e734b6088 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00004000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00004000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/main.h new file mode 100644 index 0000000000..a87637b942 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/main.h @@ -0,0 +1,30 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +uint32_t SerialKeyPressed(uint8_t *key); + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..cda8ff1a5b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 0 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..e3caff5b0f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/template.uvoptx @@ -0,0 +1,647 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + + 1 + 0 + 0 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 1 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..9b342b7298 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x4000 + 0x7c000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20002000 + 0xe000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..cda8ff1a5b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 0 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..6d334edab1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 85 + 85 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 22 + 1 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..347624616c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x4000 + 0x7c000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20002000 + 0xe000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/main.c new file mode 100644 index 0000000000..b5639dc115 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/main.c @@ -0,0 +1,133 @@ +/** + * @file main.c + * @author Application Team + * @version V4.3.0 + * @date 2018-09-04 + * @brief Main program body. +******************************************************************************/ + +volatile unsigned char test_success; + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +#define FLASH_IAP_ADDR 0x00000000//IAP start address + +//Jump to IAP peogram +typedef void (*IapFun)(void); +IapFun JumpToIap; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Error_Handle. + * @param None + * @retval None + */ +void Error_Handle(void) +{ + while (1); +} + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + uint8_t key; + uint32_t val; + + test_success = 0; + + Clock_Init(); + + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN|UART_CTRL_RXEN; + + val = __get_MSP(); + printf("msp 0x%x\r\n", (unsigned int)val); + printf("Enter App test.\r\n"); + + NVIC_SetPendingIRQ(UART5_IRQn); + NVIC_EnableIRQ(UART5_IRQn); + + test_success = 0; + + while (1) + { + SerialKeyPressed(&key); + /*If UART receive '6', jump to IAP program*/ + if(key == 0x36) + { + JumpToIap=(IapFun)*(volatile uint32_t*)(FLASH_IAP_ADDR+4); + __set_MSP(*(__IO uint32_t*) FLASH_IAP_ADDR); + /*Jump to IAP program*/ + JumpToIap(); + } + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +uint32_t SerialKeyPressed(uint8_t *key) +{ + if (UART5->STATE&UART_STATE_RXFULL) + { + *key = (uint8_t)UART5->DATA; + return 1; + } + else + { + return 0; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/target_isr.c new file mode 100644 index 0000000000..4336e6a6bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern volatile unsigned char test_success; + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ + test_success = 1; + + NVIC_ClearPendingIRQ(UART5_IRQn); + printf("Enter UART5 IRQ.\r\n"); +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Bootloader/Bootloader_0x4000_APP/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + 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b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..70a6e93c1d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/template.uvoptx @@ -0,0 +1,627 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35905 + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..a9b47a6048 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 100 + 100 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/main.c new file mode 100644 index 0000000000..ce818449d5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/main.c @@ -0,0 +1,124 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + CMP_TypeDef InitStruct; + CMP_CountTypeDef CountInitStruct; + CMP_INTTypeDef INTInitStruct; + CMP_OutputTypeDef OutputInitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* Forbidden Comparator2 N input pin, IOA5 */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + CMP_DeInit(CMP_2); + CMP_StructInit(&InitStruct); + InitStruct.DebSel = CMP_DEB_RTCCLK_2; /* 2 32KHz de-bounce */ + InitStruct.SignalSourceSel = CMP_SIGNALSRC_NPIN_TO_BGPREF; /* Compare N to BGP refence(1.2V) */ + CMP_Init(CMP_2, &InitStruct); + + CMP_CountStructInit(&CountInitStruct); + CountInitStruct.ModeSel = CMP_MODE_RISING; /* Rising edge */ + CountInitStruct.CheckPeriod = CMP_PERIOD_7_8125MS; /* Checked every 7.8125ms */ + CountInitStruct.CheckNum = CMP_CHKNUM_4; /* Checked data 4 times */ + CMP_CountInit(CMP_2, &CountInitStruct); + + /* Comparator interrupt enable control. */ + CMP_INTStructInit(&INTInitStruct); + INTInitStruct.INTNumSel = CMP_INTNUM_1; + INTInitStruct.SubSel = CMP_COUNT_SUB; + INTInitStruct.THRNum = 10; + CMP_INTInit(CMP_2, &INTInitStruct); + + CMP_INTConfig(CMP_2, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 0); + + CMP_OutputStructInit(&OutputInitStruct); + OutputInitStruct.DebSel = CMP_OUTPUT_DEB; + OutputInitStruct.OutputSel = ENABLE; /* Enable Comparator2(output on IOA6) */ + CMP_OutputInit(CMP_2, &OutputInitStruct); + + PMU_BGPCmd(ENABLE); + CMP_Cmd(CMP_2, ENABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/target_isr.c new file mode 100644 index 0000000000..5239eb7d3a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/target_isr.c @@ -0,0 +1,308 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if(CMP_GetINTStatus(CMP_2)) + { + CMP_ClearINTStatus(CMP_2); + printf("CMP_2 CMPCNT %d\r\n", (unsigned int)ANA->CMPCNT2); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_ExtSignalToBGP/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d5c4adb2cc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..c72beb1ff7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 106 + 106 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/main.c new file mode 100644 index 0000000000..c879c97f46 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/main.c @@ -0,0 +1,130 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + CMP_TypeDef InitStruct; + CMP_CountTypeDef CountInitStruct; + CMP_INTTypeDef INTInitStruct; + CMP_OutputTypeDef OutputInitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* Forbidden Comparator1 input pins: + - P input, IOE8 + - N input, IOE9 */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; + GPIOBToF_Init(GPIOE, &GPIO_InitStruct); + + CMP_DeInit(CMP_1); + CMP_StructInit(&InitStruct); + InitStruct.DebSel = CMP_DEB_RTCCLK_2; /* 2 32KHz de-bounce */ + InitStruct.SignalSourceSel = CMP_SIGNALSRC_PPIN_TO_NPIN; /* Compare P to N */ + CMP_Init(CMP_1,&InitStruct); + + PMU_BGPCmd(ENABLE); + + CMP_CountStructInit(&CountInitStruct); + CountInitStruct.ModeSel = CMP_MODE_RISING; /* Rising edge */ + CountInitStruct.CheckPeriod = CMP_PERIOD_7_8125MS; /* Checked every 7.8125ms */ + CountInitStruct.CheckNum = CMP_CHKNUM_4; /* Checked data 4 times */ + CMP_CountInit(CMP_1, &CountInitStruct); + + /* Comparator interrupt enable control. */ + CMP_INTStructInit(&INTInitStruct); + INTInitStruct.INTNumSel = CMP_INTNUM_1; + INTInitStruct.SubSel = CMP_COUNT_NOSUB; + INTInitStruct.THRNum = 9; + CMP_INTInit(CMP_1, &INTInitStruct); + + CMP_INTConfig(CMP_1, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 0); + + /* CMP2 output, IOE7 */ + CMP_OutputStructInit(&OutputInitStruct); + OutputInitStruct.DebSel = CMP_OUTPUT_DEB; + OutputInitStruct.OutputSel = ENABLE; + CMP_OutputInit(CMP_1, &OutputInitStruct); + + /* Enable Comparator1 */ + CMP_Cmd(CMP_1, ENABLE); + CMP_ClearCNTValue(CMP_1); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/target_isr.c new file mode 100644 index 0000000000..f1d4e03244 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/target_isr.c @@ -0,0 +1,308 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if(CMP_GetINTStatus(CMP_1)) + { + CMP_ClearINTStatus(CMP_1); + printf("Enter CMP_1 interrupt, CMPCNT: %d\r\n", (unsigned int)ANA->CMPCNT1); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_TwoExtSignals/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..243110e454 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..ab6946bedb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 109 + 109 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/main.c new file mode 100644 index 0000000000..1c0bf5f071 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/main.c @@ -0,0 +1,140 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + CMP_TypeDef InitStruct; + CMP_CountTypeDef CountInitStruct; + CMP_INTTypeDef INTInitStruct; + + test_success = 0; + + Clock_Init(); + + /* Initializes FLASH 1USCYCLE. */ + FLASH_CycleInit(); + + Stdio_Init(); + + /* Forbidden Comparator2 N input pin, IOA5 */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + CMP_DeInit(CMP_2); + CMP_StructInit(&InitStruct); + InitStruct.DebSel = CMP_DEB_RTCCLK_2; /* 2 32KHz de-bounce */ + InitStruct.SignalSourceSel = CMP_SIGNALSRC_PBAT_TO_NPIN; /* Compare BATRTC to N */ + CMP_Init(CMP_2, &InitStruct); + + CMP_CountStructInit(&CountInitStruct); + CountInitStruct.ModeSel = CMP_MODE_RISING; /* Comparator2 mode rising, ouput 0->1, generate wake-up signal */ + CountInitStruct.CheckPeriod = CMP_PERIOD_7_8125MS; /* Checked every 7.8125ms */ + CountInitStruct.CheckNum = CMP_CHKNUM_4; /* Checked data 4 times */ + CMP_CountInit(CMP_2, &CountInitStruct); + + CMP_INTStructInit(&INTInitStruct); + INTInitStruct.INTNumSel = CMP_INTNUM_1; /* Every time a subtraction is made, an interrupt is generated */ + INTInitStruct.SubSel = CMP_COUNT_SUB; /* If the Comparator2 counter exceeds the \ + CMP2_THR, the CMP2_THR is subtracted until \ + the Comparator2 counter is less than the CMP2_THR*/ + INTInitStruct.THRNum = 5; /* Every 6 interrupts will be triggered */ + CMP_INTInit(CMP_2, &INTInitStruct); + + /* Clear Comparator2 interrupt flag */ + CMP_ClearINTStatus(CMP_2); + /* Enable Comparator2 interrupt, ANA NVIC interrupt */ + CMP_INTConfig(CMP_2, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 0); + + PMU_BGPCmd(ENABLE); + /* Enable Comparator2 */ + CMP_Cmd(CMP_2, ENABLE); + + test_success = 1; + + while(1) + { + /* Disable WDT, enter sleep mode */ + printf("Enter sleep mode\r\n"); + WDT_Disable(); + if (PMU_EnterSleepMode()) + { + printf("Enter sleep fail\r\n"); + while (1); + } + + /* Quit sleep mode */ + Stdio_Init(); + printf("Exit sleep mode, CMP2 CMPCNT: %d\r\n", (uint32_t)ANA->CMPCNT2); + WDT_Clear(); + } + +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/target_isr.c new file mode 100644 index 0000000000..103269290a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/target_isr.c @@ -0,0 +1,307 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if (CMP_GetINTStatus(CMP_2)) + { + CMP_ClearINTStatus(CMP_2); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CMP/CMP_WakeUp_Sleep/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.ewd @@ -0,0 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+ + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..9a75f07195 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 84 + 84 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/main.c new file mode 100644 index 0000000000..e837c62a4e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/main.c @@ -0,0 +1,108 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + uint32_t data_a[2] = { 0xFFFFFFFF, 0xFFFFFFFF }; + uint32_t data_b[2] = { 5, 0x80000000 }; + uint32_t data_o[2] = { 0 }; + + test_success = 0; + + /* Clock initialization */ + Clock_Init(); + /* Print initialization */ + Stdio_Init(); + + /* Configure address */ + CRYPT_AddressAConfig((uint32_t)&data_a[0]); + CRYPT_AddressBConfig((uint32_t)&data_b[0]); + CRYPT_AddressOConfig((uint32_t)&data_o[0]); + + /* Start operation */ + CRYPT_StartAdd(CRYPT_LENGTH_64, CRYPT_STOPCPU); + /* Waiting for operation done */ + CRYPT_WaitForLastOperation(); + + printf("Carry bit is %d\r\n", CRYPT_GetCarryBorrowBit()); +#ifdef __GNUC__ + printf("Result[63:32] 0x%08lx\r\n", data_o[1]); + printf("Result[31: 0] 0x%08lx\r\n", data_o[0]); +#else + printf("Result[63:32] 0x%08x\r\n", data_o[1]); + printf("Result[31: 0] 0x%08x\r\n", data_o[0]); +#endif + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_Add/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/IAR_Kill.bat b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/IAR_Kill.bat new file mode 100644 index 0000000000..a6e07b0aa7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/IAR_Kill.bat @@ -0,0 +1,8 @@ +@echo off + +del /s /a *.lst *.pbi *.cout *.pbd *.browse *.wsdt *.map *.dni *.dep *.ewt *.dbgdt *.tmp 2>nul +for /r . %%d in (.) do rd /s /q "%%d\Debug" 2>nul +for /r . %%d in (.) do rd /s /q "%%d\Release" 2>nul +for /r . %%d in (.) do rd /s /q "%%d\settings" 2>nul + +exit \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.ewp new file mode 100644 index 0000000000..a26d080d15 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.ewp @@ -0,0 +1,2019 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\types.h + + + $PROJ_DIR$\..\Src\uECC.c + + + $PROJ_DIR$\..\Src\uECC.h + + + $PROJ_DIR$\..\Src\uECC_vli.h + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/main.h new file mode 100644 index 0000000000..cbf53ba51f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/main.h @@ -0,0 +1,30 @@ +/** + * @file main.h + * @author Application Team + * @version V4.3.0 + * @date 2018-09-04 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#include "uECC.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/target_isr.h new file mode 100644 index 0000000000..34859a1c65 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V4.3.0 + * @date 2018-09-04 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/v_stdio.h new file mode 100644 index 0000000000..af8d67c073 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V4.3.0 + * @date 2018-09-04 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/asm_arm.inc b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/asm_arm.inc new file mode 100644 index 0000000000..fbc456eecb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/asm_arm.inc @@ -0,0 +1,822 @@ +/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_ASM_ARM_H_ +#define _UECC_ASM_ARM_H_ + +#if (uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1) + #define uECC_MIN_WORDS 8 +#endif +#if uECC_SUPPORTS_secp224r1 + #undef uECC_MIN_WORDS + #define uECC_MIN_WORDS 7 +#endif +#if uECC_SUPPORTS_secp192r1 + #undef uECC_MIN_WORDS + #define uECC_MIN_WORDS 6 +#endif +#if uECC_SUPPORTS_secp160r1 + #undef uECC_MIN_WORDS + #define uECC_MIN_WORDS 5 +#endif + +#if (uECC_PLATFORM == uECC_arm_thumb) + #define REG_RW "+l" + #define REG_WRITE "=l" +#else + #define REG_RW "+r" + #define REG_WRITE "=r" +#endif + +#if (uECC_PLATFORM == uECC_arm_thumb || uECC_PLATFORM == uECC_arm_thumb2) + #define REG_RW_LO "+l" + #define REG_WRITE_LO "=l" +#else + #define REG_RW_LO "+r" + #define REG_WRITE_LO "=r" +#endif + +#if (uECC_PLATFORM == uECC_arm_thumb2) + #define RESUME_SYNTAX +#else + #define RESUME_SYNTAX ".syntax divided \n\t" +#endif + +#if (uECC_OPTIMIZATION_LEVEL >= 2) + +uECC_VLI_API uECC_word_t uECC_vli_add(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { +#if (uECC_MAX_WORDS != uECC_MIN_WORDS) + #if (uECC_PLATFORM == uECC_arm_thumb) || (uECC_PLATFORM == uECC_arm_thumb2) + uint32_t jump = (uECC_MAX_WORDS - num_words) * 4 * 2 + 1; + #else /* ARM */ + uint32_t jump = (uECC_MAX_WORDS - num_words) * 4 * 4; + #endif +#endif + uint32_t carry; + uint32_t left_word; + uint32_t right_word; + + __asm volatile ( +/* ".syntax unified \n\t" */ + "movs %[carry], #0 \n\t" + #if (uECC_MAX_WORDS != uECC_MIN_WORDS) + "adr %[left], 1f \n\t" + ".align 4 \n\t" + "adds %[jump], %[left] \n\t" + #endif + + "ldmia %[lptr]!, {%[left]} \n\t" + "ldmia %[rptr]!, {%[right]} \n\t" + "adds %[left], %[right] \n\t" + "stmia %[dptr]!, {%[left]} \n\t" + + #if (uECC_MAX_WORDS != uECC_MIN_WORDS) + "bx %[jump] \n\t" + #endif + "1: \n\t" + REPEAT(DEC(uECC_MAX_WORDS), + "ldmia %[lptr]!, {%[left]} \n\t" + "ldmia %[rptr]!, {%[right]} \n\t" + "adcs %[left], %[right] \n\t" + "stmia %[dptr]!, {%[left]} \n\t") + + "adcs %[carry], %[carry] \n\t" + RESUME_SYNTAX + : [dptr] REG_RW_LO (result), [lptr] REG_RW_LO (left), [rptr] REG_RW_LO (right), + #if (uECC_MAX_WORDS != uECC_MIN_WORDS) + [jump] REG_RW_LO (jump), + #endif + [carry] REG_WRITE_LO (carry), [left] REG_WRITE_LO (left_word), + [right] REG_WRITE_LO (right_word) + : + : "cc", "memory" + ); + return carry; +} +#define asm_add 1 + +uECC_VLI_API uECC_word_t uECC_vli_sub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { +#if (uECC_MAX_WORDS != uECC_MIN_WORDS) + #if (uECC_PLATFORM == uECC_arm_thumb) || (uECC_PLATFORM == uECC_arm_thumb2) + uint32_t jump = (uECC_MAX_WORDS - num_words) * 4 * 2 + 1; + #else /* ARM */ + uint32_t jump = (uECC_MAX_WORDS - num_words) * 4 * 4; + #endif +#endif + uint32_t carry; + uint32_t left_word; + uint32_t right_word; + + __asm volatile ( + ".syntax unified \n\t" + "movs %[carry], #0 \n\t" + #if (uECC_MAX_WORDS != uECC_MIN_WORDS) + "adr %[left], 1f \n\t" + ".align 4 \n\t" + "adds %[jump], %[left] \n\t" + #endif + + "ldmia %[lptr]!, {%[left]} \n\t" + "ldmia %[rptr]!, {%[right]} \n\t" + "subs %[left], %[right] \n\t" + "stmia %[dptr]!, {%[left]} \n\t" + + #if (uECC_MAX_WORDS != uECC_MIN_WORDS) + "bx %[jump] \n\t" + #endif + "1: \n\t" + REPEAT(DEC(uECC_MAX_WORDS), + "ldmia %[lptr]!, {%[left]} \n\t" + "ldmia %[rptr]!, {%[right]} \n\t" + "sbcs %[left], %[right] \n\t" + "stmia %[dptr]!, {%[left]} \n\t") + + "adcs %[carry], %[carry] \n\t" + RESUME_SYNTAX + : [dptr] REG_RW_LO (result), [lptr] REG_RW_LO (left), [rptr] REG_RW_LO (right), + #if (uECC_MAX_WORDS != uECC_MIN_WORDS) + [jump] REG_RW_LO (jump), + #endif + [carry] REG_WRITE_LO (carry), [left] REG_WRITE_LO (left_word), + [right] REG_WRITE_LO (right_word) + : + : "cc", "memory" + ); + return !carry; /* Note that on ARM, carry flag set means "no borrow" when subtracting + (for some reason...) */ +} +#define asm_sub 1 + +#endif /* (uECC_OPTIMIZATION_LEVEL >= 2) */ + +#if (uECC_OPTIMIZATION_LEVEL >= 3) + +#if (uECC_PLATFORM != uECC_arm_thumb) + +#if uECC_ARM_USE_UMAAL + #include "asm_arm_mult_square_umaal.inc" +#else + #include "asm_arm_mult_square.inc" +#endif + +#if (uECC_OPTIMIZATION_LEVEL == 3) + +uECC_VLI_API void uECC_vli_mult(uint32_t *result, + const uint32_t *left, + const uint32_t *right, + wordcount_t num_words) { + register uint32_t *r0 __asm__("r0") = result; + register const uint32_t *r1 __asm__("r1") = left; + register const uint32_t *r2 __asm__("r2") = right; + register uint32_t r3 __asm__("r3") = num_words; + + __asm__ volatile ( + ".syntax unified \n\t" +#if (uECC_MIN_WORDS == 5) + FAST_MULT_ASM_5 + #if (uECC_MAX_WORDS > 5) + FAST_MULT_ASM_5_TO_6 + #endif + #if (uECC_MAX_WORDS > 6) + FAST_MULT_ASM_6_TO_7 + #endif + #if (uECC_MAX_WORDS > 7) + FAST_MULT_ASM_7_TO_8 + #endif +#elif (uECC_MIN_WORDS == 6) + FAST_MULT_ASM_6 + #if (uECC_MAX_WORDS > 6) + FAST_MULT_ASM_6_TO_7 + #endif + #if (uECC_MAX_WORDS > 7) + FAST_MULT_ASM_7_TO_8 + #endif +#elif (uECC_MIN_WORDS == 7) + FAST_MULT_ASM_7 + #if (uECC_MAX_WORDS > 7) + FAST_MULT_ASM_7_TO_8 + #endif +#elif (uECC_MIN_WORDS == 8) + FAST_MULT_ASM_8 +#endif + "1: \n\t" + RESUME_SYNTAX + : "+r" (r0), "+r" (r1), "+r" (r2) + : "r" (r3) + : "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); +} +#define asm_mult 1 + +#if uECC_SQUARE_FUNC +uECC_VLI_API void uECC_vli_square(uECC_word_t *result, + const uECC_word_t *left, + wordcount_t num_words) { + register uint32_t *r0 __asm__("r0") = result; + register const uint32_t *r1 __asm__("r1") = left; + register uint32_t r2 __asm__("r2") = num_words; + + __asm__ volatile ( + ".syntax unified \n\t" +#if (uECC_MIN_WORDS == 5) + FAST_SQUARE_ASM_5 + #if (uECC_MAX_WORDS > 5) + FAST_SQUARE_ASM_5_TO_6 + #endif + #if (uECC_MAX_WORDS > 6) + FAST_SQUARE_ASM_6_TO_7 + #endif + #if (uECC_MAX_WORDS > 7) + FAST_SQUARE_ASM_7_TO_8 + #endif +#elif (uECC_MIN_WORDS == 6) + FAST_SQUARE_ASM_6 + #if (uECC_MAX_WORDS > 6) + FAST_SQUARE_ASM_6_TO_7 + #endif + #if (uECC_MAX_WORDS > 7) + FAST_SQUARE_ASM_7_TO_8 + #endif +#elif (uECC_MIN_WORDS == 7) + FAST_SQUARE_ASM_7 + #if (uECC_MAX_WORDS > 7) + FAST_SQUARE_ASM_7_TO_8 + #endif +#elif (uECC_MIN_WORDS == 8) + FAST_SQUARE_ASM_8 +#endif + + "1: \n\t" + RESUME_SYNTAX + : "+r" (r0), "+r" (r1) + : "r" (r2) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); +} +#define asm_square 1 +#endif /* uECC_SQUARE_FUNC */ + +#else /* (uECC_OPTIMIZATION_LEVEL > 3) */ + +uECC_VLI_API void uECC_vli_mult(uint32_t *result, + const uint32_t *left, + const uint32_t *right, + wordcount_t num_words) { + register uint32_t *r0 __asm__("r0") = result; + register const uint32_t *r1 __asm__("r1") = left; + register const uint32_t *r2 __asm__("r2") = right; + register uint32_t r3 __asm__("r3") = num_words; + +#if uECC_SUPPORTS_secp160r1 + if (num_words == 5) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_MULT_ASM_5 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1), "+r" (r2) + : "r" (r3) + : "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +#if uECC_SUPPORTS_secp192r1 + if (num_words == 6) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_MULT_ASM_6 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1), "+r" (r2) + : "r" (r3) + : "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +#if uECC_SUPPORTS_secp224r1 + if (num_words == 7) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_MULT_ASM_7 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1), "+r" (r2) + : "r" (r3) + : "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +#if (uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1) + if (num_words == 8) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_MULT_ASM_8 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1), "+r" (r2) + : "r" (r3) + : "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +} +#define asm_mult 1 + +#if uECC_SQUARE_FUNC +uECC_VLI_API void uECC_vli_square(uECC_word_t *result, + const uECC_word_t *left, + wordcount_t num_words) { + register uint32_t *r0 __asm__("r0") = result; + register const uint32_t *r1 __asm__("r1") = left; + register uint32_t r2 __asm__("r2") = num_words; + +#if uECC_SUPPORTS_secp160r1 + if (num_words == 5) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_SQUARE_ASM_5 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1) + : "r" (r2) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +#if uECC_SUPPORTS_secp192r1 + if (num_words == 6) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_SQUARE_ASM_6 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1) + : "r" (r2) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +#if uECC_SUPPORTS_secp224r1 + if (num_words == 7) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_SQUARE_ASM_7 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1) + : "r" (r2) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +#if (uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1) + if (num_words == 8) { + __asm__ volatile ( + ".syntax unified \n\t" + FAST_SQUARE_ASM_8 + RESUME_SYNTAX + : "+r" (r0), "+r" (r1) + : "r" (r2) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); + return; + } +#endif +} +#define asm_square 1 +#endif /* uECC_SQUARE_FUNC */ + +#endif /* (uECC_OPTIMIZATION_LEVEL > 3) */ + +#endif /* uECC_PLATFORM != uECC_arm_thumb */ + +#endif /* (uECC_OPTIMIZATION_LEVEL >= 3) */ + +/* ---- "Small" implementations ---- */ + +#if !asm_add +uECC_VLI_API uECC_word_t uECC_vli_add(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { + uint32_t carry = 0; + uint32_t left_word; + uint32_t right_word; + + __asm__ volatile ( + ".syntax unified \n\t" + "1: \n\t" + "ldmia %[lptr]!, {%[left]} \n\t" /* Load left word. */ + "ldmia %[rptr]!, {%[right]} \n\t" /* Load right word. */ + "lsrs %[carry], #1 \n\t" /* Set up carry flag (carry = 0 after this). */ + "adcs %[left], %[left], %[right] \n\t" /* Add with carry. */ + "adcs %[carry], %[carry], %[carry] \n\t" /* Store carry bit. */ + "stmia %[dptr]!, {%[left]} \n\t" /* Store result word. */ + "subs %[ctr], #1 \n\t" /* Decrement counter. */ + "bne 1b \n\t" /* Loop until counter == 0. */ + RESUME_SYNTAX + : [dptr] REG_RW (result), [lptr] REG_RW (left), [rptr] REG_RW (right), + [ctr] REG_RW (num_words), [carry] REG_RW (carry), + [left] REG_WRITE (left_word), [right] REG_WRITE (right_word) + : + : "cc", "memory" + ); + return carry; +} +#define asm_add 1 +#endif + +#if !asm_sub +uECC_VLI_API uECC_word_t uECC_vli_sub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { + uint32_t carry = 1; /* carry = 1 initially (means don't borrow) */ + uint32_t left_word; + uint32_t right_word; + + __asm__ volatile ( + ".syntax unified \n\t" + "1: \n\t" + "ldmia %[lptr]!, {%[left]} \n\t" /* Load left word. */ + "ldmia %[rptr]!, {%[right]} \n\t" /* Load right word. */ + "lsrs %[carry], #1 \n\t" /* Set up carry flag (carry = 0 after this). */ + "sbcs %[left], %[left], %[right] \n\t" /* Subtract with borrow. */ + "adcs %[carry], %[carry], %[carry] \n\t" /* Store carry bit. */ + "stmia %[dptr]!, {%[left]} \n\t" /* Store result word. */ + "subs %[ctr], #1 \n\t" /* Decrement counter. */ + "bne 1b \n\t" /* Loop until counter == 0. */ + RESUME_SYNTAX + : [dptr] REG_RW (result), [lptr] REG_RW (left), [rptr] REG_RW (right), + [ctr] REG_RW (num_words), [carry] REG_RW (carry), + [left] REG_WRITE (left_word), [right] REG_WRITE (right_word) + : + : "cc", "memory" + ); + return !carry; +} +#define asm_sub 1 +#endif + +#if !asm_mult +uECC_VLI_API void uECC_vli_mult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { +#if (uECC_PLATFORM != uECC_arm_thumb) + uint32_t c0 = 0; + uint32_t c1 = 0; + uint32_t c2 = 0; + uint32_t k = 0; + uint32_t i; + uint32_t t0, t1; + + __asm volatile ( + ".syntax unified \n\t" + + "1: \n\t" /* outer loop (k < num_words) */ + "movs %[i], #0 \n\t" /* i = 0 */ + "b 3f \n\t" + + "2: \n\t" /* outer loop (k >= num_words) */ + "movs %[i], %[k] \n\t" /* i = k */ + "subs %[i], %[last_word] \n\t" /* i = k - (num_words - 1) (times 4) */ + + "3: \n\t" /* inner loop */ + "subs %[t0], %[k], %[i] \n\t" /* t0 = k-i */ + + "ldr %[t1], [%[right], %[t0]] \n\t" /* t1 = right[k - i] */ + "ldr %[t0], [%[left], %[i]] \n\t" /* t0 = left[i] */ + + "umull %[t0], %[t1], %[t0], %[t1] \n\t" /* (t0, t1) = left[i] * right[k - i] */ + + "adds %[c0], %[c0], %[t0] \n\t" /* add low word to c0 */ + "adcs %[c1], %[c1], %[t1] \n\t" /* add high word to c1, including carry */ + "adcs %[c2], %[c2], #0 \n\t" /* add carry to c2 */ + + "adds %[i], #4 \n\t" /* i += 4 */ + "cmp %[i], %[last_word] \n\t" /* i > (num_words - 1) (times 4)? */ + "bgt 4f \n\t" /* if so, exit the loop */ + "cmp %[i], %[k] \n\t" /* i <= k? */ + "ble 3b \n\t" /* if so, continue looping */ + + "4: \n\t" /* end inner loop */ + + "str %[c0], [%[result], %[k]] \n\t" /* result[k] = c0 */ + "mov %[c0], %[c1] \n\t" /* c0 = c1 */ + "mov %[c1], %[c2] \n\t" /* c1 = c2 */ + "movs %[c2], #0 \n\t" /* c2 = 0 */ + "adds %[k], #4 \n\t" /* k += 4 */ + "cmp %[k], %[last_word] \n\t" /* k <= (num_words - 1) (times 4) ? */ + "ble 1b \n\t" /* if so, loop back, start with i = 0 */ + "cmp %[k], %[last_word], lsl #1 \n\t" /* k <= (num_words * 2 - 2) (times 4) ? */ + "ble 2b \n\t" /* if so, loop back, start with i = (k + 1) - num_words */ + /* end outer loop */ + + "str %[c0], [%[result], %[k]] \n\t" /* result[num_words * 2 - 1] = c0 */ + RESUME_SYNTAX +/* : [c0] "+r" (c0), [c1] "+r" (c1), [c2] "+r" (c2), */ + : [c0] "=r" (c0), [c1] "=r" (c1), [c2] "=r" (c2), + [k] "+r" (k), [i] "=&r" (i), [t0] "=&r" (t0), [t1] "=&r" (t1) + : [result] "r" (result), [left] "r" (left), [right] "r" (right), + [last_word] "r" ((num_words - 1) * 4) + : "cc", "memory" + ); + +#else /* Thumb-1 */ + uint32_t r4, r5, r6, r7; + + __asm__ volatile ( + ".syntax unified \n\t" + "subs %[r3], #1 \n\t" /* r3 = num_words - 1 */ + "lsls %[r3], #2 \n\t" /* r3 = (num_words - 1) * 4 */ + "mov r8, %[r3] \n\t" /* r8 = (num_words - 1) * 4 */ + "lsls %[r3], #1 \n\t" /* r3 = (num_words - 1) * 8 */ + "mov r9, %[r3] \n\t" /* r9 = (num_words - 1) * 8 */ + "movs %[r3], #0 \n\t" /* c0 = 0 */ + "movs %[r4], #0 \n\t" /* c1 = 0 */ + "movs %[r5], #0 \n\t" /* c2 = 0 */ + "movs %[r6], #0 \n\t" /* k = 0 */ + + "push {%[r0]} \n\t" /* keep result on the stack */ + + "1: \n\t" /* outer loop (k < num_words) */ + "movs %[r7], #0 \n\t" /* r7 = i = 0 */ + "b 3f \n\t" + + "2: \n\t" /* outer loop (k >= num_words) */ + "movs %[r7], %[r6] \n\t" /* r7 = k */ + "mov %[r0], r8 \n\t" /* r0 = (num_words - 1) * 4 */ + "subs %[r7], %[r0] \n\t" /* r7 = i = k - (num_words - 1) (times 4) */ + + "3: \n\t" /* inner loop */ + "mov r10, %[r3] \n\t" + "mov r11, %[r4] \n\t" + "mov r12, %[r5] \n\t" + "mov r14, %[r6] \n\t" + "subs %[r0], %[r6], %[r7] \n\t" /* r0 = k - i */ + + "ldr %[r4], [%[r2], %[r0]] \n\t" /* r4 = right[k - i] */ + "ldr %[r0], [%[r1], %[r7]] \n\t" /* r0 = left[i] */ + + "lsrs %[r3], %[r0], #16 \n\t" /* r3 = a1 */ + "uxth %[r0], %[r0] \n\t" /* r0 = a0 */ + + "lsrs %[r5], %[r4], #16 \n\t" /* r5 = b1 */ + "uxth %[r4], %[r4] \n\t" /* r4 = b0 */ + + "movs %[r6], %[r3] \n\t" /* r6 = a1 */ + "muls %[r6], %[r5], %[r6] \n\t" /* r6 = a1 * b1 */ + "muls %[r3], %[r4], %[r3] \n\t" /* r3 = b0 * a1 */ + "muls %[r5], %[r0], %[r5] \n\t" /* r5 = a0 * b1 */ + "muls %[r0], %[r4], %[r0] \n\t" /* r0 = a0 * b0 */ + + /* Add middle terms */ + "lsls %[r4], %[r3], #16 \n\t" + "lsrs %[r3], %[r3], #16 \n\t" + "adds %[r0], %[r4] \n\t" + "adcs %[r6], %[r3] \n\t" + + "lsls %[r4], %[r5], #16 \n\t" + "lsrs %[r5], %[r5], #16 \n\t" + "adds %[r0], %[r4] \n\t" + "adcs %[r6], %[r5] \n\t" + + "mov %[r3], r10\n\t" + "mov %[r4], r11\n\t" + "mov %[r5], r12\n\t" + "adds %[r3], %[r0] \n\t" /* add low word to c0 */ + "adcs %[r4], %[r6] \n\t" /* add high word to c1, including carry */ + "movs %[r0], #0 \n\t" /* r0 = 0 (does not affect carry bit) */ + "adcs %[r5], %[r0] \n\t" /* add carry to c2 */ + + "mov %[r6], r14\n\t" /* r6 = k */ + + "adds %[r7], #4 \n\t" /* i += 4 */ + "cmp %[r7], r8 \n\t" /* i > (num_words - 1) (times 4)? */ + "bgt 4f \n\t" /* if so, exit the loop */ + "cmp %[r7], %[r6] \n\t" /* i <= k? */ + "ble 3b \n\t" /* if so, continue looping */ + + "4: \n\t" /* end inner loop */ + + "ldr %[r0], [sp, #0] \n\t" /* r0 = result */ + + "str %[r3], [%[r0], %[r6]] \n\t" /* result[k] = c0 */ + "mov %[r3], %[r4] \n\t" /* c0 = c1 */ + "mov %[r4], %[r5] \n\t" /* c1 = c2 */ + "movs %[r5], #0 \n\t" /* c2 = 0 */ + "adds %[r6], #4 \n\t" /* k += 4 */ + "cmp %[r6], r8 \n\t" /* k <= (num_words - 1) (times 4) ? */ + "ble 1b \n\t" /* if so, loop back, start with i = 0 */ + "cmp %[r6], r9 \n\t" /* k <= (num_words * 2 - 2) (times 4) ? */ + "ble 2b \n\t" /* if so, loop back, with i = (k + 1) - num_words */ + /* end outer loop */ + + "str %[r3], [%[r0], %[r6]] \n\t" /* result[num_words * 2 - 1] = c0 */ + "pop {%[r0]} \n\t" /* pop result off the stack */ + + ".syntax divided \n\t" + : [r3] "+l" (num_words), [r4] "=&l" (r4), + [r5] "=&l" (r5), [r6] "=&l" (r6), [r7] "=&l" (r7) + : [r0] "l" (result), [r1] "l" (left), [r2] "l" (right) + : "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); +#endif +} +#define asm_mult 1 +#endif + +#if uECC_SQUARE_FUNC +#if !asm_square +uECC_VLI_API void uECC_vli_square(uECC_word_t *result, + const uECC_word_t *left, + wordcount_t num_words) { +#if (uECC_PLATFORM != uECC_arm_thumb) + uint32_t c0 = 0; + uint32_t c1 = 0; + uint32_t c2 = 0; + uint32_t k = 0; + uint32_t i, tt; + uint32_t t0, t1; + + __asm volatile ( + ".syntax unified \n\t" + + "1: \n\t" /* outer loop (k < num_words) */ + "movs %[i], #0 \n\t" /* i = 0 */ + "b 3f \n\t" + + "2: \n\t" /* outer loop (k >= num_words) */ + "movs %[i], %[k] \n\t" /* i = k */ + "subs %[i], %[last_word] \n\t" /* i = k - (num_words - 1) (times 4) */ + + "3: \n\t" /* inner loop */ + "subs %[tt], %[k], %[i] \n\t" /* tt = k-i */ + + "ldr %[t1], [%[left], %[tt]] \n\t" /* t1 = left[k - i] */ + "ldr %[t0], [%[left], %[i]] \n\t" /* t0 = left[i] */ + + "umull %[t0], %[t1], %[t0], %[t1] \n\t" /* (t0, t1) = left[i] * right[k - i] */ + + "cmp %[i], %[tt] \n\t" /* (i < k - i) ? */ + "bge 4f \n\t" /* if i >= k - i, skip */ + "adds %[c0], %[c0], %[t0] \n\t" /* add low word to c0 */ + "adcs %[c1], %[c1], %[t1] \n\t" /* add high word to c1, including carry */ + "adcs %[c2], %[c2], #0 \n\t" /* add carry to c2 */ + + "4: \n\t" + "adds %[c0], %[c0], %[t0] \n\t" /* add low word to c0 */ + "adcs %[c1], %[c1], %[t1] \n\t" /* add high word to c1, including carry */ + "adcs %[c2], %[c2], #0 \n\t" /* add carry to c2 */ + + "adds %[i], #4 \n\t" /* i += 4 */ + "cmp %[i], %[k] \n\t" /* i >= k? */ + "bge 5f \n\t" /* if so, exit the loop */ + "subs %[tt], %[k], %[i] \n\t" /* tt = k - i */ + "cmp %[i], %[tt] \n\t" /* i <= k - i? */ + "ble 3b \n\t" /* if so, continue looping */ + + "5: \n\t" /* end inner loop */ + + "str %[c0], [%[result], %[k]] \n\t" /* result[k] = c0 */ + "mov %[c0], %[c1] \n\t" /* c0 = c1 */ + "mov %[c1], %[c2] \n\t" /* c1 = c2 */ + "movs %[c2], #0 \n\t" /* c2 = 0 */ + "adds %[k], #4 \n\t" /* k += 4 */ + "cmp %[k], %[last_word] \n\t" /* k <= (num_words - 1) (times 4) ? */ + "ble 1b \n\t" /* if so, loop back, start with i = 0 */ + "cmp %[k], %[last_word], lsl #1 \n\t" /* k <= (num_words * 2 - 2) (times 4) ? */ + "ble 2b \n\t" /* if so, loop back, start with i = (k + 1) - num_words */ + /* end outer loop */ + + "str %[c0], [%[result], %[k]] \n\t" /* result[num_words * 2 - 1] = c0 */ + RESUME_SYNTAX +/* : [c0] "+r" (c0), [c1] "+r" (c1), [c2] "+r" (c2), */ + : [c0] "=r" (c0), [c1] "=r" (c1), [c2] "=r" (c2), + [k] "+r" (k), [i] "=&r" (i), [tt] "=&r" (tt), [t0] "=&r" (t0), [t1] "=&r" (t1) + : [result] "r" (result), [left] "r" (left), [last_word] "r" ((num_words - 1) * 4) + : "cc", "memory" + ); + +#else + uint32_t r3, r4, r5, r6, r7; + + __asm__ volatile ( + ".syntax unified \n\t" + "subs %[r2], #1 \n\t" /* r2 = num_words - 1 */ + "lsls %[r2], #2 \n\t" /* r2 = (num_words - 1) * 4 */ + "mov r8, %[r2] \n\t" /* r8 = (num_words - 1) * 4 */ + "lsls %[r2], #1 \n\t" /* r2 = (num_words - 1) * 8 */ + "mov r9, %[r2] \n\t" /* r9 = (num_words - 1) * 8 */ + "movs %[r2], #0 \n\t" /* c0 = 0 */ + "movs %[r3], #0 \n\t" /* c1 = 0 */ + "movs %[r4], #0 \n\t" /* c2 = 0 */ + "movs %[r5], #0 \n\t" /* k = 0 */ + + "push {%[r0]} \n\t" /* keep result on the stack */ + + "1: \n\t" /* outer loop (k < num_words) */ + "movs %[r6], #0 \n\t" /* r6 = i = 0 */ + "b 3f \n\t" + + "2: \n\t" /* outer loop (k >= num_words) */ + "movs %[r6], %[r5] \n\t" /* r6 = k */ + "mov %[r0], r8 \n\t" /* r0 = (num_words - 1) * 4 */ + "subs %[r6], %[r0] \n\t" /* r6 = i = k - (num_words - 1) (times 4) */ + + "3: \n\t" /* inner loop */ + "mov r10, %[r2] \n\t" + "mov r11, %[r3] \n\t" + "mov r12, %[r4] \n\t" + "mov r14, %[r5] \n\t" + "subs %[r7], %[r5], %[r6] \n\t" /* r7 = k - i */ + + "ldr %[r3], [%[r1], %[r7]] \n\t" /* r3 = left[k - i] */ + "ldr %[r0], [%[r1], %[r6]] \n\t" /* r0 = left[i] */ + + "lsrs %[r2], %[r0], #16 \n\t" /* r2 = a1 */ + "uxth %[r0], %[r0] \n\t" /* r0 = a0 */ + + "lsrs %[r4], %[r3], #16 \n\t" /* r4 = b1 */ + "uxth %[r3], %[r3] \n\t" /* r3 = b0 */ + + "movs %[r5], %[r2] \n\t" /* r5 = a1 */ + "muls %[r5], %[r4], %[r5] \n\t" /* r5 = a1 * b1 */ + "muls %[r2], %[r3], %[r2] \n\t" /* r2 = b0 * a1 */ + "muls %[r4], %[r0], %[r4] \n\t" /* r4 = a0 * b1 */ + "muls %[r0], %[r3], %[r0] \n\t" /* r0 = a0 * b0 */ + + /* Add middle terms */ + "lsls %[r3], %[r2], #16 \n\t" + "lsrs %[r2], %[r2], #16 \n\t" + "adds %[r0], %[r3] \n\t" + "adcs %[r5], %[r2] \n\t" + + "lsls %[r3], %[r4], #16 \n\t" + "lsrs %[r4], %[r4], #16 \n\t" + "adds %[r0], %[r3] \n\t" + "adcs %[r5], %[r4] \n\t" + + /* Add to acc, doubling if necessary */ + "mov %[r2], r10\n\t" + "mov %[r3], r11\n\t" + "mov %[r4], r12\n\t" + + "cmp %[r6], %[r7] \n\t" /* (i < k - i) ? */ + "bge 4f \n\t" /* if i >= k - i, skip */ + "movs %[r7], #0 \n\t" /* r7 = 0 */ + "adds %[r2], %[r0] \n\t" /* add low word to c0 */ + "adcs %[r3], %[r5] \n\t" /* add high word to c1, including carry */ + "adcs %[r4], %[r7] \n\t" /* add carry to c2 */ + "4: \n\t" + "movs %[r7], #0 \n\t" /* r7 = 0 */ + "adds %[r2], %[r0] \n\t" /* add low word to c0 */ + "adcs %[r3], %[r5] \n\t" /* add high word to c1, including carry */ + "adcs %[r4], %[r7] \n\t" /* add carry to c2 */ + + "mov %[r5], r14\n\t" /* r5 = k */ + + "adds %[r6], #4 \n\t" /* i += 4 */ + "cmp %[r6], %[r5] \n\t" /* i >= k? */ + "bge 5f \n\t" /* if so, exit the loop */ + "subs %[r7], %[r5], %[r6] \n\t" /* r7 = k - i */ + "cmp %[r6], %[r7] \n\t" /* i <= k - i? */ + "ble 3b \n\t" /* if so, continue looping */ + + "5: \n\t" /* end inner loop */ + + "ldr %[r0], [sp, #0] \n\t" /* r0 = result */ + + "str %[r2], [%[r0], %[r5]] \n\t" /* result[k] = c0 */ + "mov %[r2], %[r3] \n\t" /* c0 = c1 */ + "mov %[r3], %[r4] \n\t" /* c1 = c2 */ + "movs %[r4], #0 \n\t" /* c2 = 0 */ + "adds %[r5], #4 \n\t" /* k += 4 */ + "cmp %[r5], r8 \n\t" /* k <= (num_words - 1) (times 4) ? */ + "ble 1b \n\t" /* if so, loop back, start with i = 0 */ + "cmp %[r5], r9 \n\t" /* k <= (num_words * 2 - 2) (times 4) ? */ + "ble 2b \n\t" /* if so, loop back, with i = (k + 1) - num_words */ + /* end outer loop */ + + "str %[r2], [%[r0], %[r5]] \n\t" /* result[num_words * 2 - 1] = c0 */ + "pop {%[r0]} \n\t" /* pop result off the stack */ + + ".syntax divided \n\t" + : [r2] "+l" (num_words), [r3] "=&l" (r3), [r4] "=&l" (r4), + [r5] "=&l" (r5), [r6] "=&l" (r6), [r7] "=&l" (r7) + : [r0] "l" (result), [r1] "l" (left) + : "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory" + ); +#endif +} +#define asm_square 1 +#endif +#endif /* uECC_SQUARE_FUNC */ + +#endif /* _UECC_ASM_ARM_H_ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/curve-specific.inc b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/curve-specific.inc new file mode 100644 index 0000000000..9e81c6a4f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/curve-specific.inc @@ -0,0 +1,1247 @@ + +#ifndef _UECC_CURVE_SPECIFIC_H_ +#define _UECC_CURVE_SPECIFIC_H_ + +#define num_bytes_secp160r1 20 +#define num_bytes_secp192r1 24 +#define num_bytes_secp224r1 28 +#define num_bytes_secp256r1 32 +#define num_bytes_secp256k1 32 + +#if (uECC_WORD_SIZE == 1) + +#define num_words_secp160r1 20 +#define num_words_secp192r1 24 +#define num_words_secp224r1 28 +#define num_words_secp256r1 32 +#define num_words_secp256k1 32 + +#define BYTES_TO_WORDS_8(a, b, c, d, e, f, g, h) \ + 0x##a, 0x##b, 0x##c, 0x##d, 0x##e, 0x##f, 0x##g, 0x##h +#define BYTES_TO_WORDS_4(a, b, c, d) 0x##a, 0x##b, 0x##c, 0x##d + +#elif (uECC_WORD_SIZE == 4) + +#define num_words_secp160r1 5 +#define num_words_secp192r1 6 +#define num_words_secp224r1 7 +#define num_words_secp256r1 8 +#define num_words_secp256k1 8 + +#define BYTES_TO_WORDS_8(a, b, c, d, e, f, g, h) 0x##d##c##b##a, 0x##h##g##f##e +#define BYTES_TO_WORDS_4(a, b, c, d) 0x##d##c##b##a + +#elif (uECC_WORD_SIZE == 8) + +#define num_words_secp160r1 3 +#define num_words_secp192r1 3 +#define num_words_secp224r1 4 +#define num_words_secp256r1 4 +#define num_words_secp256k1 4 + +#define BYTES_TO_WORDS_8(a, b, c, d, e, f, g, h) 0x##h##g##f##e##d##c##b##a##ull +#define BYTES_TO_WORDS_4(a, b, c, d) 0x##d##c##b##a##ull + +#endif /* uECC_WORD_SIZE */ + +#if uECC_SUPPORTS_secp160r1 || uECC_SUPPORTS_secp192r1 || \ + uECC_SUPPORTS_secp224r1 || uECC_SUPPORTS_secp256r1 +static void double_jacobian_default(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * Z1, + uECC_Curve curve) { + /* t1 = X, t2 = Y, t3 = Z */ + uECC_word_t t4[uECC_MAX_WORDS]; + uECC_word_t t5[uECC_MAX_WORDS]; + wordcount_t num_words = curve->num_words; + + if (uECC_vli_isZero(Z1, num_words)) { + return; + } + + uECC_vli_modSquare_fast(t4, Y1, curve); /* t4 = y1^2 */ + uECC_vli_modMult_fast(t5, X1, t4, curve); /* t5 = x1*y1^2 = A */ + uECC_vli_modSquare_fast(t4, t4, curve); /* t4 = y1^4 */ + uECC_vli_modMult_fast(Y1, Y1, Z1, curve); /* t2 = y1*z1 = z3 */ + uECC_vli_modSquare_fast(Z1, Z1, curve); /* t3 = z1^2 */ + + uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = x1 + z1^2 */ + uECC_vli_modAdd(Z1, Z1, Z1, curve->p, num_words); /* t3 = 2*z1^2 */ + uECC_vli_modSub(Z1, X1, Z1, curve->p, num_words); /* t3 = x1 - z1^2 */ + uECC_vli_modMult_fast(X1, X1, Z1, curve); /* t1 = x1^2 - z1^4 */ + + uECC_vli_modAdd(Z1, X1, X1, curve->p, num_words); /* t3 = 2*(x1^2 - z1^4) */ + uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = 3*(x1^2 - z1^4) */ + if (uECC_vli_testBit(X1, 0)) { + uECC_word_t l_carry = uECC_vli_add(X1, X1, curve->p, num_words); + uECC_vli_rshift1(X1, num_words); + X1[num_words - 1] |= l_carry << (uECC_WORD_BITS - 1); + } else { + uECC_vli_rshift1(X1, num_words); + } + /* t1 = 3/2*(x1^2 - z1^4) = B */ + + uECC_vli_modSquare_fast(Z1, X1, curve); /* t3 = B^2 */ + uECC_vli_modSub(Z1, Z1, t5, curve->p, num_words); /* t3 = B^2 - A */ + uECC_vli_modSub(Z1, Z1, t5, curve->p, num_words); /* t3 = B^2 - 2A = x3 */ + uECC_vli_modSub(t5, t5, Z1, curve->p, num_words); /* t5 = A - x3 */ + uECC_vli_modMult_fast(X1, X1, t5, curve); /* t1 = B * (A - x3) */ + uECC_vli_modSub(t4, X1, t4, curve->p, num_words); /* t4 = B * (A - x3) - y1^4 = y3 */ + + uECC_vli_set(X1, Z1, num_words); + uECC_vli_set(Z1, Y1, num_words); + uECC_vli_set(Y1, t4, num_words); +} + +/* Computes result = x^3 + ax + b. result must not overlap x. */ +static void x_side_default(uECC_word_t *result, const uECC_word_t *x, uECC_Curve curve) { + uECC_word_t _3[uECC_MAX_WORDS] = {3}; /* -a = 3 */ + wordcount_t num_words = curve->num_words; + + uECC_vli_modSquare_fast(result, x, curve); /* r = x^2 */ + uECC_vli_modSub(result, result, _3, curve->p, num_words); /* r = x^2 - 3 */ + uECC_vli_modMult_fast(result, result, x, curve); /* r = x^3 - 3x */ + uECC_vli_modAdd(result, result, curve->b, curve->p, num_words); /* r = x^3 - 3x + b */ +} +#endif /* uECC_SUPPORTS_secp... */ + +#if uECC_SUPPORT_COMPRESSED_POINT +#if uECC_SUPPORTS_secp160r1 || uECC_SUPPORTS_secp192r1 || \ + uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1 +/* Compute a = sqrt(a) (mod curve_p). */ +static void mod_sqrt_default(uECC_word_t *a, uECC_Curve curve) { + bitcount_t i; + uECC_word_t p1[uECC_MAX_WORDS] = {1}; + uECC_word_t l_result[uECC_MAX_WORDS] = {1}; + wordcount_t num_words = curve->num_words; + + /* When curve->p == 3 (mod 4), we can compute + sqrt(a) = a^((curve->p + 1) / 4) (mod curve->p). */ + uECC_vli_add(p1, curve->p, p1, num_words); /* p1 = curve_p + 1 */ + for (i = uECC_vli_numBits(p1, num_words) - 1; i > 1; --i) { + uECC_vli_modSquare_fast(l_result, l_result, curve); + if (uECC_vli_testBit(p1, i)) { + uECC_vli_modMult_fast(l_result, l_result, a, curve); + } + } + uECC_vli_set(a, l_result, num_words); +} +#endif /* uECC_SUPPORTS_secp... */ +#endif /* uECC_SUPPORT_COMPRESSED_POINT */ + +#if uECC_SUPPORTS_secp160r1 + +#if (uECC_OPTIMIZATION_LEVEL > 0) +static void vli_mmod_fast_secp160r1(uECC_word_t *result, uECC_word_t *product); +#endif + +static const struct uECC_Curve_t curve_secp160r1 = { + num_words_secp160r1, + num_bytes_secp160r1, + 161, /* num_n_bits */ + { BYTES_TO_WORDS_8(FF, FF, FF, 7F, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_4(FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(57, 22, 75, CA, D3, AE, 27, F9), + BYTES_TO_WORDS_8(C8, F4, 01, 00, 00, 00, 00, 00), + BYTES_TO_WORDS_8(00, 00, 00, 00, 01, 00, 00, 00) }, + { BYTES_TO_WORDS_8(82, FC, CB, 13, B9, 8B, C3, 68), + BYTES_TO_WORDS_8(89, 69, 64, 46, 28, 73, F5, 8E), + BYTES_TO_WORDS_4(68, B5, 96, 4A), + + BYTES_TO_WORDS_8(32, FB, C5, 7A, 37, 51, 23, 04), + BYTES_TO_WORDS_8(12, C9, DC, 59, 7D, 94, 68, 31), + BYTES_TO_WORDS_4(55, 28, A6, 23) }, + { BYTES_TO_WORDS_8(45, FA, 65, C5, AD, D4, D4, 81), + BYTES_TO_WORDS_8(9F, F8, AC, 65, 8B, 7A, BD, 54), + BYTES_TO_WORDS_4(FC, BE, 97, 1C) }, + &double_jacobian_default, +#if uECC_SUPPORT_COMPRESSED_POINT + &mod_sqrt_default, +#endif + &x_side_default, +#if (uECC_OPTIMIZATION_LEVEL > 0) + &vli_mmod_fast_secp160r1 +#endif +}; + +uECC_Curve uECC_secp160r1(void) { return &curve_secp160r1; } + +#if (uECC_OPTIMIZATION_LEVEL > 0 && !asm_mmod_fast_secp160r1) +/* Computes result = product % curve_p + see http://www.isys.uni-klu.ac.at/PDF/2001-0126-MT.pdf page 354 + + Note that this only works if log2(omega) < log2(p) / 2 */ +static void omega_mult_secp160r1(uECC_word_t *result, const uECC_word_t *right); +#if uECC_WORD_SIZE == 8 +static void vli_mmod_fast_secp160r1(uECC_word_t *result, uECC_word_t *product) { + uECC_word_t tmp[2 * num_words_secp160r1]; + uECC_word_t copy; + + uECC_vli_clear(tmp, num_words_secp160r1); + uECC_vli_clear(tmp + num_words_secp160r1, num_words_secp160r1); + + omega_mult_secp160r1(tmp, product + num_words_secp160r1 - 1); /* (Rq, q) = q * c */ + + product[num_words_secp160r1 - 1] &= 0xffffffff; + copy = tmp[num_words_secp160r1 - 1]; + tmp[num_words_secp160r1 - 1] &= 0xffffffff; + uECC_vli_add(result, product, tmp, num_words_secp160r1); /* (C, r) = r + q */ + uECC_vli_clear(product, num_words_secp160r1); + tmp[num_words_secp160r1 - 1] = copy; + omega_mult_secp160r1(product, tmp + num_words_secp160r1 - 1); /* Rq*c */ + uECC_vli_add(result, result, product, num_words_secp160r1); /* (C1, r) = r + Rq*c */ + + while (uECC_vli_cmp_unsafe(result, curve_secp160r1.p, num_words_secp160r1) > 0) { + uECC_vli_sub(result, result, curve_secp160r1.p, num_words_secp160r1); + } +} + +static void omega_mult_secp160r1(uint64_t *result, const uint64_t *right) { + uint32_t carry; + unsigned i; + + /* Multiply by (2^31 + 1). */ + carry = 0; + for (i = 0; i < num_words_secp160r1; ++i) { + uint64_t tmp = (right[i] >> 32) | (right[i + 1] << 32); + result[i] = (tmp << 31) + tmp + carry; + carry = (tmp >> 33) + (result[i] < tmp || (carry && result[i] == tmp)); + } + result[i] = carry; +} +#else +static void vli_mmod_fast_secp160r1(uECC_word_t *result, uECC_word_t *product) { + uECC_word_t tmp[2 * num_words_secp160r1]; + uECC_word_t carry; + + uECC_vli_clear(tmp, num_words_secp160r1); + uECC_vli_clear(tmp + num_words_secp160r1, num_words_secp160r1); + + omega_mult_secp160r1(tmp, product + num_words_secp160r1); /* (Rq, q) = q * c */ + + carry = uECC_vli_add(result, product, tmp, num_words_secp160r1); /* (C, r) = r + q */ + uECC_vli_clear(product, num_words_secp160r1); + omega_mult_secp160r1(product, tmp + num_words_secp160r1); /* Rq*c */ + carry += uECC_vli_add(result, result, product, num_words_secp160r1); /* (C1, r) = r + Rq*c */ + + while (carry > 0) { + --carry; + uECC_vli_sub(result, result, curve_secp160r1.p, num_words_secp160r1); + } + if (uECC_vli_cmp_unsafe(result, curve_secp160r1.p, num_words_secp160r1) > 0) { + uECC_vli_sub(result, result, curve_secp160r1.p, num_words_secp160r1); + } +} +#endif + +#if uECC_WORD_SIZE == 1 +static void omega_mult_secp160r1(uint8_t *result, const uint8_t *right) { + uint8_t carry; + uint8_t i; + + /* Multiply by (2^31 + 1). */ + uECC_vli_set(result + 4, right, num_words_secp160r1); /* 2^32 */ + uECC_vli_rshift1(result + 4, num_words_secp160r1); /* 2^31 */ + result[3] = right[0] << 7; /* get last bit from shift */ + + carry = uECC_vli_add(result, result, right, num_words_secp160r1); /* 2^31 + 1 */ + for (i = num_words_secp160r1; carry; ++i) { + uint16_t sum = (uint16_t)result[i] + carry; + result[i] = (uint8_t)sum; + carry = sum >> 8; + } +} +#elif uECC_WORD_SIZE == 4 +static void omega_mult_secp160r1(uint32_t *result, const uint32_t *right) { + uint32_t carry; + unsigned i; + + /* Multiply by (2^31 + 1). */ + uECC_vli_set(result + 1, right, num_words_secp160r1); /* 2^32 */ + uECC_vli_rshift1(result + 1, num_words_secp160r1); /* 2^31 */ + result[0] = right[0] << 31; /* get last bit from shift */ + + carry = uECC_vli_add(result, result, right, num_words_secp160r1); /* 2^31 + 1 */ + for (i = num_words_secp160r1; carry; ++i) { + uint64_t sum = (uint64_t)result[i] + carry; + result[i] = (uint32_t)sum; + carry = sum >> 32; + } +} +#endif /* uECC_WORD_SIZE */ +#endif /* (uECC_OPTIMIZATION_LEVEL > 0 && !asm_mmod_fast_secp160r1) */ + +#endif /* uECC_SUPPORTS_secp160r1 */ + +#if uECC_SUPPORTS_secp192r1 + +#if (uECC_OPTIMIZATION_LEVEL > 0) +static void vli_mmod_fast_secp192r1(uECC_word_t *result, uECC_word_t *product); +#endif + +static const struct uECC_Curve_t curve_secp192r1 = { + num_words_secp192r1, + num_bytes_secp192r1, + 192, /* num_n_bits */ + { BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FE, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(31, 28, D2, B4, B1, C9, 6B, 14), + BYTES_TO_WORDS_8(36, F8, DE, 99, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(12, 10, FF, 82, FD, 0A, FF, F4), + BYTES_TO_WORDS_8(00, 88, A1, 43, EB, 20, BF, 7C), + BYTES_TO_WORDS_8(F6, 90, 30, B0, 0E, A8, 8D, 18), + + BYTES_TO_WORDS_8(11, 48, 79, 1E, A1, 77, F9, 73), + BYTES_TO_WORDS_8(D5, CD, 24, 6B, ED, 11, 10, 63), + BYTES_TO_WORDS_8(78, DA, C8, FF, 95, 2B, 19, 07) }, + { BYTES_TO_WORDS_8(B1, B9, 46, C1, EC, DE, B8, FE), + BYTES_TO_WORDS_8(49, 30, 24, 72, AB, E9, A7, 0F), + BYTES_TO_WORDS_8(E7, 80, 9C, E5, 19, 05, 21, 64) }, + &double_jacobian_default, +#if uECC_SUPPORT_COMPRESSED_POINT + &mod_sqrt_default, +#endif + &x_side_default, +#if (uECC_OPTIMIZATION_LEVEL > 0) + &vli_mmod_fast_secp192r1 +#endif +}; + +uECC_Curve uECC_secp192r1(void) { return &curve_secp192r1; } + +#if (uECC_OPTIMIZATION_LEVEL > 0) +/* Computes result = product % curve_p. + See algorithm 5 and 6 from http://www.isys.uni-klu.ac.at/PDF/2001-0126-MT.pdf */ +#if uECC_WORD_SIZE == 1 +static void vli_mmod_fast_secp192r1(uint8_t *result, uint8_t *product) { + uint8_t tmp[num_words_secp192r1]; + uint8_t carry; + + uECC_vli_set(result, product, num_words_secp192r1); + + uECC_vli_set(tmp, &product[24], num_words_secp192r1); + carry = uECC_vli_add(result, result, tmp, num_words_secp192r1); + + tmp[0] = tmp[1] = tmp[2] = tmp[3] = tmp[4] = tmp[5] = tmp[6] = tmp[7] = 0; + tmp[8] = product[24]; tmp[9] = product[25]; tmp[10] = product[26]; tmp[11] = product[27]; + tmp[12] = product[28]; tmp[13] = product[29]; tmp[14] = product[30]; tmp[15] = product[31]; + tmp[16] = product[32]; tmp[17] = product[33]; tmp[18] = product[34]; tmp[19] = product[35]; + tmp[20] = product[36]; tmp[21] = product[37]; tmp[22] = product[38]; tmp[23] = product[39]; + carry += uECC_vli_add(result, result, tmp, num_words_secp192r1); + + tmp[0] = tmp[8] = product[40]; + tmp[1] = tmp[9] = product[41]; + tmp[2] = tmp[10] = product[42]; + tmp[3] = tmp[11] = product[43]; + tmp[4] = tmp[12] = product[44]; + tmp[5] = tmp[13] = product[45]; + tmp[6] = tmp[14] = product[46]; + tmp[7] = tmp[15] = product[47]; + tmp[16] = tmp[17] = tmp[18] = tmp[19] = tmp[20] = tmp[21] = tmp[22] = tmp[23] = 0; + carry += uECC_vli_add(result, result, tmp, num_words_secp192r1); + + while (carry || uECC_vli_cmp_unsafe(curve_secp192r1.p, result, num_words_secp192r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp192r1.p, num_words_secp192r1); + } +} +#elif uECC_WORD_SIZE == 4 +static void vli_mmod_fast_secp192r1(uint32_t *result, uint32_t *product) { + uint32_t tmp[num_words_secp192r1]; + int carry; + + uECC_vli_set(result, product, num_words_secp192r1); + + uECC_vli_set(tmp, &product[6], num_words_secp192r1); + carry = uECC_vli_add(result, result, tmp, num_words_secp192r1); + + tmp[0] = tmp[1] = 0; + tmp[2] = product[6]; + tmp[3] = product[7]; + tmp[4] = product[8]; + tmp[5] = product[9]; + carry += uECC_vli_add(result, result, tmp, num_words_secp192r1); + + tmp[0] = tmp[2] = product[10]; + tmp[1] = tmp[3] = product[11]; + tmp[4] = tmp[5] = 0; + carry += uECC_vli_add(result, result, tmp, num_words_secp192r1); + + while (carry || uECC_vli_cmp_unsafe(curve_secp192r1.p, result, num_words_secp192r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp192r1.p, num_words_secp192r1); + } +} +#else +static void vli_mmod_fast_secp192r1(uint64_t *result, uint64_t *product) { + uint64_t tmp[num_words_secp192r1]; + int carry; + + uECC_vli_set(result, product, num_words_secp192r1); + + uECC_vli_set(tmp, &product[3], num_words_secp192r1); + carry = (int)uECC_vli_add(result, result, tmp, num_words_secp192r1); + + tmp[0] = 0; + tmp[1] = product[3]; + tmp[2] = product[4]; + carry += uECC_vli_add(result, result, tmp, num_words_secp192r1); + + tmp[0] = tmp[1] = product[5]; + tmp[2] = 0; + carry += uECC_vli_add(result, result, tmp, num_words_secp192r1); + + while (carry || uECC_vli_cmp_unsafe(curve_secp192r1.p, result, num_words_secp192r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp192r1.p, num_words_secp192r1); + } +} +#endif /* uECC_WORD_SIZE */ +#endif /* (uECC_OPTIMIZATION_LEVEL > 0) */ + +#endif /* uECC_SUPPORTS_secp192r1 */ + +#if uECC_SUPPORTS_secp224r1 + +#if uECC_SUPPORT_COMPRESSED_POINT +static void mod_sqrt_secp224r1(uECC_word_t *a, uECC_Curve curve); +#endif +#if (uECC_OPTIMIZATION_LEVEL > 0) +static void vli_mmod_fast_secp224r1(uECC_word_t *result, uECC_word_t *product); +#endif + +static const struct uECC_Curve_t curve_secp224r1 = { + num_words_secp224r1, + num_bytes_secp224r1, + 224, /* num_n_bits */ + { BYTES_TO_WORDS_8(01, 00, 00, 00, 00, 00, 00, 00), + BYTES_TO_WORDS_8(00, 00, 00, 00, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_4(FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(3D, 2A, 5C, 5C, 45, 29, DD, 13), + BYTES_TO_WORDS_8(3E, F0, B8, E0, A2, 16, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_4(FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(21, 1D, 5C, 11, D6, 80, 32, 34), + BYTES_TO_WORDS_8(22, 11, C2, 56, D3, C1, 03, 4A), + BYTES_TO_WORDS_8(B9, 90, 13, 32, 7F, BF, B4, 6B), + BYTES_TO_WORDS_4(BD, 0C, 0E, B7), + + BYTES_TO_WORDS_8(34, 7E, 00, 85, 99, 81, D5, 44), + BYTES_TO_WORDS_8(64, 47, 07, 5A, A0, 75, 43, CD), + BYTES_TO_WORDS_8(E6, DF, 22, 4C, FB, 23, F7, B5), + BYTES_TO_WORDS_4(88, 63, 37, BD) }, + { BYTES_TO_WORDS_8(B4, FF, 55, 23, 43, 39, 0B, 27), + BYTES_TO_WORDS_8(BA, D8, BF, D7, B7, B0, 44, 50), + BYTES_TO_WORDS_8(56, 32, 41, F5, AB, B3, 04, 0C), + BYTES_TO_WORDS_4(85, 0A, 05, B4) }, + &double_jacobian_default, +#if uECC_SUPPORT_COMPRESSED_POINT + &mod_sqrt_secp224r1, +#endif + &x_side_default, +#if (uECC_OPTIMIZATION_LEVEL > 0) + &vli_mmod_fast_secp224r1 +#endif +}; + +uECC_Curve uECC_secp224r1(void) { return &curve_secp224r1; } + + +#if uECC_SUPPORT_COMPRESSED_POINT +/* Routine 3.2.4 RS; from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +static void mod_sqrt_secp224r1_rs(uECC_word_t *d1, + uECC_word_t *e1, + uECC_word_t *f1, + const uECC_word_t *d0, + const uECC_word_t *e0, + const uECC_word_t *f0) { + uECC_word_t t[num_words_secp224r1]; + + uECC_vli_modSquare_fast(t, d0, &curve_secp224r1); /* t <-- d0 ^ 2 */ + uECC_vli_modMult_fast(e1, d0, e0, &curve_secp224r1); /* e1 <-- d0 * e0 */ + uECC_vli_modAdd(d1, t, f0, curve_secp224r1.p, num_words_secp224r1); /* d1 <-- t + f0 */ + uECC_vli_modAdd(e1, e1, e1, curve_secp224r1.p, num_words_secp224r1); /* e1 <-- e1 + e1 */ + uECC_vli_modMult_fast(f1, t, f0, &curve_secp224r1); /* f1 <-- t * f0 */ + uECC_vli_modAdd(f1, f1, f1, curve_secp224r1.p, num_words_secp224r1); /* f1 <-- f1 + f1 */ + uECC_vli_modAdd(f1, f1, f1, curve_secp224r1.p, num_words_secp224r1); /* f1 <-- f1 + f1 */ +} + +/* Routine 3.2.5 RSS; from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +static void mod_sqrt_secp224r1_rss(uECC_word_t *d1, + uECC_word_t *e1, + uECC_word_t *f1, + const uECC_word_t *d0, + const uECC_word_t *e0, + const uECC_word_t *f0, + const bitcount_t j) { + bitcount_t i; + + uECC_vli_set(d1, d0, num_words_secp224r1); /* d1 <-- d0 */ + uECC_vli_set(e1, e0, num_words_secp224r1); /* e1 <-- e0 */ + uECC_vli_set(f1, f0, num_words_secp224r1); /* f1 <-- f0 */ + for (i = 1; i <= j; i++) { + mod_sqrt_secp224r1_rs(d1, e1, f1, d1, e1, f1); /* RS (d1,e1,f1,d1,e1,f1) */ + } +} + +/* Routine 3.2.6 RM; from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +static void mod_sqrt_secp224r1_rm(uECC_word_t *d2, + uECC_word_t *e2, + uECC_word_t *f2, + const uECC_word_t *c, + const uECC_word_t *d0, + const uECC_word_t *e0, + const uECC_word_t *d1, + const uECC_word_t *e1) { + uECC_word_t t1[num_words_secp224r1]; + uECC_word_t t2[num_words_secp224r1]; + + uECC_vli_modMult_fast(t1, e0, e1, &curve_secp224r1); /* t1 <-- e0 * e1 */ + uECC_vli_modMult_fast(t1, t1, c, &curve_secp224r1); /* t1 <-- t1 * c */ + /* t1 <-- p - t1 */ + uECC_vli_modSub(t1, curve_secp224r1.p, t1, curve_secp224r1.p, num_words_secp224r1); + uECC_vli_modMult_fast(t2, d0, d1, &curve_secp224r1); /* t2 <-- d0 * d1 */ + uECC_vli_modAdd(t2, t2, t1, curve_secp224r1.p, num_words_secp224r1); /* t2 <-- t2 + t1 */ + uECC_vli_modMult_fast(t1, d0, e1, &curve_secp224r1); /* t1 <-- d0 * e1 */ + uECC_vli_modMult_fast(e2, d1, e0, &curve_secp224r1); /* e2 <-- d1 * e0 */ + uECC_vli_modAdd(e2, e2, t1, curve_secp224r1.p, num_words_secp224r1); /* e2 <-- e2 + t1 */ + uECC_vli_modSquare_fast(f2, e2, &curve_secp224r1); /* f2 <-- e2^2 */ + uECC_vli_modMult_fast(f2, f2, c, &curve_secp224r1); /* f2 <-- f2 * c */ + /* f2 <-- p - f2 */ + uECC_vli_modSub(f2, curve_secp224r1.p, f2, curve_secp224r1.p, num_words_secp224r1); + uECC_vli_set(d2, t2, num_words_secp224r1); /* d2 <-- t2 */ +} + +/* Routine 3.2.7 RP; from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +static void mod_sqrt_secp224r1_rp(uECC_word_t *d1, + uECC_word_t *e1, + uECC_word_t *f1, + const uECC_word_t *c, + const uECC_word_t *r) { + wordcount_t i; + wordcount_t pow2i = 1; + uECC_word_t d0[num_words_secp224r1]; + uECC_word_t e0[num_words_secp224r1] = {1}; /* e0 <-- 1 */ + uECC_word_t f0[num_words_secp224r1]; + + uECC_vli_set(d0, r, num_words_secp224r1); /* d0 <-- r */ + /* f0 <-- p - c */ + uECC_vli_modSub(f0, curve_secp224r1.p, c, curve_secp224r1.p, num_words_secp224r1); + for (i = 0; i <= 6; i++) { + mod_sqrt_secp224r1_rss(d1, e1, f1, d0, e0, f0, pow2i); /* RSS (d1,e1,f1,d0,e0,f0,2^i) */ + mod_sqrt_secp224r1_rm(d1, e1, f1, c, d1, e1, d0, e0); /* RM (d1,e1,f1,c,d1,e1,d0,e0) */ + uECC_vli_set(d0, d1, num_words_secp224r1); /* d0 <-- d1 */ + uECC_vli_set(e0, e1, num_words_secp224r1); /* e0 <-- e1 */ + uECC_vli_set(f0, f1, num_words_secp224r1); /* f0 <-- f1 */ + pow2i *= 2; + } +} + +/* Compute a = sqrt(a) (mod curve_p). */ +/* Routine 3.2.8 mp_mod_sqrt_224; from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +static void mod_sqrt_secp224r1(uECC_word_t *a, uECC_Curve curve) { + bitcount_t i; + uECC_word_t e1[num_words_secp224r1]; + uECC_word_t f1[num_words_secp224r1]; + uECC_word_t d0[num_words_secp224r1]; + uECC_word_t e0[num_words_secp224r1]; + uECC_word_t f0[num_words_secp224r1]; + uECC_word_t d1[num_words_secp224r1]; + + /* s = a; using constant instead of random value */ + mod_sqrt_secp224r1_rp(d0, e0, f0, a, a); /* RP (d0, e0, f0, c, s) */ + mod_sqrt_secp224r1_rs(d1, e1, f1, d0, e0, f0); /* RS (d1, e1, f1, d0, e0, f0) */ + for (i = 1; i <= 95; i++) { + uECC_vli_set(d0, d1, num_words_secp224r1); /* d0 <-- d1 */ + uECC_vli_set(e0, e1, num_words_secp224r1); /* e0 <-- e1 */ + uECC_vli_set(f0, f1, num_words_secp224r1); /* f0 <-- f1 */ + mod_sqrt_secp224r1_rs(d1, e1, f1, d0, e0, f0); /* RS (d1, e1, f1, d0, e0, f0) */ + if (uECC_vli_isZero(d1, num_words_secp224r1)) { /* if d1 == 0 */ + break; + } + } + uECC_vli_modInv(f1, e0, curve_secp224r1.p, num_words_secp224r1); /* f1 <-- 1 / e0 */ + uECC_vli_modMult_fast(a, d0, f1, &curve_secp224r1); /* a <-- d0 / e0 */ +} +#endif /* uECC_SUPPORT_COMPRESSED_POINT */ + +#if (uECC_OPTIMIZATION_LEVEL > 0) +/* Computes result = product % curve_p + from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +#if uECC_WORD_SIZE == 1 +static void vli_mmod_fast_secp224r1(uint8_t *result, uint8_t *product) { + uint8_t tmp[num_words_secp224r1]; + int8_t carry; + + /* t */ + uECC_vli_set(result, product, num_words_secp224r1); + + /* s1 */ + tmp[0] = tmp[1] = tmp[2] = tmp[3] = 0; + tmp[4] = tmp[5] = tmp[6] = tmp[7] = 0; + tmp[8] = tmp[9] = tmp[10] = tmp[11] = 0; + tmp[12] = product[28]; tmp[13] = product[29]; tmp[14] = product[30]; tmp[15] = product[31]; + tmp[16] = product[32]; tmp[17] = product[33]; tmp[18] = product[34]; tmp[19] = product[35]; + tmp[20] = product[36]; tmp[21] = product[37]; tmp[22] = product[38]; tmp[23] = product[39]; + tmp[24] = product[40]; tmp[25] = product[41]; tmp[26] = product[42]; tmp[27] = product[43]; + carry = uECC_vli_add(result, result, tmp, num_words_secp224r1); + + /* s2 */ + tmp[12] = product[44]; tmp[13] = product[45]; tmp[14] = product[46]; tmp[15] = product[47]; + tmp[16] = product[48]; tmp[17] = product[49]; tmp[18] = product[50]; tmp[19] = product[51]; + tmp[20] = product[52]; tmp[21] = product[53]; tmp[22] = product[54]; tmp[23] = product[55]; + tmp[24] = tmp[25] = tmp[26] = tmp[27] = 0; + carry += uECC_vli_add(result, result, tmp, num_words_secp224r1); + + /* d1 */ + tmp[0] = product[28]; tmp[1] = product[29]; tmp[2] = product[30]; tmp[3] = product[31]; + tmp[4] = product[32]; tmp[5] = product[33]; tmp[6] = product[34]; tmp[7] = product[35]; + tmp[8] = product[36]; tmp[9] = product[37]; tmp[10] = product[38]; tmp[11] = product[39]; + tmp[12] = product[40]; tmp[13] = product[41]; tmp[14] = product[42]; tmp[15] = product[43]; + tmp[16] = product[44]; tmp[17] = product[45]; tmp[18] = product[46]; tmp[19] = product[47]; + tmp[20] = product[48]; tmp[21] = product[49]; tmp[22] = product[50]; tmp[23] = product[51]; + tmp[24] = product[52]; tmp[25] = product[53]; tmp[26] = product[54]; tmp[27] = product[55]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp224r1); + + /* d2 */ + tmp[0] = product[44]; tmp[1] = product[45]; tmp[2] = product[46]; tmp[3] = product[47]; + tmp[4] = product[48]; tmp[5] = product[49]; tmp[6] = product[50]; tmp[7] = product[51]; + tmp[8] = product[52]; tmp[9] = product[53]; tmp[10] = product[54]; tmp[11] = product[55]; + tmp[12] = tmp[13] = tmp[14] = tmp[15] = 0; + tmp[16] = tmp[17] = tmp[18] = tmp[19] = 0; + tmp[20] = tmp[21] = tmp[22] = tmp[23] = 0; + tmp[24] = tmp[25] = tmp[26] = tmp[27] = 0; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp224r1); + + if (carry < 0) { + do { + carry += uECC_vli_add(result, result, curve_secp224r1.p, num_words_secp224r1); + } while (carry < 0); + } else { + while (carry || uECC_vli_cmp_unsafe(curve_secp224r1.p, result, num_words_secp224r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp224r1.p, num_words_secp224r1); + } + } +} +#elif uECC_WORD_SIZE == 4 +static void vli_mmod_fast_secp224r1(uint32_t *result, uint32_t *product) +{ + uint32_t tmp[num_words_secp224r1]; + int carry; + + /* t */ + uECC_vli_set(result, product, num_words_secp224r1); + + /* s1 */ + tmp[0] = tmp[1] = tmp[2] = 0; + tmp[3] = product[7]; + tmp[4] = product[8]; + tmp[5] = product[9]; + tmp[6] = product[10]; + carry = uECC_vli_add(result, result, tmp, num_words_secp224r1); + + /* s2 */ + tmp[3] = product[11]; + tmp[4] = product[12]; + tmp[5] = product[13]; + tmp[6] = 0; + carry += uECC_vli_add(result, result, tmp, num_words_secp224r1); + + /* d1 */ + tmp[0] = product[7]; + tmp[1] = product[8]; + tmp[2] = product[9]; + tmp[3] = product[10]; + tmp[4] = product[11]; + tmp[5] = product[12]; + tmp[6] = product[13]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp224r1); + + /* d2 */ + tmp[0] = product[11]; + tmp[1] = product[12]; + tmp[2] = product[13]; + tmp[3] = tmp[4] = tmp[5] = tmp[6] = 0; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp224r1); + + if (carry < 0) { + do { + carry += uECC_vli_add(result, result, curve_secp224r1.p, num_words_secp224r1); + } while (carry < 0); + } else { + while (carry || uECC_vli_cmp_unsafe(curve_secp224r1.p, result, num_words_secp224r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp224r1.p, num_words_secp224r1); + } + } +} +#else +static void vli_mmod_fast_secp224r1(uint64_t *result, uint64_t *product) +{ + uint64_t tmp[num_words_secp224r1]; + int carry = 0; + + /* t */ + uECC_vli_set(result, product, num_words_secp224r1); + result[num_words_secp224r1 - 1] &= 0xffffffff; + + /* s1 */ + tmp[0] = 0; + tmp[1] = product[3] & 0xffffffff00000000ull; + tmp[2] = product[4]; + tmp[3] = product[5] & 0xffffffff; + uECC_vli_add(result, result, tmp, num_words_secp224r1); + + /* s2 */ + tmp[1] = product[5] & 0xffffffff00000000ull; + tmp[2] = product[6]; + tmp[3] = 0; + uECC_vli_add(result, result, tmp, num_words_secp224r1); + + /* d1 */ + tmp[0] = (product[3] >> 32) | (product[4] << 32); + tmp[1] = (product[4] >> 32) | (product[5] << 32); + tmp[2] = (product[5] >> 32) | (product[6] << 32); + tmp[3] = product[6] >> 32; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp224r1); + + /* d2 */ + tmp[0] = (product[5] >> 32) | (product[6] << 32); + tmp[1] = product[6] >> 32; + tmp[2] = tmp[3] = 0; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp224r1); + + if (carry < 0) { + do { + carry += uECC_vli_add(result, result, curve_secp224r1.p, num_words_secp224r1); + } while (carry < 0); + } else { + while (uECC_vli_cmp_unsafe(curve_secp224r1.p, result, num_words_secp224r1) != 1) { + uECC_vli_sub(result, result, curve_secp224r1.p, num_words_secp224r1); + } + } +} +#endif /* uECC_WORD_SIZE */ +#endif /* (uECC_OPTIMIZATION_LEVEL > 0) */ + +#endif /* uECC_SUPPORTS_secp224r1 */ + +#if uECC_SUPPORTS_secp256r1 + +#if (uECC_OPTIMIZATION_LEVEL > 0) +static void vli_mmod_fast_secp256r1(uECC_word_t *result, uECC_word_t *product); +#endif + +static const struct uECC_Curve_t curve_secp256r1 = { + num_words_secp256r1, + num_bytes_secp256r1, + 256, /* num_n_bits */ + { BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, 00, 00, 00, 00), + BYTES_TO_WORDS_8(00, 00, 00, 00, 00, 00, 00, 00), + BYTES_TO_WORDS_8(01, 00, 00, 00, FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(51, 25, 63, FC, C2, CA, B9, F3), + BYTES_TO_WORDS_8(84, 9E, 17, A7, AD, FA, E6, BC), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(00, 00, 00, 00, FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(96, C2, 98, D8, 45, 39, A1, F4), + BYTES_TO_WORDS_8(A0, 33, EB, 2D, 81, 7D, 03, 77), + BYTES_TO_WORDS_8(F2, 40, A4, 63, E5, E6, BC, F8), + BYTES_TO_WORDS_8(47, 42, 2C, E1, F2, D1, 17, 6B), + + BYTES_TO_WORDS_8(F5, 51, BF, 37, 68, 40, B6, CB), + BYTES_TO_WORDS_8(CE, 5E, 31, 6B, 57, 33, CE, 2B), + BYTES_TO_WORDS_8(16, 9E, 0F, 7C, 4A, EB, E7, 8E), + BYTES_TO_WORDS_8(9B, 7F, 1A, FE, E2, 42, E3, 4F) }, + { BYTES_TO_WORDS_8(4B, 60, D2, 27, 3E, 3C, CE, 3B), + BYTES_TO_WORDS_8(F6, B0, 53, CC, B0, 06, 1D, 65), + BYTES_TO_WORDS_8(BC, 86, 98, 76, 55, BD, EB, B3), + BYTES_TO_WORDS_8(E7, 93, 3A, AA, D8, 35, C6, 5A) }, + &double_jacobian_default, +#if uECC_SUPPORT_COMPRESSED_POINT + &mod_sqrt_default, +#endif + &x_side_default, +#if (uECC_OPTIMIZATION_LEVEL > 0) + &vli_mmod_fast_secp256r1 +#endif +}; + +uECC_Curve uECC_secp256r1(void) { return &curve_secp256r1; } + + +#if (uECC_OPTIMIZATION_LEVEL > 0 && !asm_mmod_fast_secp256r1) +/* Computes result = product % curve_p + from http://www.nsa.gov/ia/_files/nist-routines.pdf */ +#if uECC_WORD_SIZE == 1 +static void vli_mmod_fast_secp256r1(uint8_t *result, uint8_t *product) { + uint8_t tmp[num_words_secp256r1]; + int8_t carry; + + /* t */ + uECC_vli_set(result, product, num_words_secp256r1); + + /* s1 */ + tmp[0] = tmp[1] = tmp[2] = tmp[3] = 0; + tmp[4] = tmp[5] = tmp[6] = tmp[7] = 0; + tmp[8] = tmp[9] = tmp[10] = tmp[11] = 0; + tmp[12] = product[44]; tmp[13] = product[45]; tmp[14] = product[46]; tmp[15] = product[47]; + tmp[16] = product[48]; tmp[17] = product[49]; tmp[18] = product[50]; tmp[19] = product[51]; + tmp[20] = product[52]; tmp[21] = product[53]; tmp[22] = product[54]; tmp[23] = product[55]; + tmp[24] = product[56]; tmp[25] = product[57]; tmp[26] = product[58]; tmp[27] = product[59]; + tmp[28] = product[60]; tmp[29] = product[61]; tmp[30] = product[62]; tmp[31] = product[63]; + carry = uECC_vli_add(tmp, tmp, tmp, num_words_secp256r1); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s2 */ + tmp[12] = product[48]; tmp[13] = product[49]; tmp[14] = product[50]; tmp[15] = product[51]; + tmp[16] = product[52]; tmp[17] = product[53]; tmp[18] = product[54]; tmp[19] = product[55]; + tmp[20] = product[56]; tmp[21] = product[57]; tmp[22] = product[58]; tmp[23] = product[59]; + tmp[24] = product[60]; tmp[25] = product[61]; tmp[26] = product[62]; tmp[27] = product[63]; + tmp[28] = tmp[29] = tmp[30] = tmp[31] = 0; + carry += uECC_vli_add(tmp, tmp, tmp, num_words_secp256r1); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s3 */ + tmp[0] = product[32]; tmp[1] = product[33]; tmp[2] = product[34]; tmp[3] = product[35]; + tmp[4] = product[36]; tmp[5] = product[37]; tmp[6] = product[38]; tmp[7] = product[39]; + tmp[8] = product[40]; tmp[9] = product[41]; tmp[10] = product[42]; tmp[11] = product[43]; + tmp[12] = tmp[13] = tmp[14] = tmp[15] = 0; + tmp[16] = tmp[17] = tmp[18] = tmp[19] = 0; + tmp[20] = tmp[21] = tmp[22] = tmp[23] = 0; + tmp[24] = product[56]; tmp[25] = product[57]; tmp[26] = product[58]; tmp[27] = product[59]; + tmp[28] = product[60]; tmp[29] = product[61]; tmp[30] = product[62]; tmp[31] = product[63]; + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s4 */ + tmp[0] = product[36]; tmp[1] = product[37]; tmp[2] = product[38]; tmp[3] = product[39]; + tmp[4] = product[40]; tmp[5] = product[41]; tmp[6] = product[42]; tmp[7] = product[43]; + tmp[8] = product[44]; tmp[9] = product[45]; tmp[10] = product[46]; tmp[11] = product[47]; + tmp[12] = product[52]; tmp[13] = product[53]; tmp[14] = product[54]; tmp[15] = product[55]; + tmp[16] = product[56]; tmp[17] = product[57]; tmp[18] = product[58]; tmp[19] = product[59]; + tmp[20] = product[60]; tmp[21] = product[61]; tmp[22] = product[62]; tmp[23] = product[63]; + tmp[24] = product[52]; tmp[25] = product[53]; tmp[26] = product[54]; tmp[27] = product[55]; + tmp[28] = product[32]; tmp[29] = product[33]; tmp[30] = product[34]; tmp[31] = product[35]; + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* d1 */ + tmp[0] = product[44]; tmp[1] = product[45]; tmp[2] = product[46]; tmp[3] = product[47]; + tmp[4] = product[48]; tmp[5] = product[49]; tmp[6] = product[50]; tmp[7] = product[51]; + tmp[8] = product[52]; tmp[9] = product[53]; tmp[10] = product[54]; tmp[11] = product[55]; + tmp[12] = tmp[13] = tmp[14] = tmp[15] = 0; + tmp[16] = tmp[17] = tmp[18] = tmp[19] = 0; + tmp[20] = tmp[21] = tmp[22] = tmp[23] = 0; + tmp[24] = product[32]; tmp[25] = product[33]; tmp[26] = product[34]; tmp[27] = product[35]; + tmp[28] = product[40]; tmp[29] = product[41]; tmp[30] = product[42]; tmp[31] = product[43]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d2 */ + tmp[0] = product[48]; tmp[1] = product[49]; tmp[2] = product[50]; tmp[3] = product[51]; + tmp[4] = product[52]; tmp[5] = product[53]; tmp[6] = product[54]; tmp[7] = product[55]; + tmp[8] = product[56]; tmp[9] = product[57]; tmp[10] = product[58]; tmp[11] = product[59]; + tmp[12] = product[60]; tmp[13] = product[61]; tmp[14] = product[62]; tmp[15] = product[63]; + tmp[16] = tmp[17] = tmp[18] = tmp[19] = 0; + tmp[20] = tmp[21] = tmp[22] = tmp[23] = 0; + tmp[24] = product[36]; tmp[25] = product[37]; tmp[26] = product[38]; tmp[27] = product[39]; + tmp[28] = product[44]; tmp[29] = product[45]; tmp[30] = product[46]; tmp[31] = product[47]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d3 */ + tmp[0] = product[52]; tmp[1] = product[53]; tmp[2] = product[54]; tmp[3] = product[55]; + tmp[4] = product[56]; tmp[5] = product[57]; tmp[6] = product[58]; tmp[7] = product[59]; + tmp[8] = product[60]; tmp[9] = product[61]; tmp[10] = product[62]; tmp[11] = product[63]; + tmp[12] = product[32]; tmp[13] = product[33]; tmp[14] = product[34]; tmp[15] = product[35]; + tmp[16] = product[36]; tmp[17] = product[37]; tmp[18] = product[38]; tmp[19] = product[39]; + tmp[20] = product[40]; tmp[21] = product[41]; tmp[22] = product[42]; tmp[23] = product[43]; + tmp[24] = tmp[25] = tmp[26] = tmp[27] = 0; + tmp[28] = product[48]; tmp[29] = product[49]; tmp[30] = product[50]; tmp[31] = product[51]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d4 */ + tmp[0] = product[56]; tmp[1] = product[57]; tmp[2] = product[58]; tmp[3] = product[59]; + tmp[4] = product[60]; tmp[5] = product[61]; tmp[6] = product[62]; tmp[7] = product[63]; + tmp[8] = tmp[9] = tmp[10] = tmp[11] = 0; + tmp[12] = product[36]; tmp[13] = product[37]; tmp[14] = product[38]; tmp[15] = product[39]; + tmp[16] = product[40]; tmp[17] = product[41]; tmp[18] = product[42]; tmp[19] = product[43]; + tmp[20] = product[44]; tmp[21] = product[45]; tmp[22] = product[46]; tmp[23] = product[47]; + tmp[24] = tmp[25] = tmp[26] = tmp[27] = 0; + tmp[28] = product[52]; tmp[29] = product[53]; tmp[30] = product[54]; tmp[31] = product[55]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + if (carry < 0) { + do { + carry += uECC_vli_add(result, result, curve_secp256r1.p, num_words_secp256r1); + } while (carry < 0); + } else { + while (carry || uECC_vli_cmp_unsafe(curve_secp256r1.p, result, num_words_secp256r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp256r1.p, num_words_secp256r1); + } + } +} +#elif uECC_WORD_SIZE == 4 +static void vli_mmod_fast_secp256r1(uint32_t *result, uint32_t *product) { + uint32_t tmp[num_words_secp256r1]; + int carry; + + /* t */ + uECC_vli_set(result, product, num_words_secp256r1); + + /* s1 */ + tmp[0] = tmp[1] = tmp[2] = 0; + tmp[3] = product[11]; + tmp[4] = product[12]; + tmp[5] = product[13]; + tmp[6] = product[14]; + tmp[7] = product[15]; + carry = uECC_vli_add(tmp, tmp, tmp, num_words_secp256r1); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s2 */ + tmp[3] = product[12]; + tmp[4] = product[13]; + tmp[5] = product[14]; + tmp[6] = product[15]; + tmp[7] = 0; + carry += uECC_vli_add(tmp, tmp, tmp, num_words_secp256r1); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s3 */ + tmp[0] = product[8]; + tmp[1] = product[9]; + tmp[2] = product[10]; + tmp[3] = tmp[4] = tmp[5] = 0; + tmp[6] = product[14]; + tmp[7] = product[15]; + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s4 */ + tmp[0] = product[9]; + tmp[1] = product[10]; + tmp[2] = product[11]; + tmp[3] = product[13]; + tmp[4] = product[14]; + tmp[5] = product[15]; + tmp[6] = product[13]; + tmp[7] = product[8]; + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* d1 */ + tmp[0] = product[11]; + tmp[1] = product[12]; + tmp[2] = product[13]; + tmp[3] = tmp[4] = tmp[5] = 0; + tmp[6] = product[8]; + tmp[7] = product[10]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d2 */ + tmp[0] = product[12]; + tmp[1] = product[13]; + tmp[2] = product[14]; + tmp[3] = product[15]; + tmp[4] = tmp[5] = 0; + tmp[6] = product[9]; + tmp[7] = product[11]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d3 */ + tmp[0] = product[13]; + tmp[1] = product[14]; + tmp[2] = product[15]; + tmp[3] = product[8]; + tmp[4] = product[9]; + tmp[5] = product[10]; + tmp[6] = 0; + tmp[7] = product[12]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d4 */ + tmp[0] = product[14]; + tmp[1] = product[15]; + tmp[2] = 0; + tmp[3] = product[9]; + tmp[4] = product[10]; + tmp[5] = product[11]; + tmp[6] = 0; + tmp[7] = product[13]; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + if (carry < 0) { + do { + carry += uECC_vli_add(result, result, curve_secp256r1.p, num_words_secp256r1); + } while (carry < 0); + } else { + while (carry || uECC_vli_cmp_unsafe(curve_secp256r1.p, result, num_words_secp256r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp256r1.p, num_words_secp256r1); + } + } +} +#else +static void vli_mmod_fast_secp256r1(uint64_t *result, uint64_t *product) { + uint64_t tmp[num_words_secp256r1]; + int carry; + + /* t */ + uECC_vli_set(result, product, num_words_secp256r1); + + /* s1 */ + tmp[0] = 0; + tmp[1] = product[5] & 0xffffffff00000000ull; + tmp[2] = product[6]; + tmp[3] = product[7]; + carry = (int)uECC_vli_add(tmp, tmp, tmp, num_words_secp256r1); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s2 */ + tmp[1] = product[6] << 32; + tmp[2] = (product[6] >> 32) | (product[7] << 32); + tmp[3] = product[7] >> 32; + carry += uECC_vli_add(tmp, tmp, tmp, num_words_secp256r1); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s3 */ + tmp[0] = product[4]; + tmp[1] = product[5] & 0xffffffff; + tmp[2] = 0; + tmp[3] = product[7]; + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* s4 */ + tmp[0] = (product[4] >> 32) | (product[5] << 32); + tmp[1] = (product[5] >> 32) | (product[6] & 0xffffffff00000000ull); + tmp[2] = product[7]; + tmp[3] = (product[6] >> 32) | (product[4] << 32); + carry += uECC_vli_add(result, result, tmp, num_words_secp256r1); + + /* d1 */ + tmp[0] = (product[5] >> 32) | (product[6] << 32); + tmp[1] = (product[6] >> 32); + tmp[2] = 0; + tmp[3] = (product[4] & 0xffffffff) | (product[5] << 32); + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d2 */ + tmp[0] = product[6]; + tmp[1] = product[7]; + tmp[2] = 0; + tmp[3] = (product[4] >> 32) | (product[5] & 0xffffffff00000000ull); + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d3 */ + tmp[0] = (product[6] >> 32) | (product[7] << 32); + tmp[1] = (product[7] >> 32) | (product[4] << 32); + tmp[2] = (product[4] >> 32) | (product[5] << 32); + tmp[3] = (product[6] << 32); + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + /* d4 */ + tmp[0] = product[7]; + tmp[1] = product[4] & 0xffffffff00000000ull; + tmp[2] = product[5]; + tmp[3] = product[6] & 0xffffffff00000000ull; + carry -= uECC_vli_sub(result, result, tmp, num_words_secp256r1); + + if (carry < 0) { + do { + carry += uECC_vli_add(result, result, curve_secp256r1.p, num_words_secp256r1); + } while (carry < 0); + } else { + while (carry || uECC_vli_cmp_unsafe(curve_secp256r1.p, result, num_words_secp256r1) != 1) { + carry -= uECC_vli_sub(result, result, curve_secp256r1.p, num_words_secp256r1); + } + } +} +#endif /* uECC_WORD_SIZE */ +#endif /* (uECC_OPTIMIZATION_LEVEL > 0 && !asm_mmod_fast_secp256r1) */ + +#endif /* uECC_SUPPORTS_secp256r1 */ + +#if uECC_SUPPORTS_secp256k1 + +static void double_jacobian_secp256k1(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * Z1, + uECC_Curve curve); +static void x_side_secp256k1(uECC_word_t *result, const uECC_word_t *x, uECC_Curve curve); +#if (uECC_OPTIMIZATION_LEVEL > 0) +static void vli_mmod_fast_secp256k1(uECC_word_t *result, uECC_word_t *product); +#endif + +static const struct uECC_Curve_t curve_secp256k1 = { + num_words_secp256k1, + num_bytes_secp256k1, + 256, /* num_n_bits */ + { BYTES_TO_WORDS_8(2F, FC, FF, FF, FE, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(41, 41, 36, D0, 8C, 5E, D2, BF), + BYTES_TO_WORDS_8(3B, A0, 48, AF, E6, DC, AE, BA), + BYTES_TO_WORDS_8(FE, FF, FF, FF, FF, FF, FF, FF), + BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF) }, + { BYTES_TO_WORDS_8(98, 17, F8, 16, 5B, 81, F2, 59), + BYTES_TO_WORDS_8(D9, 28, CE, 2D, DB, FC, 9B, 02), + BYTES_TO_WORDS_8(07, 0B, 87, CE, 95, 62, A0, 55), + BYTES_TO_WORDS_8(AC, BB, DC, F9, 7E, 66, BE, 79), + + BYTES_TO_WORDS_8(B8, D4, 10, FB, 8F, D0, 47, 9C), + BYTES_TO_WORDS_8(19, 54, 85, A6, 48, B4, 17, FD), + BYTES_TO_WORDS_8(A8, 08, 11, 0E, FC, FB, A4, 5D), + BYTES_TO_WORDS_8(65, C4, A3, 26, 77, DA, 3A, 48) }, + { BYTES_TO_WORDS_8(07, 00, 00, 00, 00, 00, 00, 00), + BYTES_TO_WORDS_8(00, 00, 00, 00, 00, 00, 00, 00), + BYTES_TO_WORDS_8(00, 00, 00, 00, 00, 00, 00, 00), + BYTES_TO_WORDS_8(00, 00, 00, 00, 00, 00, 00, 00) }, + &double_jacobian_secp256k1, +#if uECC_SUPPORT_COMPRESSED_POINT + &mod_sqrt_default, +#endif + &x_side_secp256k1, +#if (uECC_OPTIMIZATION_LEVEL > 0) + &vli_mmod_fast_secp256k1 +#endif +}; + +uECC_Curve uECC_secp256k1(void) { return &curve_secp256k1; } + + +/* Double in place */ +static void double_jacobian_secp256k1(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * Z1, + uECC_Curve curve) { + /* t1 = X, t2 = Y, t3 = Z */ + uECC_word_t t4[num_words_secp256k1]; + uECC_word_t t5[num_words_secp256k1]; + + if (uECC_vli_isZero(Z1, num_words_secp256k1)) { + return; + } + + uECC_vli_modSquare_fast(t5, Y1, curve); /* t5 = y1^2 */ + uECC_vli_modMult_fast(t4, X1, t5, curve); /* t4 = x1*y1^2 = A */ + uECC_vli_modSquare_fast(X1, X1, curve); /* t1 = x1^2 */ + uECC_vli_modSquare_fast(t5, t5, curve); /* t5 = y1^4 */ + uECC_vli_modMult_fast(Z1, Y1, Z1, curve); /* t3 = y1*z1 = z3 */ + + uECC_vli_modAdd(Y1, X1, X1, curve->p, num_words_secp256k1); /* t2 = 2*x1^2 */ + uECC_vli_modAdd(Y1, Y1, X1, curve->p, num_words_secp256k1); /* t2 = 3*x1^2 */ + if (uECC_vli_testBit(Y1, 0)) { + uECC_word_t carry = uECC_vli_add(Y1, Y1, curve->p, num_words_secp256k1); + uECC_vli_rshift1(Y1, num_words_secp256k1); + Y1[num_words_secp256k1 - 1] |= carry << (uECC_WORD_BITS - 1); + } else { + uECC_vli_rshift1(Y1, num_words_secp256k1); + } + /* t2 = 3/2*(x1^2) = B */ + + uECC_vli_modSquare_fast(X1, Y1, curve); /* t1 = B^2 */ + uECC_vli_modSub(X1, X1, t4, curve->p, num_words_secp256k1); /* t1 = B^2 - A */ + uECC_vli_modSub(X1, X1, t4, curve->p, num_words_secp256k1); /* t1 = B^2 - 2A = x3 */ + + uECC_vli_modSub(t4, t4, X1, curve->p, num_words_secp256k1); /* t4 = A - x3 */ + uECC_vli_modMult_fast(Y1, Y1, t4, curve); /* t2 = B * (A - x3) */ + uECC_vli_modSub(Y1, Y1, t5, curve->p, num_words_secp256k1); /* t2 = B * (A - x3) - y1^4 = y3 */ +} + +/* Computes result = x^3 + b. result must not overlap x. */ +static void x_side_secp256k1(uECC_word_t *result, const uECC_word_t *x, uECC_Curve curve) { + uECC_vli_modSquare_fast(result, x, curve); /* r = x^2 */ + uECC_vli_modMult_fast(result, result, x, curve); /* r = x^3 */ + uECC_vli_modAdd(result, result, curve->b, curve->p, num_words_secp256k1); /* r = x^3 + b */ +} + +#if (uECC_OPTIMIZATION_LEVEL > 0 && !asm_mmod_fast_secp256k1) +static void omega_mult_secp256k1(uECC_word_t *result, const uECC_word_t *right); +static void vli_mmod_fast_secp256k1(uECC_word_t *result, uECC_word_t *product) { + uECC_word_t tmp[2 * num_words_secp256k1]; + uECC_word_t carry; + + uECC_vli_clear(tmp, num_words_secp256k1); + uECC_vli_clear(tmp + num_words_secp256k1, num_words_secp256k1); + + omega_mult_secp256k1(tmp, product + num_words_secp256k1); /* (Rq, q) = q * c */ + + carry = uECC_vli_add(result, product, tmp, num_words_secp256k1); /* (C, r) = r + q */ + uECC_vli_clear(product, num_words_secp256k1); + omega_mult_secp256k1(product, tmp + num_words_secp256k1); /* Rq*c */ + carry += uECC_vli_add(result, result, product, num_words_secp256k1); /* (C1, r) = r + Rq*c */ + + while (carry > 0) { + --carry; + uECC_vli_sub(result, result, curve_secp256k1.p, num_words_secp256k1); + } + if (uECC_vli_cmp_unsafe(result, curve_secp256k1.p, num_words_secp256k1) > 0) { + uECC_vli_sub(result, result, curve_secp256k1.p, num_words_secp256k1); + } +} + +#if uECC_WORD_SIZE == 1 +static void omega_mult_secp256k1(uint8_t * result, const uint8_t * right) { + /* Multiply by (2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1). */ + uECC_word_t r0 = 0; + uECC_word_t r1 = 0; + uECC_word_t r2 = 0; + wordcount_t k; + + /* Multiply by (2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1). */ + muladd(0xD1, right[0], &r0, &r1, &r2); + result[0] = r0; + r0 = r1; + r1 = r2; + /* r2 is still 0 */ + + for (k = 1; k < num_words_secp256k1; ++k) { + muladd(0x03, right[k - 1], &r0, &r1, &r2); + muladd(0xD1, right[k], &r0, &r1, &r2); + result[k] = r0; + r0 = r1; + r1 = r2; + r2 = 0; + } + muladd(0x03, right[num_words_secp256k1 - 1], &r0, &r1, &r2); + result[num_words_secp256k1] = r0; + result[num_words_secp256k1 + 1] = r1; + /* add the 2^32 multiple */ + result[4 + num_words_secp256k1] = + uECC_vli_add(result + 4, result + 4, right, num_words_secp256k1); +} +#elif uECC_WORD_SIZE == 4 +static void omega_mult_secp256k1(uint32_t * result, const uint32_t * right) { + /* Multiply by (2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1). */ + uint32_t carry = 0; + wordcount_t k; + + for (k = 0; k < num_words_secp256k1; ++k) { + uint64_t p = (uint64_t)0x3D1 * right[k] + carry; + result[k] = (uint32_t) p; + carry = p >> 32; + } + result[num_words_secp256k1] = carry; + /* add the 2^32 multiple */ + result[1 + num_words_secp256k1] = + uECC_vli_add(result + 1, result + 1, right, num_words_secp256k1); +} +#else +static void omega_mult_secp256k1(uint64_t * result, const uint64_t * right) { + uECC_word_t r0 = 0; + uECC_word_t r1 = 0; + uECC_word_t r2 = 0; + wordcount_t k; + + /* Multiply by (2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1). */ + for (k = 0; k < num_words_secp256k1; ++k) { + muladd(0x1000003D1ull, right[k], &r0, &r1, &r2); + result[k] = r0; + r0 = r1; + r1 = r2; + r2 = 0; + } + result[num_words_secp256k1] = r0; +} +#endif /* uECC_WORD_SIZE */ +#endif /* (uECC_OPTIMIZATION_LEVEL > 0 && && !asm_mmod_fast_secp256k1) */ + +#endif /* uECC_SUPPORTS_secp256k1 */ + +#endif /* _UECC_CURVE_SPECIFIC_H_ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/main.c new file mode 100644 index 0000000000..a484beed50 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/main.c @@ -0,0 +1,143 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +int test_ecdsa(void) +{ + int i, c; + uint8_t private[32] = {0}; + uint8_t public[64] = {0}; + uint8_t hash[32] = {0}; + uint8_t sig[64] = {0}; + + const struct uECC_Curve_t * curves[5]; + int num_curves = 0; +#if uECC_SUPPORTS_secp160r1 + curves[num_curves++] = uECC_secp160r1(); +#endif +#if uECC_SUPPORTS_secp192r1 + curves[num_curves++] = uECC_secp192r1(); +#endif +#if uECC_SUPPORTS_secp224r1 + curves[num_curves++] = uECC_secp224r1(); +#endif +#if uECC_SUPPORTS_secp256r1 + curves[num_curves++] = uECC_secp256r1(); +#endif +#if uECC_SUPPORTS_secp256k1 + curves[num_curves++] = uECC_secp256k1(); +#endif + + printf("Testing 256 signatures\r\n"); + for (c = 0; c < num_curves; ++c) + { + for (i = 0; i < 1; ++i) { + + printf("uECC_make_key()\r\n"); + + if (!uECC_make_key(public, private, curves[c])) + { + printf("uECC_make_key() failed\r\n"); + return 1; + } + memcpy(hash, public, sizeof(hash)); + + printf("uECC_sign()\r\n"); + + if (!uECC_sign(private, hash, sizeof(hash), sig, curves[c])) + { + printf("uECC_sign() failed\r\n"); + return 1; + } + + printf("uECC_verify()\r\n"); + + if (!uECC_verify(public, hash, sizeof(hash), sig, curves[c])) + { + printf("uECC_verify() failed\r\n"); + return 1; + } + } + printf("done\r\n"); +} + + return 0; +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /* Clock initialization */ + Clock_Init(); + /* Print initialization */ + Stdio_Init(); + + test_ecdsa(); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/platform-specific.inc b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/platform-specific.inc new file mode 100644 index 0000000000..448515a782 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/platform-specific.inc @@ -0,0 +1,86 @@ +/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_PLATFORM_SPECIFIC_H_ +#define _UECC_PLATFORM_SPECIFIC_H_ + +#include "types.h" + +#if (defined(_WIN32) || defined(_WIN64)) +/* Windows */ + +#define WIN32_LEAN_AND_MEAN +#include +#include + +static int default_RNG(uint8_t *dest, unsigned size) { + HCRYPTPROV prov; + if (!CryptAcquireContext(&prov, NULL, NULL, PROV_RSA_FULL, CRYPT_VERIFYCONTEXT)) { + return 0; + } + + CryptGenRandom(prov, size, (BYTE *)dest); + CryptReleaseContext(prov, 0); + return 1; +} +#define default_RNG_defined 1 + +#elif defined(unix) || defined(__linux__) || defined(__unix__) || defined(__unix) || \ + (defined(__APPLE__) && defined(__MACH__)) || defined(uECC_POSIX) + +/* Some POSIX-like system with /dev/urandom or /dev/random. */ +#include +#include +#include + +#ifndef O_CLOEXEC + #define O_CLOEXEC 0 +#endif + +static int default_RNG(uint8_t *dest, unsigned size) { + int fd = open("/dev/urandom", O_RDONLY | O_CLOEXEC); + if (fd == -1) { + fd = open("/dev/random", O_RDONLY | O_CLOEXEC); + if (fd == -1) { + return 0; + } + } + + char *ptr = (char *)dest; + size_t left = size; + while (left > 0) { + ssize_t bytes_read = read(fd, ptr, left); + if (bytes_read <= 0) { // read failed + close(fd); + return 0; + } + left -= bytes_read; + ptr += bytes_read; + } + + close(fd); + return 1; +} +#define default_RNG_defined 1 + +#else + +// ycliao +static int default_RNG(uint8_t *dest, unsigned size) { + + unsigned i = 0; + char *ptr = (char *)dest; + unsigned left = size; + while (left > 0) { + *ptr = i++; + left -= 1; + ptr += 1; + } + + return 1; +} + +#define default_RNG_defined 1 + +#endif /* platform */ + +#endif /* _UECC_PLATFORM_SPECIFIC_H_ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/target_isr.c new file mode 100644 index 0000000000..e72ff03e05 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/types.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/types.h new file mode 100644 index 0000000000..9ee81438fa --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/types.h @@ -0,0 +1,108 @@ +/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_TYPES_H_ +#define _UECC_TYPES_H_ + +#ifndef uECC_PLATFORM + #if __AVR__ + #define uECC_PLATFORM uECC_avr + #elif defined(__thumb2__) || defined(_M_ARMT) /* I think MSVC only supports Thumb-2 targets */ + #define uECC_PLATFORM uECC_arm_thumb2 + #elif defined(__thumb__) + #define uECC_PLATFORM uECC_arm_thumb + #elif defined(__arm__) || defined(_M_ARM) + #define uECC_PLATFORM uECC_arm + #elif defined(__aarch64__) + #define uECC_PLATFORM uECC_arm64 + #elif defined(__i386__) || defined(_M_IX86) || defined(_X86_) || defined(__I86__) + #define uECC_PLATFORM uECC_x86 + #elif defined(__amd64__) || defined(_M_X64) + #define uECC_PLATFORM uECC_x86_64 + #else + #define uECC_PLATFORM uECC_arch_other + #endif +#endif + +#ifndef uECC_ARM_USE_UMAAL + #if (uECC_PLATFORM == uECC_arm) && (__ARM_ARCH >= 6) + #define uECC_ARM_USE_UMAAL 1 + #elif (uECC_PLATFORM == uECC_arm_thumb2) && (__ARM_ARCH >= 6) && !__ARM_ARCH_7M__ + #define uECC_ARM_USE_UMAAL 1 + #else + #define uECC_ARM_USE_UMAAL 0 + #endif +#endif + +#ifndef uECC_WORD_SIZE + #if uECC_PLATFORM == uECC_avr + #define uECC_WORD_SIZE 1 + #elif (uECC_PLATFORM == uECC_x86_64 || uECC_PLATFORM == uECC_arm64) + #define uECC_WORD_SIZE 8 + #else + #define uECC_WORD_SIZE 4 + #endif +#endif + +#if (uECC_WORD_SIZE != 1) && (uECC_WORD_SIZE != 4) && (uECC_WORD_SIZE != 8) + #error "Unsupported value for uECC_WORD_SIZE" +#endif + +#if ((uECC_PLATFORM == uECC_avr) && (uECC_WORD_SIZE != 1)) + #pragma message ("uECC_WORD_SIZE must be 1 for AVR") + #undef uECC_WORD_SIZE + #define uECC_WORD_SIZE 1 +#endif + +#if ((uECC_PLATFORM == uECC_arm || uECC_PLATFORM == uECC_arm_thumb || \ + uECC_PLATFORM == uECC_arm_thumb2) && \ + (uECC_WORD_SIZE != 4)) + #pragma message ("uECC_WORD_SIZE must be 4 for ARM") + #undef uECC_WORD_SIZE + #define uECC_WORD_SIZE 4 +#endif + +#if defined(__SIZEOF_INT128__) || ((__clang_major__ * 100 + __clang_minor__) >= 302) + #define SUPPORTS_INT128 1 +#else + #define SUPPORTS_INT128 0 +#endif + +typedef int8_t wordcount_t; +typedef int16_t bitcount_t; +typedef int8_t cmpresult_t; + +#if (uECC_WORD_SIZE == 1) + +typedef uint8_t uECC_word_t; +typedef uint16_t uECC_dword_t; + +#define HIGH_BIT_SET 0x80 +#define uECC_WORD_BITS 8 +#define uECC_WORD_BITS_SHIFT 3 +#define uECC_WORD_BITS_MASK 0x07 + +#elif (uECC_WORD_SIZE == 4) + +typedef uint32_t uECC_word_t; +typedef uint64_t uECC_dword_t; + +#define HIGH_BIT_SET 0x80000000 +#define uECC_WORD_BITS 32 +#define uECC_WORD_BITS_SHIFT 5 +#define uECC_WORD_BITS_MASK 0x01F + +#elif (uECC_WORD_SIZE == 8) + +typedef uint64_t uECC_word_t; +#if SUPPORTS_INT128 +typedef unsigned __int128 uECC_dword_t; +#endif + +#define HIGH_BIT_SET 0x8000000000000000ull +#define uECC_WORD_BITS 64 +#define uECC_WORD_BITS_SHIFT 6 +#define uECC_WORD_BITS_MASK 0x03F + +#endif /* uECC_WORD_SIZE */ + +#endif /* _UECC_TYPES_H_ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC.c new file mode 100644 index 0000000000..b7bfc7ff92 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC.c @@ -0,0 +1,1882 @@ +/** + ****************************************************************************** + * @file uECC.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +#include "main.h" +#include "uECC.h" +#include "uECC_vli.h" + +#define HW_CRYPT_ACC /* Hardware Crypto accelerator */ +//#define TOGGLE_IO /* Toggle IO for debug */ + +#ifndef uECC_RNG_MAX_TRIES + #define uECC_RNG_MAX_TRIES 64 +#endif + +#if uECC_ENABLE_VLI_API + #define uECC_VLI_API +#else + #define uECC_VLI_API static +#endif + +#define CONCATX(a, ...) a ## __VA_ARGS__ +#define CONCAT(a, ...) CONCATX(a, __VA_ARGS__) + +#define STRX(a) #a +#define STR(a) STRX(a) + +#define EVAL(...) EVAL1(EVAL1(EVAL1(EVAL1(__VA_ARGS__)))) +#define EVAL1(...) EVAL2(EVAL2(EVAL2(EVAL2(__VA_ARGS__)))) +#define EVAL2(...) EVAL3(EVAL3(EVAL3(EVAL3(__VA_ARGS__)))) +#define EVAL3(...) EVAL4(EVAL4(EVAL4(EVAL4(__VA_ARGS__)))) +#define EVAL4(...) __VA_ARGS__ + +#define DEC_1 0 +#define DEC_2 1 +#define DEC_3 2 +#define DEC_4 3 +#define DEC_5 4 +#define DEC_6 5 +#define DEC_7 6 +#define DEC_8 7 +#define DEC_9 8 +#define DEC_10 9 +#define DEC_11 10 +#define DEC_12 11 +#define DEC_13 12 +#define DEC_14 13 +#define DEC_15 14 +#define DEC_16 15 +#define DEC_17 16 +#define DEC_18 17 +#define DEC_19 18 +#define DEC_20 19 +#define DEC_21 20 +#define DEC_22 21 +#define DEC_23 22 +#define DEC_24 23 +#define DEC_25 24 +#define DEC_26 25 +#define DEC_27 26 +#define DEC_28 27 +#define DEC_29 28 +#define DEC_30 29 +#define DEC_31 30 +#define DEC_32 31 + +#define DEC(N) CONCAT(DEC_, N) + +#define SECOND_ARG(_, val, ...) val +#define SOME_CHECK_0 ~, 0 +#define GET_SECOND_ARG(...) SECOND_ARG(__VA_ARGS__, SOME,) +#define SOME_OR_0(N) GET_SECOND_ARG(CONCAT(SOME_CHECK_, N)) + +#define EMPTY(...) +#define DEFER(...) __VA_ARGS__ EMPTY() + +#define REPEAT_NAME_0() REPEAT_0 +#define REPEAT_NAME_SOME() REPEAT_SOME +#define REPEAT_0(...) +#define REPEAT_SOME(N, stuff) DEFER(CONCAT(REPEAT_NAME_, SOME_OR_0(DEC(N))))()(DEC(N), stuff) stuff +#define REPEAT(N, stuff) EVAL(REPEAT_SOME(N, stuff)) + +#define REPEATM_NAME_0() REPEATM_0 +#define REPEATM_NAME_SOME() REPEATM_SOME +#define REPEATM_0(...) +#define REPEATM_SOME(N, macro) macro(N) \ + DEFER(CONCAT(REPEATM_NAME_, SOME_OR_0(DEC(N))))()(DEC(N), macro) +#define REPEATM(N, macro) EVAL(REPEATM_SOME(N, macro)) + +#include "platform-specific.inc" + +#if (uECC_WORD_SIZE == 1) + #if uECC_SUPPORTS_secp160r1 + #define uECC_MAX_WORDS 21 /* Due to the size of curve_n. */ + #endif + #if uECC_SUPPORTS_secp192r1 + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 24 + #endif + #if uECC_SUPPORTS_secp224r1 + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 28 + #endif + #if (uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1) + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 32 + #endif +#elif (uECC_WORD_SIZE == 4) + #if uECC_SUPPORTS_secp160r1 + #define uECC_MAX_WORDS 6 /* Due to the size of curve_n. */ + #endif + #if uECC_SUPPORTS_secp192r1 + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 6 + #endif + #if uECC_SUPPORTS_secp224r1 + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 7 + #endif + #if (uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1) + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 8 + #endif +#elif (uECC_WORD_SIZE == 8) + #if uECC_SUPPORTS_secp160r1 + #define uECC_MAX_WORDS 3 + #endif + #if uECC_SUPPORTS_secp192r1 + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 3 + #endif + #if uECC_SUPPORTS_secp224r1 + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 4 + #endif + #if (uECC_SUPPORTS_secp256r1 || uECC_SUPPORTS_secp256k1) + #undef uECC_MAX_WORDS + #define uECC_MAX_WORDS 4 + #endif +#endif /* uECC_WORD_SIZE */ + +#define BITS_TO_WORDS(num_bits) ((num_bits + ((uECC_WORD_SIZE * 8) - 1)) / (uECC_WORD_SIZE * 8)) +#define BITS_TO_BYTES(num_bits) ((num_bits + 7) / 8) + +struct uECC_Curve_t { + wordcount_t num_words; + wordcount_t num_bytes; + bitcount_t num_n_bits; + uECC_word_t p[uECC_MAX_WORDS]; + uECC_word_t n[uECC_MAX_WORDS]; + uECC_word_t G[uECC_MAX_WORDS * 2]; + uECC_word_t b[uECC_MAX_WORDS]; + void (*double_jacobian)(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * Z1, + uECC_Curve curve); +#if uECC_SUPPORT_COMPRESSED_POINT + void (*mod_sqrt)(uECC_word_t *a, uECC_Curve curve); +#endif + void (*x_side)(uECC_word_t *result, const uECC_word_t *x, uECC_Curve curve); +#if (uECC_OPTIMIZATION_LEVEL > 0) + void (*mmod_fast)(uECC_word_t *result, uECC_word_t *product); +#endif +}; + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN +static void bcopy(uint8_t *dst, + const uint8_t *src, + unsigned num_bytes) { + while (0 != num_bytes) { + num_bytes--; + dst[num_bytes] = src[num_bytes]; + } +} +#endif + +static cmpresult_t uECC_vli_cmp_unsafe(const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +#if (uECC_PLATFORM == uECC_arm || uECC_PLATFORM == uECC_arm_thumb || \ + uECC_PLATFORM == uECC_arm_thumb2) + #include "asm_arm.inc" +#endif + +#if (uECC_PLATFORM == uECC_avr) + #include "asm_avr.inc" +#endif + +#if default_RNG_defined +static uECC_RNG_Function g_rng_function = &default_RNG; +#else +static uECC_RNG_Function g_rng_function = 0; +#endif + +void uECC_set_rng(uECC_RNG_Function rng_function) { + g_rng_function = rng_function; +} + +uECC_RNG_Function uECC_get_rng(void) { + return g_rng_function; +} + +int uECC_curve_private_key_size(uECC_Curve curve) { + return BITS_TO_BYTES(curve->num_n_bits); +} + +int uECC_curve_public_key_size(uECC_Curve curve) { + return 2 * curve->num_bytes; +} + +#if !asm_clear +uECC_VLI_API void uECC_vli_clear(uECC_word_t *vli, wordcount_t num_words) { + wordcount_t i; + for (i = 0; i < num_words; ++i) { + vli[i] = 0; + } +} +#endif /* !asm_clear */ + +/* Constant-time comparison to zero - secure way to compare long integers */ +/* Returns 1 if vli == 0, 0 otherwise. */ +uECC_VLI_API uECC_word_t uECC_vli_isZero(const uECC_word_t *vli, wordcount_t num_words) { + uECC_word_t bits = 0; + wordcount_t i; + for (i = 0; i < num_words; ++i) { + bits |= vli[i]; + } + return (bits == 0); +} + +/* Returns nonzero if bit 'bit' of vli is set. */ +uECC_VLI_API uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit) { + return (vli[bit >> uECC_WORD_BITS_SHIFT] & ((uECC_word_t)1 << (bit & uECC_WORD_BITS_MASK))); +} + +/* Counts the number of words in vli. */ +static wordcount_t vli_numDigits(const uECC_word_t *vli, const wordcount_t max_words) { + wordcount_t i; + /* Search from the end until we find a non-zero digit. + We do it in reverse because we expect that most digits will be nonzero. */ + for (i = max_words - 1; i >= 0 && vli[i] == 0; --i) { + } + + return (i + 1); +} + +/* Counts the number of bits required to represent vli. */ +uECC_VLI_API bitcount_t uECC_vli_numBits(const uECC_word_t *vli, const wordcount_t max_words) { + uECC_word_t i; + uECC_word_t digit; + + wordcount_t num_digits = vli_numDigits(vli, max_words); + if (num_digits == 0) { + return 0; + } + + digit = vli[num_digits - 1]; + for (i = 0; digit; ++i) { + digit >>= 1; + } + + return (((bitcount_t)(num_digits - 1) << uECC_WORD_BITS_SHIFT) + i); +} + +/* Sets dest = src. */ +#if !asm_set +uECC_VLI_API void uECC_vli_set(uECC_word_t *dest, const uECC_word_t *src, wordcount_t num_words) { + wordcount_t i; + for (i = 0; i < num_words; ++i) { + dest[i] = src[i]; + } +} +#endif /* !asm_set */ + +/* Returns sign of left - right. */ +static cmpresult_t uECC_vli_cmp_unsafe(const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { + wordcount_t i; + for (i = num_words - 1; i >= 0; --i) { + if (left[i] > right[i]) { + return 1; + } else if (left[i] < right[i]) { + return -1; + } + } + return 0; +} + +/* Constant-time comparison function - secure way to compare long integers */ +/* Returns one if left == right, zero otherwise. */ +uECC_VLI_API uECC_word_t uECC_vli_equal(const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { + uECC_word_t diff = 0; + wordcount_t i; + for (i = num_words - 1; i >= 0; --i) { + diff |= (left[i] ^ right[i]); + } + return (diff == 0); +} + +uECC_VLI_API uECC_word_t uECC_vli_sub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Returns sign of left - right, in constant time. */ +uECC_VLI_API cmpresult_t uECC_vli_cmp(const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { + uECC_word_t tmp[uECC_MAX_WORDS]; + uECC_word_t neg = !!uECC_vli_sub(tmp, left, right, num_words); + uECC_word_t equal = uECC_vli_isZero(tmp, num_words); + return (!equal - 2 * neg); +} + +/* Computes vli = vli >> 1. */ +#if !asm_rshift1 +uECC_VLI_API void uECC_vli_rshift1(uECC_word_t *vli, wordcount_t num_words) { + +#ifdef TOGGLE_IO + GPIOA->DAT |= 0x0020; +#endif + +// uECC_word_t result[16], i; + +#ifdef HW_CRYPT_ACC + + CRYPT->PTRA = (unsigned int)&vli[0]; + CRYPT->PTRO = (unsigned int)&vli[0]; +// CRYPT->PTRO = (unsigned int)&result[0]; + CRYPT->CTRL = ((num_words-1)<<8)|0x31; + + while (CRYPT->CTRL & 0x1); + +#else + + uECC_word_t *end = vli; + uECC_word_t carry = 0; + + vli += num_words; + while (vli-- > end) { + uECC_word_t temp = *vli; + *vli = (temp >> 1) | carry; + carry = temp << (uECC_WORD_BITS - 1); + } + +// for (i=0;iDAT &= ~0x0020; +#endif + +} +#endif /* !asm_rshift1 */ + +/* Computes result = left + right, returning carry. Can modify in place. */ +#if !asm_add +uECC_VLI_API uECC_word_t uECC_vli_add(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { +#ifdef TOGGLE_IO + GPIOA->DAT |= 0x0040; +#endif + +#ifdef HW_CRYPT_ACC + uECC_word_t tmp, ii; + uECC_word_t tmp_buf[16]; +// uECC_word_t result2[16]; + + tmp = (unsigned int)&left[0]; + if ((tmp&0xF0000000) == 0) { + for (ii=0;iiPTRA = (unsigned int)&tmp_buf[0]; + } else { + CRYPT->PTRA = tmp; + } + tmp = (unsigned int)&right[0]; + if ((tmp&0xF0000000) == 0) { + for (ii=0;iiPTRB = (unsigned int)&tmp_buf[0]; + } else { + CRYPT->PTRB = tmp; + } + CRYPT->PTRO = (unsigned int)&result[0]; + CRYPT->CTRL = ((num_words-1)<<8)|0x11; + +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0040; +#endif + + return CRYPT->CARRY; + +#else + uECC_word_t carry = 0; + wordcount_t i; + + for (i = 0; i < num_words; ++i) { + uECC_word_t sum = left[i] + right[i] + carry; + if (sum != left[i]) { + carry = (sum < left[i]); + } + result[i] = sum; + } + +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0040; +#endif + + return carry; + +#endif + +// for (i=0;iDAT |= 0x0080; +#endif + +#ifdef HW_CRYPT_ACC + uECC_word_t tmp, ii; + uECC_word_t tmp_buf[16]; +// uECC_word_t result2[16]; + + tmp = (unsigned int)&left[0]; + if ((tmp&0xF0000000) == 0) { + for (ii=0;iiPTRA = (unsigned int)&tmp_buf[0]; + } else { + CRYPT->PTRA = tmp; + } + tmp = (unsigned int)&right[0]; + if ((tmp&0xF0000000) == 0) { + for (ii=0;iiPTRB = (unsigned int)&tmp_buf[0]; + } else { + CRYPT->PTRB = tmp; + } + CRYPT->PTRO = (unsigned int)&result[0]; + CRYPT->CTRL = ((num_words-1)<<8)|0x21; + +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0080; +#endif + + return CRYPT->CARRY; + +#else + + uECC_word_t borrow = 0; + wordcount_t i; + for (i = 0; i < num_words; ++i) { + uECC_word_t diff = left[i] - right[i] - borrow; + if (diff != left[i]) { + borrow = (diff > left[i]); + } + result[i] = diff; + } +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0080; +#endif + +// for (i=0;i 0) && \ + ((uECC_WORD_SIZE == 1) || (uECC_WORD_SIZE == 8))) +/*static*/ void muladd(uECC_word_t a, + uECC_word_t b, + uECC_word_t *r0, + uECC_word_t *r1, + uECC_word_t *r2) { +#if uECC_WORD_SIZE == 8 && !SUPPORTS_INT128 + uint64_t a0 = a & 0xffffffffull; + uint64_t a1 = a >> 32; + uint64_t b0 = b & 0xffffffffull; + uint64_t b1 = b >> 32; + + uint64_t i0 = a0 * b0; + uint64_t i1 = a0 * b1; + uint64_t i2 = a1 * b0; + uint64_t i3 = a1 * b1; + + uint64_t p0, p1; + + i2 += (i0 >> 32); + i2 += i1; + if (i2 < i1) { /* overflow */ + i3 += 0x100000000ull; + } + + p0 = (i0 & 0xffffffffull) | (i2 << 32); + p1 = i3 + (i2 >> 32); + + *r0 += p0; + *r1 += (p1 + (*r0 < p0)); + *r2 += ((*r1 < p1) || (*r1 == p1 && *r0 < p0)); +#else + uECC_dword_t p = (uECC_dword_t)a * b; + uECC_dword_t r01 = ((uECC_dword_t)(*r1) << uECC_WORD_BITS) | *r0; + r01 += p; + *r2 += (r01 < p); + *r1 = r01 >> uECC_WORD_BITS; + *r0 = (uECC_word_t)r01; +#endif +} +#endif /* muladd needed */ + +#if !asm_mult +uECC_VLI_API void uECC_vli_mult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words) { + +// uECC_word_t result2[32]; +#ifdef TOGGLE_IO + GPIOA->DAT |= 0x0800; +#endif + +#ifdef HW_CRYPT_ACC + uECC_word_t tmp, ii; + uECC_word_t tmp_buf[16]; + + tmp = (unsigned int)&left[0]; + if ((tmp&0xF0000000) == 0) { + for (ii=0;iiPTRA = (unsigned int)&tmp_buf[0]; + } else { + CRYPT->PTRA = tmp; + } + tmp = (unsigned int)&right[0]; + if ((tmp&0xF0000000) == 0) { + for (ii=0;iiPTRB = (unsigned int)&tmp_buf[0]; + } else { + CRYPT->PTRB = tmp; + } + CRYPT->PTRO = (unsigned int)&result[0]; + CRYPT->CTRL = ((num_words-1)<<8)|0x1; + + while (CRYPT->CTRL & 0x1); +#else + uECC_word_t r0 = 0; + uECC_word_t r1 = 0; + uECC_word_t r2 = 0; + wordcount_t i, k; + + /* Compute each digit of result in sequence, maintaining the carries. */ + for (k = 0; k < num_words; ++k) { + for (i = 0; i <= k; ++i) { + muladd(left[i], right[k - i], &r0, &r1, &r2); + } + result[k] = r0; + r0 = r1; + r1 = r2; + r2 = 0; + } + for (k = num_words; k < num_words * 2 - 1; ++k) { + for (i = (k + 1) - num_words; i < num_words; ++i) { + muladd(left[i], right[k - i], &r0, &r1, &r2); + } + result[k] = r0; + r0 = r1; + r1 = r2; + r2 = 0; + } + result[num_words * 2 - 1] = r0; + +// for (i=0;i<(num_words * 2);i++) { +// if (result[i] != result2[i]) { +// print1("MULT Fail!!!\n"); +// } +// } +#endif + +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0800; +#endif + + +} +#endif /* !asm_mult */ + +#if uECC_SQUARE_FUNC + +#if !asm_square +/*static*/ void mul2add(uECC_word_t a, + uECC_word_t b, + uECC_word_t *r0, + uECC_word_t *r1, + uECC_word_t *r2) { +#if uECC_WORD_SIZE == 8 && !SUPPORTS_INT128 + uint64_t a0 = a & 0xffffffffull; + uint64_t a1 = a >> 32; + uint64_t b0 = b & 0xffffffffull; + uint64_t b1 = b >> 32; + + uint64_t i0 = a0 * b0; + uint64_t i1 = a0 * b1; + uint64_t i2 = a1 * b0; + uint64_t i3 = a1 * b1; + + uint64_t p0, p1; + + i2 += (i0 >> 32); + i2 += i1; + if (i2 < i1) + { /* overflow */ + i3 += 0x100000000ull; + } + + p0 = (i0 & 0xffffffffull) | (i2 << 32); + p1 = i3 + (i2 >> 32); + + *r2 += (p1 >> 63); + p1 = (p1 << 1) | (p0 >> 63); + p0 <<= 1; + + *r0 += p0; + *r1 += (p1 + (*r0 < p0)); + *r2 += ((*r1 < p1) || (*r1 == p1 && *r0 < p0)); +#else + uECC_dword_t p = (uECC_dword_t)a * b; + uECC_dword_t r01 = ((uECC_dword_t)(*r1) << uECC_WORD_BITS) | *r0; + *r2 += (p >> (uECC_WORD_BITS * 2 - 1)); + p *= 2; + r01 += p; + *r2 += (r01 < p); + *r1 = r01 >> uECC_WORD_BITS; + *r0 = (uECC_word_t)r01; +#endif +} + +uECC_VLI_API void uECC_vli_square(uECC_word_t *result, + const uECC_word_t *left, + wordcount_t num_words) { +// uECC_word_t result2[32]; + +#ifdef TOGGLE_IO + GPIOA->DAT |= 0x0100; +#endif + +#ifdef HW_CRYPT_ACC + + CRYPT->PTRA = (unsigned int)&left[0]; + CRYPT->PTRB = (unsigned int)&left[0]; + CRYPT->PTRO = (unsigned int)&result[0]; + CRYPT->CTRL = ((num_words-1)<<8)|0x1; + + while (CRYPT->CTRL & 0x1); + +#else + uECC_word_t r0 = 0; + uECC_word_t r1 = 0; + uECC_word_t r2 = 0; + + wordcount_t i, k; + + for (k = 0; k < num_words * 2 - 1; ++k) { + uECC_word_t min = (k < num_words ? 0 : (k + 1) - num_words); + for (i = min; i <= k && i <= k - i; ++i) { + if (i < k-i) { + mul2add(left[i], left[k - i], &r0, &r1, &r2); + } else { + muladd(left[i], left[k - i], &r0, &r1, &r2); + } + } + result[k] = r0; + r0 = r1; + r1 = r2; + r2 = 0; + } + + result[num_words * 2 - 1] = r0; + +// for (i=0;i<(num_words * 2);i++) { +// if (result[i] != result2[i]) { +// print1("SQUARE Fail!!!\n"); +// } +// } + +#endif + +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0100; +#endif + +} +#endif /* !asm_square */ + +#else /* uECC_SQUARE_FUNC */ + +#if uECC_ENABLE_VLI_API +uECC_VLI_API void uECC_vli_square(uECC_word_t *result, + const uECC_word_t *left, + wordcount_t num_words) { + uECC_vli_mult(result, left, left, num_words); +} +#endif /* uECC_ENABLE_VLI_API */ + +#endif /* uECC_SQUARE_FUNC */ + +/* Computes result = (left + right) % mod. + Assumes that left < mod and right < mod, and that result does not overlap mod. */ +uECC_VLI_API void uECC_vli_modAdd(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t carry = uECC_vli_add(result, left, right, num_words); + if (carry || uECC_vli_cmp_unsafe(mod, result, num_words) != 1) { + /* result > mod (result = mod + remainder), so subtract mod to get remainder. */ + uECC_vli_sub(result, result, mod, num_words); + } +} + +/* Computes result = (left - right) % mod. + Assumes that left < mod and right < mod, and that result does not overlap mod. */ +uECC_VLI_API void uECC_vli_modSub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t l_borrow = uECC_vli_sub(result, left, right, num_words); + if (l_borrow) { + /* In this case, result == -diff == (max int) - diff. Since -x % d == d - x, + we can get the correct result from result + mod (with overflow). */ + uECC_vli_add(result, result, mod, num_words); + } +} + +/* Computes result = product % mod, where product is 2N words long. */ +/* Currently only designed to work for curve_p or curve_n. */ +uECC_VLI_API void uECC_vli_mmod(uECC_word_t *result, + uECC_word_t *product, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t mod_multiple[2 * uECC_MAX_WORDS]; + uECC_word_t tmp[2 * uECC_MAX_WORDS]; + uECC_word_t *v[2] = {tmp, product}; + uECC_word_t index; + + /* Shift mod so its highest set bit is at the maximum position. */ + bitcount_t shift = (num_words * 2 * uECC_WORD_BITS) - uECC_vli_numBits(mod, num_words); + wordcount_t word_shift = shift / uECC_WORD_BITS; + wordcount_t bit_shift = shift % uECC_WORD_BITS; + uECC_word_t carry = 0; + uECC_vli_clear(mod_multiple, word_shift); + if (bit_shift > 0) { + for(index = 0; index < (uECC_word_t)num_words; ++index) { + mod_multiple[word_shift + index] = (mod[index] << bit_shift) | carry; + carry = mod[index] >> (uECC_WORD_BITS - bit_shift); + } + } else { + uECC_vli_set(mod_multiple + word_shift, mod, num_words); + } + +// uECC_word_t result2[32], borrow2, j; + + for (index = 1; shift >= 0; --shift) { + uECC_word_t borrow = 0; +#ifdef HW_CRYPT_ACC + borrow = uECC_vli_sub(&v[1 - index][0], &v[index][0], mod_multiple, num_words*2); +#else + wordcount_t i; + for (i = 0; i < num_words * 2; ++i) { + uECC_word_t diff = v[index][i] - mod_multiple[i] - borrow; + if (diff != v[index][i]) { + borrow = (diff > v[index][i]); + } + v[1 - index][i] = diff; + } +#endif + index = !(index ^ borrow); /* Swap the index if there was no borrow */ +#ifdef HW_CRYPT_ACC + uECC_vli_rshift1(mod_multiple, num_words*2); +#else + uECC_vli_rshift1(mod_multiple, num_words); + mod_multiple[num_words - 1] |= mod_multiple[num_words] << (uECC_WORD_BITS - 1); + uECC_vli_rshift1(mod_multiple + num_words, num_words); +#endif + } + uECC_vli_set(result, v[index], num_words); +} + +/* Computes result = (left * right) % mod. */ +uECC_VLI_API void uECC_vli_modMult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t product[2 * uECC_MAX_WORDS]; +#ifdef TOGGLE_IO + GPIOA->DAT |= 0x0200; +#endif + uECC_vli_mult(product, left, right, num_words); + uECC_vli_mmod(result, product, mod, num_words); +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0200; +#endif +} + +uECC_VLI_API void uECC_vli_modMult_fast(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + uECC_Curve curve) { + uECC_word_t product[2 * uECC_MAX_WORDS]; + +#ifdef TOGGLE_IO + GPIOA->DAT |= 0x0010; +#endif + + uECC_vli_mult(product, left, right, curve->num_words); +#if (uECC_OPTIMIZATION_LEVEL > 0) + curve->mmod_fast(result, product); +#else + uECC_vli_mmod(result, product, curve->p, curve->num_words); +#endif + +#ifdef TOGGLE_IO + GPIOA->DAT &= ~0x0010; +#endif + +} + +#if uECC_SQUARE_FUNC + +#if uECC_ENABLE_VLI_API +/* Computes result = left^2 % mod. */ +uECC_VLI_API void uECC_vli_modSquare(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t product[2 * uECC_MAX_WORDS]; + uECC_vli_square(product, left, num_words); + uECC_vli_mmod(result, product, mod, num_words); +} +#endif /* uECC_ENABLE_VLI_API */ + +uECC_VLI_API void uECC_vli_modSquare_fast(uECC_word_t *result, + const uECC_word_t *left, + uECC_Curve curve) { + uECC_word_t product[2 * uECC_MAX_WORDS]; + uECC_vli_square(product, left, curve->num_words); +#if (uECC_OPTIMIZATION_LEVEL > 0) + curve->mmod_fast(result, product); +#else + uECC_vli_mmod(result, product, curve->p, curve->num_words); +#endif +} + +#else /* uECC_SQUARE_FUNC */ + +#if uECC_ENABLE_VLI_API +uECC_VLI_API void uECC_vli_modSquare(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_vli_modMult(result, left, left, mod, num_words); +} +#endif /* uECC_ENABLE_VLI_API */ + +uECC_VLI_API void uECC_vli_modSquare_fast(uECC_word_t *result, + const uECC_word_t *left, + uECC_Curve curve) { + uECC_vli_modMult_fast(result, left, left, curve); +} + +#endif /* uECC_SQUARE_FUNC */ + +#define EVEN(vli) (!(vli[0] & 1)) +static void vli_modInv_update(uECC_word_t *uv, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t carry = 0; + if (!EVEN(uv)) { + carry = uECC_vli_add(uv, uv, mod, num_words); + } + uECC_vli_rshift1(uv, num_words); + if (carry) { + uv[num_words - 1] |= HIGH_BIT_SET; + } +} + +/* Computes result = (1 / input) % mod. All VLIs are the same size. + See "From Euclid's GCD to Montgomery Multiplication to the Great Divide" */ +uECC_VLI_API void uECC_vli_modInv(uECC_word_t *result, + const uECC_word_t *input, + const uECC_word_t *mod, + wordcount_t num_words) { + uECC_word_t a[uECC_MAX_WORDS], b[uECC_MAX_WORDS], u[uECC_MAX_WORDS], v[uECC_MAX_WORDS]; + cmpresult_t cmpResult; + + if (uECC_vli_isZero(input, num_words)) { + uECC_vli_clear(result, num_words); + return; + } + + uECC_vli_set(a, input, num_words); + uECC_vli_set(b, mod, num_words); + uECC_vli_clear(u, num_words); + u[0] = 1; + uECC_vli_clear(v, num_words); + while ((cmpResult = uECC_vli_cmp_unsafe(a, b, num_words)) != 0) { + if (EVEN(a)) { + uECC_vli_rshift1(a, num_words); + vli_modInv_update(u, mod, num_words); + } else if (EVEN(b)) { + uECC_vli_rshift1(b, num_words); + vli_modInv_update(v, mod, num_words); + } else if (cmpResult > 0) { + uECC_vli_sub(a, a, b, num_words); + uECC_vli_rshift1(a, num_words); + if (uECC_vli_cmp_unsafe(u, v, num_words) < 0) { + uECC_vli_add(u, u, mod, num_words); + } + uECC_vli_sub(u, u, v, num_words); + vli_modInv_update(u, mod, num_words); + } else { + uECC_vli_sub(b, b, a, num_words); + uECC_vli_rshift1(b, num_words); + if (uECC_vli_cmp_unsafe(v, u, num_words) < 0) { + uECC_vli_add(v, v, mod, num_words); + } + uECC_vli_sub(v, v, u, num_words); + vli_modInv_update(v, mod, num_words); + } + } + uECC_vli_set(result, u, num_words); +} + +/* ------ Point operations ------ */ + +#include "curve-specific.inc" + +/* Returns 1 if 'point' is the point at infinity, 0 otherwise. */ +#define EccPoint_isZero(point, curve) uECC_vli_isZero((point), (curve)->num_words * 2) + +/* Point multiplication algorithm using Montgomery's ladder with co-Z coordinates. +From http://eprint.iacr.org/2011/338.pdf +*/ + +/* Modify (x1, y1) => (x1 * z^2, y1 * z^3) */ +static void apply_z(uECC_word_t * X1, + uECC_word_t * Y1, + const uECC_word_t * const Z, + uECC_Curve curve) { + uECC_word_t t1[uECC_MAX_WORDS]; + + uECC_vli_modSquare_fast(t1, Z, curve); /* z^2 */ + uECC_vli_modMult_fast(X1, X1, t1, curve); /* x1 * z^2 */ + uECC_vli_modMult_fast(t1, t1, Z, curve); /* z^3 */ + uECC_vli_modMult_fast(Y1, Y1, t1, curve); /* y1 * z^3 */ +} + +/* P = (x1, y1) => 2P, (x2, y2) => P' */ +static void XYcZ_initial_double(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * X2, + uECC_word_t * Y2, + const uECC_word_t * const initial_Z, + uECC_Curve curve) { + uECC_word_t z[uECC_MAX_WORDS]; + wordcount_t num_words = curve->num_words; + if (initial_Z) { + uECC_vli_set(z, initial_Z, num_words); + } else { + uECC_vli_clear(z, num_words); + z[0] = 1; + } + + uECC_vli_set(X2, X1, num_words); + uECC_vli_set(Y2, Y1, num_words); + + apply_z(X1, Y1, z, curve); + curve->double_jacobian(X1, Y1, z, curve); + apply_z(X2, Y2, z, curve); +} + +/* Input P = (x1, y1, Z), Q = (x2, y2, Z) + Output P' = (x1', y1', Z3), P + Q = (x3, y3, Z3) + or P => P', Q => P + Q +*/ +static void XYcZ_add(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * X2, + uECC_word_t * Y2, + uECC_Curve curve) { + /* t1 = X1, t2 = Y1, t3 = X2, t4 = Y2 */ + uECC_word_t t5[uECC_MAX_WORDS]; + wordcount_t num_words = curve->num_words; + + uECC_vli_modSub(t5, X2, X1, curve->p, num_words); /* t5 = x2 - x1 */ + uECC_vli_modSquare_fast(t5, t5, curve); /* t5 = (x2 - x1)^2 = A */ + uECC_vli_modMult_fast(X1, X1, t5, curve); /* t1 = x1*A = B */ + uECC_vli_modMult_fast(X2, X2, t5, curve); /* t3 = x2*A = C */ + uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y2 - y1 */ + uECC_vli_modSquare_fast(t5, Y2, curve); /* t5 = (y2 - y1)^2 = D */ + + uECC_vli_modSub(t5, t5, X1, curve->p, num_words); /* t5 = D - B */ + uECC_vli_modSub(t5, t5, X2, curve->p, num_words); /* t5 = D - B - C = x3 */ + uECC_vli_modSub(X2, X2, X1, curve->p, num_words); /* t3 = C - B */ + uECC_vli_modMult_fast(Y1, Y1, X2, curve); /* t2 = y1*(C - B) */ + uECC_vli_modSub(X2, X1, t5, curve->p, num_words); /* t3 = B - x3 */ + uECC_vli_modMult_fast(Y2, Y2, X2, curve); /* t4 = (y2 - y1)*(B - x3) */ + uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y3 */ + + uECC_vli_set(X2, t5, num_words); +} + +/* Input P = (x1, y1, Z), Q = (x2, y2, Z) + Output P + Q = (x3, y3, Z3), P - Q = (x3', y3', Z3) + or P => P - Q, Q => P + Q +*/ +static void XYcZ_addC(uECC_word_t * X1, + uECC_word_t * Y1, + uECC_word_t * X2, + uECC_word_t * Y2, + uECC_Curve curve) { + /* t1 = X1, t2 = Y1, t3 = X2, t4 = Y2 */ + uECC_word_t t5[uECC_MAX_WORDS]; + uECC_word_t t6[uECC_MAX_WORDS]; + uECC_word_t t7[uECC_MAX_WORDS]; + wordcount_t num_words = curve->num_words; + + uECC_vli_modSub(t5, X2, X1, curve->p, num_words); /* t5 = x2 - x1 */ + uECC_vli_modSquare_fast(t5, t5, curve); /* t5 = (x2 - x1)^2 = A */ + uECC_vli_modMult_fast(X1, X1, t5, curve); /* t1 = x1*A = B */ + uECC_vli_modMult_fast(X2, X2, t5, curve); /* t3 = x2*A = C */ + uECC_vli_modAdd(t5, Y2, Y1, curve->p, num_words); /* t5 = y2 + y1 */ + uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y2 - y1 */ + + uECC_vli_modSub(t6, X2, X1, curve->p, num_words); /* t6 = C - B */ + uECC_vli_modMult_fast(Y1, Y1, t6, curve); /* t2 = y1 * (C - B) = E */ + uECC_vli_modAdd(t6, X1, X2, curve->p, num_words); /* t6 = B + C */ + uECC_vli_modSquare_fast(X2, Y2, curve); /* t3 = (y2 - y1)^2 = D */ + uECC_vli_modSub(X2, X2, t6, curve->p, num_words); /* t3 = D - (B + C) = x3 */ + + uECC_vli_modSub(t7, X1, X2, curve->p, num_words); /* t7 = B - x3 */ + uECC_vli_modMult_fast(Y2, Y2, t7, curve); /* t4 = (y2 - y1)*(B - x3) */ + uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = (y2 - y1)*(B - x3) - E = y3 */ + + uECC_vli_modSquare_fast(t7, t5, curve); /* t7 = (y2 + y1)^2 = F */ + uECC_vli_modSub(t7, t7, t6, curve->p, num_words); /* t7 = F - (B + C) = x3' */ + uECC_vli_modSub(t6, t7, X1, curve->p, num_words); /* t6 = x3' - B */ + uECC_vli_modMult_fast(t6, t6, t5, curve); /* t6 = (y2+y1)*(x3' - B) */ + uECC_vli_modSub(Y1, t6, Y1, curve->p, num_words); /* t2 = (y2+y1)*(x3' - B) - E = y3' */ + + uECC_vli_set(X1, t7, num_words); +} + +/* result may overlap point. */ +static void EccPoint_mult(uECC_word_t * result, + const uECC_word_t * point, + const uECC_word_t * scalar, + const uECC_word_t * initial_Z, + bitcount_t num_bits, + uECC_Curve curve) { + /* R0 and R1 */ + uECC_word_t Rx[2][uECC_MAX_WORDS]; + uECC_word_t Ry[2][uECC_MAX_WORDS]; + uECC_word_t z[uECC_MAX_WORDS]; + bitcount_t i; + uECC_word_t nb; + wordcount_t num_words = curve->num_words; + + uECC_vli_set(Rx[1], point, num_words); + uECC_vli_set(Ry[1], point + num_words, num_words); + + XYcZ_initial_double(Rx[1], Ry[1], Rx[0], Ry[0], initial_Z, curve); + + for (i = num_bits - 2; i > 0; --i) { + nb = !uECC_vli_testBit(scalar, i); + XYcZ_addC(Rx[1 - nb], Ry[1 - nb], Rx[nb], Ry[nb], curve); + XYcZ_add(Rx[nb], Ry[nb], Rx[1 - nb], Ry[1 - nb], curve); + } + + nb = !uECC_vli_testBit(scalar, 0); + XYcZ_addC(Rx[1 - nb], Ry[1 - nb], Rx[nb], Ry[nb], curve); + + /* Find final 1/Z value. */ + uECC_vli_modSub(z, Rx[1], Rx[0], curve->p, num_words); /* X1 - X0 */ + uECC_vli_modMult_fast(z, z, Ry[1 - nb], curve); /* Yb * (X1 - X0) */ + uECC_vli_modMult_fast(z, z, point, curve); /* xP * Yb * (X1 - X0) */ + uECC_vli_modInv(z, z, curve->p, num_words); /* 1 / (xP * Yb * (X1 - X0)) */ + /* yP / (xP * Yb * (X1 - X0)) */ + uECC_vli_modMult_fast(z, z, point + num_words, curve); + uECC_vli_modMult_fast(z, z, Rx[1 - nb], curve); /* Xb * yP / (xP * Yb * (X1 - X0)) */ + /* End 1/Z calculation */ + + XYcZ_add(Rx[nb], Ry[nb], Rx[1 - nb], Ry[1 - nb], curve); + apply_z(Rx[0], Ry[0], z, curve); + + uECC_vli_set(result, Rx[0], num_words); + uECC_vli_set(result + num_words, Ry[0], num_words); +} + +static uECC_word_t regularize_k(const uECC_word_t * const k, + uECC_word_t *k0, + uECC_word_t *k1, + uECC_Curve curve) { + wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits); + bitcount_t num_n_bits = curve->num_n_bits; + uECC_word_t carry = uECC_vli_add(k0, k, curve->n, num_n_words) || + (num_n_bits < ((bitcount_t)num_n_words * uECC_WORD_SIZE * 8) && + uECC_vli_testBit(k0, num_n_bits)); + uECC_vli_add(k1, k0, curve->n, num_n_words); + return carry; +} + +static uECC_word_t EccPoint_compute_public_key(uECC_word_t *result, + uECC_word_t *private_key, + uECC_Curve curve) { + uECC_word_t tmp1[uECC_MAX_WORDS]; + uECC_word_t tmp2[uECC_MAX_WORDS]; + uECC_word_t *p2[2] = {tmp1, tmp2}; + uECC_word_t carry; + + /* Regularize the bitcount for the private key so that attackers cannot use a side channel + attack to learn the number of leading zeros. */ + carry = regularize_k(private_key, tmp1, tmp2, curve); + + EccPoint_mult(result, curve->G, p2[!carry], 0, curve->num_n_bits + 1, curve); + + if (EccPoint_isZero(result, curve)) { + return 0; + } + return 1; +} + +#if uECC_WORD_SIZE == 1 + +uECC_VLI_API void uECC_vli_nativeToBytes(uint8_t *bytes, + int num_bytes, + const uint8_t *native) { + wordcount_t i; + for (i = 0; i < num_bytes; ++i) { + bytes[i] = native[(num_bytes - 1) - i]; + } +} + +uECC_VLI_API void uECC_vli_bytesToNative(uint8_t *native, + const uint8_t *bytes, + int num_bytes) { + uECC_vli_nativeToBytes(native, num_bytes, bytes); +} + +#else + +uECC_VLI_API void uECC_vli_nativeToBytes(uint8_t *bytes, + int num_bytes, + const uECC_word_t *native) { + wordcount_t i; + for (i = 0; i < num_bytes; ++i) { + unsigned b = num_bytes - 1 - i; + bytes[i] = native[b / uECC_WORD_SIZE] >> (8 * (b % uECC_WORD_SIZE)); + } +} + +uECC_VLI_API void uECC_vli_bytesToNative(uECC_word_t *native, + const uint8_t *bytes, + int num_bytes) { + wordcount_t i; + uECC_vli_clear(native, (num_bytes + (uECC_WORD_SIZE - 1)) / uECC_WORD_SIZE); + for (i = 0; i < num_bytes; ++i) { + unsigned b = num_bytes - 1 - i; + native[b / uECC_WORD_SIZE] |= + (uECC_word_t)bytes[i] << (8 * (b % uECC_WORD_SIZE)); + } +} + +#endif /* uECC_WORD_SIZE */ + +/* Generates a random integer in the range 0 < random < top. + Both random and top have num_words words. */ +uECC_VLI_API int uECC_generate_random_int(uECC_word_t *random, + const uECC_word_t *top, + wordcount_t num_words) { + uECC_word_t mask = (uECC_word_t)-1; + uECC_word_t tries; + bitcount_t num_bits = uECC_vli_numBits(top, num_words); + + if (!g_rng_function) { + return 0; + } + + for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) { + if (!g_rng_function((uint8_t *)random, num_words * uECC_WORD_SIZE)) { + return 0; + } + random[num_words - 1] &= mask >> ((bitcount_t)(num_words * uECC_WORD_SIZE * 8 - num_bits)); + if (!uECC_vli_isZero(random, num_words) && + uECC_vli_cmp(top, random, num_words) == 1) { + return 1; + } + } + return 0; +} + +int uECC_make_key(uint8_t *public_key, + uint8_t *private_key, + uECC_Curve curve) { +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + uECC_word_t *_private = (uECC_word_t *)private_key; + uECC_word_t *_public = (uECC_word_t *)public_key; +#else + uECC_word_t _private[uECC_MAX_WORDS]; + uECC_word_t _public[uECC_MAX_WORDS * 2]; +#endif + uECC_word_t tries; + + for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) { + if (!uECC_generate_random_int(_private, curve->n, BITS_TO_WORDS(curve->num_n_bits))) { + return 0; + } + + if (EccPoint_compute_public_key(_public, _private, curve)) { +#if uECC_VLI_NATIVE_LITTLE_ENDIAN == 0 + uECC_vli_nativeToBytes(private_key, BITS_TO_BYTES(curve->num_n_bits), _private); + uECC_vli_nativeToBytes(public_key, curve->num_bytes, _public); + uECC_vli_nativeToBytes( + public_key + curve->num_bytes, curve->num_bytes, _public + curve->num_words); +#endif + return 1; + } + } + return 0; +} + +int uECC_shared_secret(const uint8_t *public_key, + const uint8_t *private_key, + uint8_t *secret, + uECC_Curve curve) { + uECC_word_t _public[uECC_MAX_WORDS * 2]; + uECC_word_t _private[uECC_MAX_WORDS]; + + uECC_word_t tmp[uECC_MAX_WORDS]; + uECC_word_t *p2[2] = {_private, tmp}; + uECC_word_t *initial_Z = 0; + uECC_word_t carry; + wordcount_t num_words = curve->num_words; + wordcount_t num_bytes = curve->num_bytes; + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy((uint8_t *) _private, private_key, num_bytes); + bcopy((uint8_t *) _public, public_key, num_bytes*2); +#else + uECC_vli_bytesToNative(_private, private_key, BITS_TO_BYTES(curve->num_n_bits)); + uECC_vli_bytesToNative(_public, public_key, num_bytes); + uECC_vli_bytesToNative(_public + num_words, public_key + num_bytes, num_bytes); +#endif + + /* Regularize the bitcount for the private key so that attackers cannot use a side channel + attack to learn the number of leading zeros. */ + carry = regularize_k(_private, _private, tmp, curve); + + /* If an RNG function was specified, try to get a random initial Z value to improve + protection against side-channel attacks. */ + if (g_rng_function) { + if (!uECC_generate_random_int(p2[carry], curve->p, num_words)) { + return 0; + } + initial_Z = p2[carry]; + } + + EccPoint_mult(_public, _public, p2[!carry], initial_Z, curve->num_n_bits + 1, curve); +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy((uint8_t *) secret, (uint8_t *) _public, num_bytes); +#else + uECC_vli_nativeToBytes(secret, num_bytes, _public); +#endif + return !EccPoint_isZero(_public, curve); +} + +#if uECC_SUPPORT_COMPRESSED_POINT +void uECC_compress(const uint8_t *public_key, uint8_t *compressed, uECC_Curve curve) { + wordcount_t i; + for (i = 0; i < curve->num_bytes; ++i) { + compressed[i+1] = public_key[i]; + } +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + compressed[0] = 2 + (public_key[curve->num_bytes] & 0x01); +#else + compressed[0] = 2 + (public_key[curve->num_bytes * 2 - 1] & 0x01); +#endif +} + +void uECC_decompress(const uint8_t *compressed, uint8_t *public_key, uECC_Curve curve) { +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + uECC_word_t *point = (uECC_word_t *)public_key; +#else + uECC_word_t point[uECC_MAX_WORDS * 2]; +#endif + uECC_word_t *y = point + curve->num_words; +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy(public_key, compressed+1, curve->num_bytes); +#else + uECC_vli_bytesToNative(point, compressed + 1, curve->num_bytes); +#endif + curve->x_side(y, point, curve); + curve->mod_sqrt(y, curve); + + if ((y[0] & 0x01) != (compressed[0] & 0x01)) { + uECC_vli_sub(y, curve->p, y, curve->num_words); + } + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN == 0 + uECC_vli_nativeToBytes(public_key, curve->num_bytes, point); + uECC_vli_nativeToBytes(public_key + curve->num_bytes, curve->num_bytes, y); +#endif +} +#endif /* uECC_SUPPORT_COMPRESSED_POINT */ + +int uECC_valid_point(const uECC_word_t *point, uECC_Curve curve) { + uECC_word_t tmp1[uECC_MAX_WORDS]; + uECC_word_t tmp2[uECC_MAX_WORDS]; + wordcount_t num_words = curve->num_words; + + /* The point at infinity is invalid. */ + if (EccPoint_isZero(point, curve)) { + return 0; + } + + /* x and y must be smaller than p. */ + if (uECC_vli_cmp_unsafe(curve->p, point, num_words) != 1 || + uECC_vli_cmp_unsafe(curve->p, point + num_words, num_words) != 1) { + return 0; + } + + uECC_vli_modSquare_fast(tmp1, point + num_words, curve); + curve->x_side(tmp2, point, curve); /* tmp2 = x^3 + ax + b */ + + /* Make sure that y^2 == x^3 + ax + b */ + return (int)(uECC_vli_equal(tmp1, tmp2, num_words)); +} + +int uECC_valid_public_key(const uint8_t *public_key, uECC_Curve curve) { +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + uECC_word_t *_public = (uECC_word_t *)public_key; +#else + uECC_word_t _public[uECC_MAX_WORDS * 2]; +#endif + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN == 0 + uECC_vli_bytesToNative(_public, public_key, curve->num_bytes); + uECC_vli_bytesToNative( + _public + curve->num_words, public_key + curve->num_bytes, curve->num_bytes); +#endif + return uECC_valid_point(_public, curve); +} + +int uECC_compute_public_key(const uint8_t *private_key, uint8_t *public_key, uECC_Curve curve) { +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + uECC_word_t *_private = (uECC_word_t *)private_key; + uECC_word_t *_public = (uECC_word_t *)public_key; +#else + uECC_word_t _private[uECC_MAX_WORDS]; + uECC_word_t _public[uECC_MAX_WORDS * 2]; +#endif + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN == 0 + uECC_vli_bytesToNative(_private, private_key, BITS_TO_BYTES(curve->num_n_bits)); +#endif + + /* Make sure the private key is in the range [1, n-1]. */ + if (uECC_vli_isZero(_private, BITS_TO_WORDS(curve->num_n_bits))) { + return 0; + } + + if (uECC_vli_cmp(curve->n, _private, BITS_TO_WORDS(curve->num_n_bits)) != 1) { + return 0; + } + + /* Compute public key. */ + if (!EccPoint_compute_public_key(_public, _private, curve)) { + return 0; + } + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN == 0 + uECC_vli_nativeToBytes(public_key, curve->num_bytes, _public); + uECC_vli_nativeToBytes( + public_key + curve->num_bytes, curve->num_bytes, _public + curve->num_words); +#endif + return 1; +} + + +/* -------- ECDSA code -------- */ + +static void bits2int(uECC_word_t *native, + const uint8_t *bits, + unsigned bits_size, + uECC_Curve curve) { + unsigned num_n_bytes = BITS_TO_BYTES(curve->num_n_bits); + unsigned num_n_words = BITS_TO_WORDS(curve->num_n_bits); + int shift; + uECC_word_t carry; + uECC_word_t *ptr; + + if (bits_size > num_n_bytes) { + bits_size = num_n_bytes; + } + + uECC_vli_clear(native, num_n_words); +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy((uint8_t *) native, bits, bits_size); +#else + uECC_vli_bytesToNative(native, bits, bits_size); +#endif + if (bits_size * 8 <= (unsigned)curve->num_n_bits) { + return; + } + shift = bits_size * 8 - curve->num_n_bits; + carry = 0; + ptr = native + num_n_words; + while (ptr-- > native) { + uECC_word_t temp = *ptr; + *ptr = (temp >> shift) | carry; + carry = temp << (uECC_WORD_BITS - shift); + } + + /* Reduce mod curve_n */ + if (uECC_vli_cmp_unsafe(curve->n, native, num_n_words) != 1) { + uECC_vli_sub(native, native, curve->n, num_n_words); + } +} + +static int uECC_sign_with_k(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + uECC_word_t *k, + uint8_t *signature, + uECC_Curve curve) { + + uECC_word_t tmp[uECC_MAX_WORDS]; + uECC_word_t s[uECC_MAX_WORDS]; + uECC_word_t *k2[2] = {tmp, s}; +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + uECC_word_t *p = (uECC_word_t *)signature; +#else + uECC_word_t p[uECC_MAX_WORDS * 2]; +#endif + uECC_word_t carry; + wordcount_t num_words = curve->num_words; + wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits); + bitcount_t num_n_bits = curve->num_n_bits; + + /* Make sure 0 < k < curve_n */ + if (uECC_vli_isZero(k, num_words) || uECC_vli_cmp(curve->n, k, num_n_words) != 1) { + return 0; + } + + carry = regularize_k(k, tmp, s, curve); + EccPoint_mult(p, curve->G, k2[!carry], 0, num_n_bits + 1, curve); + if (uECC_vli_isZero(p, num_words)) { + return 0; + } + + /* If an RNG function was specified, get a random number + to prevent side channel analysis of k. */ + if (!g_rng_function) { + uECC_vli_clear(tmp, num_n_words); + tmp[0] = 1; + } else if (!uECC_generate_random_int(tmp, curve->n, num_n_words)) { + return 0; + } + + /* Prevent side channel analysis of uECC_vli_modInv() to determine + bits of k / the private key by premultiplying by a random number */ + uECC_vli_modMult(k, k, tmp, curve->n, num_n_words); /* k' = rand * k */ + uECC_vli_modInv(k, k, curve->n, num_n_words); /* k = 1 / k' */ + uECC_vli_modMult(k, k, tmp, curve->n, num_n_words); /* k = 1 / k */ + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN == 0 + uECC_vli_nativeToBytes(signature, curve->num_bytes, p); /* store r */ +#endif + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy((uint8_t *) tmp, private_key, BITS_TO_BYTES(curve->num_n_bits)); +#else + uECC_vli_bytesToNative(tmp, private_key, BITS_TO_BYTES(curve->num_n_bits)); /* tmp = d */ +#endif + + s[num_n_words - 1] = 0; + uECC_vli_set(s, p, num_words); + uECC_vli_modMult(s, tmp, s, curve->n, num_n_words); /* s = r*d */ + + bits2int(tmp, message_hash, hash_size, curve); + uECC_vli_modAdd(s, tmp, s, curve->n, num_n_words); /* s = e + r*d */ + uECC_vli_modMult(s, s, k, curve->n, num_n_words); /* s = (e + r*d) / k */ + if (uECC_vli_numBits(s, num_n_words) > (bitcount_t)curve->num_bytes * 8) { + return 0; + } +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy((uint8_t *) signature + curve->num_bytes, (uint8_t *) s, curve->num_bytes); +#else + uECC_vli_nativeToBytes(signature + curve->num_bytes, curve->num_bytes, s); +#endif + return 1; +} + +int uECC_sign(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + uint8_t *signature, + uECC_Curve curve) { + uECC_word_t k[uECC_MAX_WORDS]; + uECC_word_t tries; + + for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) { + if (!uECC_generate_random_int(k, curve->n, BITS_TO_WORDS(curve->num_n_bits))) { + return 0; + } + + if (uECC_sign_with_k(private_key, message_hash, hash_size, k, signature, curve)) { + return 1; + } + } + return 0; +} + +/* Compute an HMAC using K as a key (as in RFC 6979). Note that K is always + the same size as the hash result size. */ +static void HMAC_init(const uECC_HashContext *hash_context, const uint8_t *K) { + uint8_t *pad = hash_context->tmp + 2 * hash_context->result_size; + unsigned i; + for (i = 0; i < hash_context->result_size; ++i) + pad[i] = K[i] ^ 0x36; + for (; i < hash_context->block_size; ++i) + pad[i] = 0x36; + + hash_context->init_hash(hash_context); + hash_context->update_hash(hash_context, pad, hash_context->block_size); +} + +static void HMAC_update(const uECC_HashContext *hash_context, + const uint8_t *message, + unsigned message_size) { + hash_context->update_hash(hash_context, message, message_size); +} + +static void HMAC_finish(const uECC_HashContext *hash_context, + const uint8_t *K, + uint8_t *result) { + uint8_t *pad = hash_context->tmp + 2 * hash_context->result_size; + unsigned i; + for (i = 0; i < hash_context->result_size; ++i) + pad[i] = K[i] ^ 0x5c; + for (; i < hash_context->block_size; ++i) + pad[i] = 0x5c; + + hash_context->finish_hash(hash_context, result); + + hash_context->init_hash(hash_context); + hash_context->update_hash(hash_context, pad, hash_context->block_size); + hash_context->update_hash(hash_context, result, hash_context->result_size); + hash_context->finish_hash(hash_context, result); +} + +/* V = HMAC_K(V) */ +static void update_V(const uECC_HashContext *hash_context, uint8_t *K, uint8_t *V) { + HMAC_init(hash_context, K); + HMAC_update(hash_context, V, hash_context->result_size); + HMAC_finish(hash_context, K, V); +} + +/* Deterministic signing, similar to RFC 6979. Differences are: + * We just use H(m) directly rather than bits2octets(H(m)) + (it is not reduced modulo curve_n). + * We generate a value for k (aka T) directly rather than converting endianness. + + Layout of hash_context->tmp: | | (1 byte overlapped 0x00 or 0x01) / */ +int uECC_sign_deterministic(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + const uECC_HashContext *hash_context, + uint8_t *signature, + uECC_Curve curve) { + uint8_t *K = hash_context->tmp; + uint8_t *V = K + hash_context->result_size; + wordcount_t num_bytes = curve->num_bytes; + wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits); + bitcount_t num_n_bits = curve->num_n_bits; + uECC_word_t tries; + unsigned i; + for (i = 0; i < hash_context->result_size; ++i) { + V[i] = 0x01; + K[i] = 0; + } + + /* K = HMAC_K(V || 0x00 || int2octets(x) || h(m)) */ + HMAC_init(hash_context, K); + V[hash_context->result_size] = 0x00; + HMAC_update(hash_context, V, hash_context->result_size + 1); + HMAC_update(hash_context, private_key, num_bytes); + HMAC_update(hash_context, message_hash, hash_size); + HMAC_finish(hash_context, K, K); + + update_V(hash_context, K, V); + + /* K = HMAC_K(V || 0x01 || int2octets(x) || h(m)) */ + HMAC_init(hash_context, K); + V[hash_context->result_size] = 0x01; + HMAC_update(hash_context, V, hash_context->result_size + 1); + HMAC_update(hash_context, private_key, num_bytes); + HMAC_update(hash_context, message_hash, hash_size); + HMAC_finish(hash_context, K, K); + + update_V(hash_context, K, V); + + for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) { + uECC_word_t T[uECC_MAX_WORDS]; + uint8_t *T_ptr = (uint8_t *)T; + wordcount_t T_bytes = 0; + for (;;) { + update_V(hash_context, K, V); + for (i = 0; i < hash_context->result_size; ++i) { + T_ptr[T_bytes++] = V[i]; + if (T_bytes >= num_n_words * uECC_WORD_SIZE) { + goto filled; + } + } + } + filled: + if ((bitcount_t)num_n_words * uECC_WORD_SIZE * 8 > num_n_bits) { + uECC_word_t mask = (uECC_word_t)-1; + T[num_n_words - 1] &= + mask >> ((bitcount_t)(num_n_words * uECC_WORD_SIZE * 8 - num_n_bits)); + } + + if (uECC_sign_with_k(private_key, message_hash, hash_size, T, signature, curve)) { + return 1; + } + + /* K = HMAC_K(V || 0x00) */ + HMAC_init(hash_context, K); + V[hash_context->result_size] = 0x00; + HMAC_update(hash_context, V, hash_context->result_size + 1); + HMAC_finish(hash_context, K, K); + + update_V(hash_context, K, V); + } + return 0; +} + +static bitcount_t smax(bitcount_t a, bitcount_t b) { + return (a > b ? a : b); +} + +int uECC_verify(const uint8_t *public_key, + const uint8_t *message_hash, + unsigned hash_size, + const uint8_t *signature, + uECC_Curve curve) { + uECC_word_t u1[uECC_MAX_WORDS], u2[uECC_MAX_WORDS]; + uECC_word_t z[uECC_MAX_WORDS]; + uECC_word_t sum[uECC_MAX_WORDS * 2]; + uECC_word_t rx[uECC_MAX_WORDS]; + uECC_word_t ry[uECC_MAX_WORDS]; + uECC_word_t tx[uECC_MAX_WORDS]; + uECC_word_t ty[uECC_MAX_WORDS]; + uECC_word_t tz[uECC_MAX_WORDS]; + const uECC_word_t *points[4]; + const uECC_word_t *point; + bitcount_t num_bits; + bitcount_t i; +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + uECC_word_t *_public = (uECC_word_t *)public_key; +#else + uECC_word_t _public[uECC_MAX_WORDS * 2]; +#endif + uECC_word_t r[uECC_MAX_WORDS], s[uECC_MAX_WORDS]; + wordcount_t num_words = curve->num_words; + wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits); + + rx[num_n_words - 1] = 0; + r[num_n_words - 1] = 0; + s[num_n_words - 1] = 0; + +#if uECC_VLI_NATIVE_LITTLE_ENDIAN + bcopy((uint8_t *) r, signature, curve->num_bytes); + bcopy((uint8_t *) s, signature + curve->num_bytes, curve->num_bytes); +#else + uECC_vli_bytesToNative(_public, public_key, curve->num_bytes); + uECC_vli_bytesToNative( + _public + num_words, public_key + curve->num_bytes, curve->num_bytes); + uECC_vli_bytesToNative(r, signature, curve->num_bytes); + uECC_vli_bytesToNative(s, signature + curve->num_bytes, curve->num_bytes); +#endif + + /* r, s must not be 0. */ + if (uECC_vli_isZero(r, num_words) || uECC_vli_isZero(s, num_words)) { + return 0; + } + + /* r, s must be < n. */ + if (uECC_vli_cmp_unsafe(curve->n, r, num_n_words) != 1 || + uECC_vli_cmp_unsafe(curve->n, s, num_n_words) != 1) { + return 0; + } + + /* Calculate u1 and u2. */ + uECC_vli_modInv(z, s, curve->n, num_n_words); /* z = 1/s */ + u1[num_n_words - 1] = 0; + bits2int(u1, message_hash, hash_size, curve); + uECC_vli_modMult(u1, u1, z, curve->n, num_n_words); /* u1 = e/s */ + uECC_vli_modMult(u2, r, z, curve->n, num_n_words); /* u2 = r/s */ + + /* Calculate sum = G + Q. */ + uECC_vli_set(sum, _public, num_words); + uECC_vli_set(sum + num_words, _public + num_words, num_words); + uECC_vli_set(tx, curve->G, num_words); + uECC_vli_set(ty, curve->G + num_words, num_words); + uECC_vli_modSub(z, sum, tx, curve->p, num_words); /* z = x2 - x1 */ + XYcZ_add(tx, ty, sum, sum + num_words, curve); + uECC_vli_modInv(z, z, curve->p, num_words); /* z = 1/z */ + apply_z(sum, sum + num_words, z, curve); + + /* Use Shamir's trick to calculate u1*G + u2*Q */ + points[0] = 0; + points[1] = curve->G; + points[2] = _public; + points[3] = sum; + num_bits = smax(uECC_vli_numBits(u1, num_n_words), + uECC_vli_numBits(u2, num_n_words)); + + point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) | + ((!!uECC_vli_testBit(u2, num_bits - 1)) << 1)]; + uECC_vli_set(rx, point, num_words); + uECC_vli_set(ry, point + num_words, num_words); + uECC_vli_clear(z, num_words); + z[0] = 1; + + for (i = num_bits - 2; i >= 0; --i) { + uECC_word_t index; + curve->double_jacobian(rx, ry, z, curve); + + index = (!!uECC_vli_testBit(u1, i)) | ((!!uECC_vli_testBit(u2, i)) << 1); + point = points[index]; + if (point) { + uECC_vli_set(tx, point, num_words); + uECC_vli_set(ty, point + num_words, num_words); + apply_z(tx, ty, z, curve); + uECC_vli_modSub(tz, rx, tx, curve->p, num_words); /* Z = x2 - x1 */ + XYcZ_add(tx, ty, rx, ry, curve); + uECC_vli_modMult_fast(z, z, tz, curve); + } + } + + uECC_vli_modInv(z, z, curve->p, num_words); /* Z = 1/Z */ + apply_z(rx, ry, z, curve); + + /* v = x1 (mod n) */ + if (uECC_vli_cmp_unsafe(curve->n, rx, num_n_words) != 1) { + uECC_vli_sub(rx, rx, curve->n, num_n_words); + } + + /* Accept only if v == r. */ + return (int)(uECC_vli_equal(rx, r, num_words)); +} + +#if uECC_ENABLE_VLI_API + +unsigned uECC_curve_num_words(uECC_Curve curve) { + return curve->num_words; +} + +unsigned uECC_curve_num_bytes(uECC_Curve curve) { + return curve->num_bytes; +} + +unsigned uECC_curve_num_bits(uECC_Curve curve) { + return curve->num_bytes * 8; +} + +unsigned uECC_curve_num_n_words(uECC_Curve curve) { + return BITS_TO_WORDS(curve->num_n_bits); +} + +unsigned uECC_curve_num_n_bytes(uECC_Curve curve) { + return BITS_TO_BYTES(curve->num_n_bits); +} + +unsigned uECC_curve_num_n_bits(uECC_Curve curve) { + return curve->num_n_bits; +} + +const uECC_word_t *uECC_curve_p(uECC_Curve curve) { + return curve->p; +} + +const uECC_word_t *uECC_curve_n(uECC_Curve curve) { + return curve->n; +} + +const uECC_word_t *uECC_curve_G(uECC_Curve curve) { + return curve->G; +} + +const uECC_word_t *uECC_curve_b(uECC_Curve curve) { + return curve->b; +} + +#if uECC_SUPPORT_COMPRESSED_POINT +void uECC_vli_mod_sqrt(uECC_word_t *a, uECC_Curve curve) { + curve->mod_sqrt(a, curve); +} +#endif + +void uECC_vli_mmod_fast(uECC_word_t *result, uECC_word_t *product, uECC_Curve curve) { +#if (uECC_OPTIMIZATION_LEVEL > 0) + curve->mmod_fast(result, product); +#else + uECC_vli_mmod(result, product, curve->p, curve->num_words); +#endif +} + +void uECC_point_mult(uECC_word_t *result, + const uECC_word_t *point, + const uECC_word_t *scalar, + uECC_Curve curve) { + uECC_word_t tmp1[uECC_MAX_WORDS]; + uECC_word_t tmp2[uECC_MAX_WORDS]; + uECC_word_t *p2[2] = {tmp1, tmp2}; + uECC_word_t carry = regularize_k(scalar, tmp1, tmp2, curve); + + EccPoint_mult(result, point, p2[!carry], 0, curve->num_n_bits + 1, curve); +} + +#endif /* uECC_ENABLE_VLI_API */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC.h new file mode 100644 index 0000000000..141b4a7a9c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC.h @@ -0,0 +1,364 @@ +/* Copyright 2014, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_H_ +#define _UECC_H_ + +#include + +/* Platform selection options. +If uECC_PLATFORM is not defined, the code will try to guess it based on compiler macros. +Possible values for uECC_PLATFORM are defined below: */ +#define uECC_arch_other 0 +#define uECC_x86 1 +#define uECC_x86_64 2 +#define uECC_arm 3 +#define uECC_arm_thumb 4 +#define uECC_arm_thumb2 5 +#define uECC_arm64 6 +#define uECC_avr 7 + +//#define uECC_PLATFORM uECC_arm_thumb2 + +/* If desired, you can define uECC_WORD_SIZE as appropriate for your platform (1, 4, or 8 bytes). +If uECC_WORD_SIZE is not explicitly defined then it will be automatically set based on your +platform. */ + +/* Optimization level; trade speed for code size. + Larger values produce code that is faster but larger. + Currently supported values are 0 - 4; 0 is unusably slow for most applications. + Optimization level 4 currently only has an effect ARM platforms where more than one + curve is enabled. */ +#ifndef uECC_OPTIMIZATION_LEVEL + #define uECC_OPTIMIZATION_LEVEL 2 +#endif + +/* uECC_SQUARE_FUNC - If enabled (defined as nonzero), this will cause a specific function to be +used for (scalar) squaring instead of the generic multiplication function. This can make things +faster somewhat faster, but increases the code size. */ +#ifndef uECC_SQUARE_FUNC + #define uECC_SQUARE_FUNC 1 +#endif + +/* uECC_VLI_NATIVE_LITTLE_ENDIAN - If enabled (defined as nonzero), this will switch to native +little-endian format for *all* arrays passed in and out of the public API. This includes public +and private keys, shared secrets, signatures and message hashes. +Using this switch reduces the amount of call stack memory used by uECC, since less intermediate +translations are required. +Note that this will *only* work on native little-endian processors and it will treat the uint8_t +arrays passed into the public API as word arrays, therefore requiring the provided byte arrays +to be word aligned on architectures that do not support unaligned accesses. */ +#ifndef uECC_VLI_NATIVE_LITTLE_ENDIAN + #define uECC_VLI_NATIVE_LITTLE_ENDIAN 0 +#endif + +/* Curve support selection. Set to 0 to remove that curve. */ +#ifndef uECC_SUPPORTS_secp160r1 + #define uECC_SUPPORTS_secp160r1 0 +#endif +#ifndef uECC_SUPPORTS_secp192r1 + #define uECC_SUPPORTS_secp192r1 1 +#endif +#ifndef uECC_SUPPORTS_secp224r1 + #define uECC_SUPPORTS_secp224r1 0 +#endif +#ifndef uECC_SUPPORTS_secp256r1 + #define uECC_SUPPORTS_secp256r1 0 +#endif +#ifndef uECC_SUPPORTS_secp256k1 + #define uECC_SUPPORTS_secp256k1 0 +#endif + +/* Specifies whether compressed point format is supported. + Set to 0 to disable point compression/decompression functions. */ +#ifndef uECC_SUPPORT_COMPRESSED_POINT + #define uECC_SUPPORT_COMPRESSED_POINT 1 +#endif + +struct uECC_Curve_t; +typedef const struct uECC_Curve_t * uECC_Curve; + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if uECC_SUPPORTS_secp160r1 +uECC_Curve uECC_secp160r1(void); +#endif +#if uECC_SUPPORTS_secp192r1 +uECC_Curve uECC_secp192r1(void); +#endif +#if uECC_SUPPORTS_secp224r1 +uECC_Curve uECC_secp224r1(void); +#endif +#if uECC_SUPPORTS_secp256r1 +uECC_Curve uECC_secp256r1(void); +#endif +#if uECC_SUPPORTS_secp256k1 +uECC_Curve uECC_secp256k1(void); +#endif + +/* uECC_RNG_Function type +The RNG function should fill 'size' random bytes into 'dest'. It should return 1 if +'dest' was filled with random data, or 0 if the random data could not be generated. +The filled-in values should be either truly random, or from a cryptographically-secure PRNG. + +A correctly functioning RNG function must be set (using uECC_set_rng()) before calling +uECC_make_key() or uECC_sign(). + +Setting a correctly functioning RNG function improves the resistance to side-channel attacks +for uECC_shared_secret() and uECC_sign_deterministic(). + +A correct RNG function is set by default when building for Windows, Linux, or OS X. +If you are building on another POSIX-compliant system that supports /dev/random or /dev/urandom, +you can define uECC_POSIX to use the predefined RNG. For embedded platforms there is no predefined +RNG function; you must provide your own. +*/ +typedef int (*uECC_RNG_Function)(uint8_t *dest, unsigned size); + +/* uECC_set_rng() function. +Set the function that will be used to generate random bytes. The RNG function should +return 1 if the random data was generated, or 0 if the random data could not be generated. + +On platforms where there is no predefined RNG function (eg embedded platforms), this must +be called before uECC_make_key() or uECC_sign() are used. + +Inputs: + rng_function - The function that will be used to generate random bytes. +*/ +void uECC_set_rng(uECC_RNG_Function rng_function); + +/* uECC_get_rng() function. + +Returns the function that will be used to generate random bytes. +*/ +uECC_RNG_Function uECC_get_rng(void); + +/* uECC_curve_private_key_size() function. + +Returns the size of a private key for the curve in bytes. +*/ +int uECC_curve_private_key_size(uECC_Curve curve); + +/* uECC_curve_public_key_size() function. + +Returns the size of a public key for the curve in bytes. +*/ +int uECC_curve_public_key_size(uECC_Curve curve); + +/* uECC_make_key() function. +Create a public/private key pair. + +Outputs: + public_key - Will be filled in with the public key. Must be at least 2 * the curve size + (in bytes) long. For example, if the curve is secp256r1, public_key must be 64 + bytes long. + private_key - Will be filled in with the private key. Must be as long as the curve order; this + is typically the same as the curve size, except for secp160r1. For example, if the + curve is secp256r1, private_key must be 32 bytes long. + + For secp160r1, private_key must be 21 bytes long! Note that the first byte will + almost always be 0 (there is about a 1 in 2^80 chance of it being non-zero). + +Returns 1 if the key pair was generated successfully, 0 if an error occurred. +*/ +int uECC_make_key(uint8_t *public_key, uint8_t *private_key, uECC_Curve curve); + +/* uECC_shared_secret() function. +Compute a shared secret given your secret key and someone else's public key. +Note: It is recommended that you hash the result of uECC_shared_secret() before using it for +symmetric encryption or HMAC. + +Inputs: + public_key - The public key of the remote party. + private_key - Your private key. + +Outputs: + secret - Will be filled in with the shared secret value. Must be the same size as the + curve size; for example, if the curve is secp256r1, secret must be 32 bytes long. + +Returns 1 if the shared secret was generated successfully, 0 if an error occurred. +*/ +int uECC_shared_secret(const uint8_t *public_key, + const uint8_t *private_key, + uint8_t *secret, + uECC_Curve curve); + +#if uECC_SUPPORT_COMPRESSED_POINT +/* uECC_compress() function. +Compress a public key. + +Inputs: + public_key - The public key to compress. + +Outputs: + compressed - Will be filled in with the compressed public key. Must be at least + (curve size + 1) bytes long; for example, if the curve is secp256r1, + compressed must be 33 bytes long. +*/ +void uECC_compress(const uint8_t *public_key, uint8_t *compressed, uECC_Curve curve); + +/* uECC_decompress() function. +Decompress a compressed public key. + +Inputs: + compressed - The compressed public key. + +Outputs: + public_key - Will be filled in with the decompressed public key. +*/ +void uECC_decompress(const uint8_t *compressed, uint8_t *public_key, uECC_Curve curve); +#endif /* uECC_SUPPORT_COMPRESSED_POINT */ + +/* uECC_valid_public_key() function. +Check to see if a public key is valid. + +Note that you are not required to check for a valid public key before using any other uECC +functions. However, you may wish to avoid spending CPU time computing a shared secret or +verifying a signature using an invalid public key. + +Inputs: + public_key - The public key to check. + +Returns 1 if the public key is valid, 0 if it is invalid. +*/ +int uECC_valid_public_key(const uint8_t *public_key, uECC_Curve curve); + +/* uECC_compute_public_key() function. +Compute the corresponding public key for a private key. + +Inputs: + private_key - The private key to compute the public key for + +Outputs: + public_key - Will be filled in with the corresponding public key + +Returns 1 if the key was computed successfully, 0 if an error occurred. +*/ +int uECC_compute_public_key(const uint8_t *private_key, uint8_t *public_key, uECC_Curve curve); + +/* uECC_sign() function. +Generate an ECDSA signature for a given hash value. + +Usage: Compute a hash of the data you wish to sign (SHA-2 is recommended) and pass it in to +this function along with your private key. + +Inputs: + private_key - Your private key. + message_hash - The hash of the message to sign. + hash_size - The size of message_hash in bytes. + +Outputs: + signature - Will be filled in with the signature value. Must be at least 2 * curve size long. + For example, if the curve is secp256r1, signature must be 64 bytes long. + +Returns 1 if the signature generated successfully, 0 if an error occurred. +*/ +int uECC_sign(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + uint8_t *signature, + uECC_Curve curve); + +/* uECC_HashContext structure. +This is used to pass in an arbitrary hash function to uECC_sign_deterministic(). +The structure will be used for multiple hash computations; each time a new hash +is computed, init_hash() will be called, followed by one or more calls to +update_hash(), and finally a call to finish_hash() to produce the resulting hash. + +The intention is that you will create a structure that includes uECC_HashContext +followed by any hash-specific data. For example: + +typedef struct SHA256_HashContext { + uECC_HashContext uECC; + SHA256_CTX ctx; +} SHA256_HashContext; + +void init_SHA256(uECC_HashContext *base) { + SHA256_HashContext *context = (SHA256_HashContext *)base; + SHA256_Init(&context->ctx); +} + +void update_SHA256(uECC_HashContext *base, + const uint8_t *message, + unsigned message_size) { + SHA256_HashContext *context = (SHA256_HashContext *)base; + SHA256_Update(&context->ctx, message, message_size); +} + +void finish_SHA256(uECC_HashContext *base, uint8_t *hash_result) { + SHA256_HashContext *context = (SHA256_HashContext *)base; + SHA256_Final(hash_result, &context->ctx); +} + +... when signing ... +{ + uint8_t tmp[32 + 32 + 64]; + SHA256_HashContext ctx = {{&init_SHA256, &update_SHA256, &finish_SHA256, 64, 32, tmp}}; + uECC_sign_deterministic(key, message_hash, &ctx.uECC, signature); +} +*/ +typedef struct uECC_HashContext { + void (*init_hash)(const struct uECC_HashContext *context); + void (*update_hash)(const struct uECC_HashContext *context, + const uint8_t *message, + unsigned message_size); + void (*finish_hash)(const struct uECC_HashContext *context, uint8_t *hash_result); + unsigned block_size; /* Hash function block size in bytes, eg 64 for SHA-256. */ + unsigned result_size; /* Hash function result size in bytes, eg 32 for SHA-256. */ + uint8_t *tmp; /* Must point to a buffer of at least (2 * result_size + block_size) bytes. */ +} uECC_HashContext; + +/* uECC_sign_deterministic() function. +Generate an ECDSA signature for a given hash value, using a deterministic algorithm +(see RFC 6979). You do not need to set the RNG using uECC_set_rng() before calling +this function; however, if the RNG is defined it will improve resistance to side-channel +attacks. + +Usage: Compute a hash of the data you wish to sign (SHA-2 is recommended) and pass it to +this function along with your private key and a hash context. Note that the message_hash +does not need to be computed with the same hash function used by hash_context. + +Inputs: + private_key - Your private key. + message_hash - The hash of the message to sign. + hash_size - The size of message_hash in bytes. + hash_context - A hash context to use. + +Outputs: + signature - Will be filled in with the signature value. + +Returns 1 if the signature generated successfully, 0 if an error occurred. +*/ +int uECC_sign_deterministic(const uint8_t *private_key, + const uint8_t *message_hash, + unsigned hash_size, + const uECC_HashContext *hash_context, + uint8_t *signature, + uECC_Curve curve); + +/* uECC_verify() function. +Verify an ECDSA signature. + +Usage: Compute the hash of the signed data using the same hash as the signer and +pass it to this function along with the signer's public key and the signature values (r and s). + +Inputs: + public_key - The signer's public key. + message_hash - The hash of the signed data. + hash_size - The size of message_hash in bytes. + signature - The signature value. + +Returns 1 if the signature is valid, 0 if it is invalid. +*/ +int uECC_verify(const uint8_t *public_key, + const uint8_t *message_hash, + unsigned hash_size, + const uint8_t *signature, + uECC_Curve curve); + +#ifdef __cplusplus +} /* end of extern "C" */ +#endif + +#endif /* _UECC_H_ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC_vli.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC_vli.h new file mode 100644 index 0000000000..b771deec53 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/uECC_vli.h @@ -0,0 +1,173 @@ + +/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */ + +#ifndef _UECC_VLI_H_ +#define _UECC_VLI_H_ + +#include "uECC.h" +#include "types.h" + +/* Functions for raw large-integer manipulation. These are only available + if uECC.c is compiled with uECC_ENABLE_VLI_API defined to 1. */ +#ifndef uECC_ENABLE_VLI_API + #define uECC_ENABLE_VLI_API 0 +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if uECC_ENABLE_VLI_API + +void uECC_vli_clear(uECC_word_t *vli, wordcount_t num_words); + +/* Constant-time comparison to zero - secure way to compare long integers */ +/* Returns 1 if vli == 0, 0 otherwise. */ +uECC_word_t uECC_vli_isZero(const uECC_word_t *vli, wordcount_t num_words); + +/* Returns nonzero if bit 'bit' of vli is set. */ +uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit); + +/* Counts the number of bits required to represent vli. */ +bitcount_t uECC_vli_numBits(const uECC_word_t *vli, const wordcount_t max_words); + +/* Sets dest = src. */ +void uECC_vli_set(uECC_word_t *dest, const uECC_word_t *src, wordcount_t num_words); + +/* Constant-time comparison function - secure way to compare long integers */ +/* Returns one if left == right, zero otherwise */ +uECC_word_t uECC_vli_equal(const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Constant-time comparison function - secure way to compare long integers */ +/* Returns sign of left - right, in constant time. */ +cmpresult_t uECC_vli_cmp(const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words); + +/* Computes vli = vli >> 1. */ +void uECC_vli_rshift1(uECC_word_t *vli, wordcount_t num_words); + +/* Computes result = left + right, returning carry. Can modify in place. */ +uECC_word_t uECC_vli_add(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Computes result = left - right, returning borrow. Can modify in place. */ +uECC_word_t uECC_vli_sub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Computes result = left * right. Result must be 2 * num_words long. */ +void uECC_vli_mult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + wordcount_t num_words); + +/* Computes result = left^2. Result must be 2 * num_words long. */ +void uECC_vli_square(uECC_word_t *result, const uECC_word_t *left, wordcount_t num_words); + +/* Computes result = (left + right) % mod. + Assumes that left < mod and right < mod, and that result does not overlap mod. */ +void uECC_vli_modAdd(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = (left - right) % mod. + Assumes that left < mod and right < mod, and that result does not overlap mod. */ +void uECC_vli_modSub(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = product % mod, where product is 2N words long. + Currently only designed to work for mod == curve->p or curve_n. */ +void uECC_vli_mmod(uECC_word_t *result, + uECC_word_t *product, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Calculates result = product (mod curve->p), where product is up to + 2 * curve->num_words long. */ +void uECC_vli_mmod_fast(uECC_word_t *result, uECC_word_t *product, uECC_Curve curve); + +/* Computes result = (left * right) % mod. + Currently only designed to work for mod == curve->p or curve_n. */ +void uECC_vli_modMult(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = (left * right) % curve->p. */ +void uECC_vli_modMult_fast(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *right, + uECC_Curve curve); + +/* Computes result = left^2 % mod. + Currently only designed to work for mod == curve->p or curve_n. */ +void uECC_vli_modSquare(uECC_word_t *result, + const uECC_word_t *left, + const uECC_word_t *mod, + wordcount_t num_words); + +/* Computes result = left^2 % curve->p. */ +void uECC_vli_modSquare_fast(uECC_word_t *result, const uECC_word_t *left, uECC_Curve curve); + +/* Computes result = (1 / input) % mod.*/ +void uECC_vli_modInv(uECC_word_t *result, + const uECC_word_t *input, + const uECC_word_t *mod, + wordcount_t num_words); + +#if uECC_SUPPORT_COMPRESSED_POINT +/* Calculates a = sqrt(a) (mod curve->p) */ +void uECC_vli_mod_sqrt(uECC_word_t *a, uECC_Curve curve); +#endif + +/* Converts an integer in uECC native format to big-endian bytes. */ +void uECC_vli_nativeToBytes(uint8_t *bytes, int num_bytes, const uECC_word_t *native); +/* Converts big-endian bytes to an integer in uECC native format. */ +void uECC_vli_bytesToNative(uECC_word_t *native, const uint8_t *bytes, int num_bytes); + +unsigned uECC_curve_num_words(uECC_Curve curve); +unsigned uECC_curve_num_bytes(uECC_Curve curve); +unsigned uECC_curve_num_bits(uECC_Curve curve); +unsigned uECC_curve_num_n_words(uECC_Curve curve); +unsigned uECC_curve_num_n_bytes(uECC_Curve curve); +unsigned uECC_curve_num_n_bits(uECC_Curve curve); + +const uECC_word_t *uECC_curve_p(uECC_Curve curve); +const uECC_word_t *uECC_curve_n(uECC_Curve curve); +const uECC_word_t *uECC_curve_G(uECC_Curve curve); +const uECC_word_t *uECC_curve_b(uECC_Curve curve); + +int uECC_valid_point(const uECC_word_t *point, uECC_Curve curve); + +/* Multiplies a point by a scalar. Points are represented by the X coordinate followed by + the Y coordinate in the same array, both coordinates are curve->num_words long. Note + that scalar must be curve->num_n_words long (NOT curve->num_words). */ +void uECC_point_mult(uECC_word_t *result, + const uECC_word_t *point, + const uECC_word_t *scalar, + uECC_Curve curve); + +/* Generates a random integer in the range 0 < random < top. + Both random and top have num_words words. */ +int uECC_generate_random_int(uECC_word_t *random, + const uECC_word_t *top, + wordcount_t num_words); + +#endif /* uECC_ENABLE_VLI_API */ + +#ifdef __cplusplus +} /* end of extern "C" */ +#endif + +#endif /* _UECC_VLI_H_ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/v_stdio.c new file mode 100644 index 0000000000..77fd069bcf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/CRYPT/CRYPT_ECC256Signatures/Src/v_stdio.c @@ -0,0 +1,38 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +/** + * @brief fputc. + * @param None + * @retval None + */ +int fputc(int ch, FILE *f) +{ + //while (UART5->STATE&UART_STATE_TXFULL); + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.ewd @@ -0,0 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+ + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM 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+ + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..e312423b12 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..d969191a6c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 79 + 79 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/main.c new file mode 100644 index 0000000000..6f8d34ae86 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/main.c @@ -0,0 +1,104 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +#define OUT_IOB13 (BIT_BAND((uint32_t)&GPIOB->DAT, 13)) +#define SET_IOB13 (BIT_BAND((uint32_t)&GPIOB->DAT, 13) = 1) +#define CLR_IOB13 (BIT_BAND((uint32_t)&GPIOB->DAT, 13) = 0) + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* IOA13 CMOS output mode */ + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_13; + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + test_success = 1; + + WDT_Disable(); + /* Toggle IOB13 with bit-band address */ + while (1) + { + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + SET_IOB13; CLR_IOB13; + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/target_isr.c new file mode 100644 index 0000000000..93adc10d40 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/target_isr.c @@ -0,0 +1,305 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Cortex/BitBand/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/target_flash.icf new file mode 100644 index 0000000000..1de5979f36 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 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b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9c449e2afe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..6428304864 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 152 + 152 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 39 + 0 + 200 + 220 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/main.c new file mode 100644 index 0000000000..f0baaa3955 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/main.c @@ -0,0 +1,176 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + DMA_InitType DMA_InitStruct; + DMA_AESInitType AESInitStruct; + uint32_t i; + uint8_t dst[16]; + uint8_t res[16]; + +#ifdef __ICCARM__ + #pragma data_alignment=4 +#endif + uint8_t key[24] +#ifndef __ICCARM__ + __attribute__((aligned (4))) +#endif +; + +#ifdef __ICCARM__ + #pragma data_alignment=4 +#endif + uint8_t src[16] +#ifndef __ICCARM__ + __attribute__((aligned (4))) +#endif +; + + test_success = 0; + + for (i=0; i<24; i++) + key[i] = i; + + for (i=0; i<16; i++) + src[i] = 0x10*i + i; + + Clock_Init(); + Stdio_Init(); + + /* DMA channel3 initialization */ + DMA_DeInit(DMA_CHANNEL_3); + DMA_InitStruct.SrcAddr = (uint32_t)&src[0]; + DMA_InitStruct.DestAddr = (uint32_t)&dst[0]; + DMA_InitStruct.FrameLen = 0; + DMA_InitStruct.PackLen = 4 - 1; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_InitStruct.ReqSrc = DMA_REQSRC_SOFT; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FEND; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FEND; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_WORD; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_3); + + /* AES configuration, encode */ + DMA_AESDeInit(); + AESInitStruct.Direction = DMA_AESDIRECTION_ENCODE; + AESInitStruct.Mode = DMA_AESMODE_192; + AESInitStruct.KeyStr = (uint32_t *)&key[0]; + DMA_AESInit(&AESInitStruct); + + /* Enable AES and DMA channel3 */ + DMA_AESCmd(ENABLE); + DMA_Cmd(DMA_CHANNEL_3, ENABLE); + + /* Waiting channel3 operation complete */ + while (DMA_GetINTStatus(DMA_INTSTS_C3BUSY)); + printf("encode:\r\n"); + for (i = 0; i < 16; i++) + { + printf("0x%x\t", dst[i]); + } + printf("\r\n"); + + ///////////////////////////// + DMA_DeInit(DMA_CHANNEL_3); + DMA_InitStruct.SrcAddr = (uint32_t)&dst[0]; + DMA_InitStruct.DestAddr = (uint32_t)&res[0]; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_3); + + /* AES configuration, decode */ + DMA_AESDeInit(); + AESInitStruct.Direction = DMA_AESDIRECTION_DECODE; + AESInitStruct.KeyStr = (uint32_t *)&key[0]; + DMA_AESInit(&AESInitStruct); + + /* Enable AES and DMA channel3 */ + DMA_AESCmd(ENABLE); + DMA_Cmd(DMA_CHANNEL_3, ENABLE); + + /* Waiting channel3 operation complete */ + while (DMA_GetINTStatus(DMA_INTSTS_C3BUSY)); + printf("decode:\r\n"); + for (i = 0; i < 16; i++) + { + printf("0x%x\t", res[i]); + } + printf("\r\n"); + + /* Resource release */ + DMA_DeInit(DMA_CHANNEL_3); + DMA_AESDeInit(); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_AES/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.ewd @@ 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/main.h new file mode 100644 index 0000000000..41292f40cb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/main.h @@ -0,0 +1,30 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +extern __IO uint32_t flag_dmaerr; /* Set to 1 if an error transfer is detected */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..6dea49db7e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/template.uvoptx @@ -0,0 +1,682 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 102 + 1 +
4954
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\main.c + + \\template\../Src/main.c\102 + + + 1 + 0 + 111 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\main.c + + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + Src_Const_Buffer + + + 2 + 1 + Dst_Buffer + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..b6122b65b5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 118 + 118 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/main.c new file mode 100644 index 0000000000..ea42bce845 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/main.c @@ -0,0 +1,152 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +#define Buffer_Size (16) + +const uint32_t Src_Const_Buffer[Buffer_Size] = +{ + 0x00000000, 0x11111111, 0x22222222, 0x33333333, + 0x44444444, 0x55555555, 0x66666666, 0x77777777, + 0x88888888, 0x99999999, 0xAAAAAAAA, 0xBBBBBBBB, + 0xCCCCCCCC, 0xDDDDDDDD, 0xEEEEEEEE, 0xFFFFFFFF +}; + +uint32_t Dst_Buffer[Buffer_Size] = { 0 }; + +__IO uint32_t flag_dmaerr; /* Set to 1 if an error transfer is detected */ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + DMA_InitType DMA_InitStruct; + uint32_t i; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* DMA channel0 initialization */ + DMA_DeInit(DMA_CHANNEL_0); + DMA_InitStruct.DestAddr = (uint32_t)&Dst_Buffer[0]; + DMA_InitStruct.SrcAddr = (uint32_t)&Src_Const_Buffer[0]; + DMA_InitStruct.FrameLen = 1 - 1; + DMA_InitStruct.PackLen = Buffer_Size - 1; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_InitStruct.ReqSrc = DMA_REQSRC_SOFT; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FEND; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FEND; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_WORD; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_0); + + /* Enable DMA channel0 data abort interrupt */ + DMA_INTConfig(DMA_INT_C0DA, ENABLE); + /* Enable DMA NVIC interrupt */ + CORTEX_SetPriority_ClearPending_EnableIRQ(DMA_IRQn, 0); + + flag_dmaerr = 0;/* Set to 1 if an error transfer is detected */ + /* Enable channel0, start operation */ + DMA_Cmd(DMA_CHANNEL_0, ENABLE); + + /* Waiting for operation complete */ + while (DMA_GetINTStatus(DMA_INTSTS_C0BUSY)); + + /* DMA channel0 resource release */ + DMA_DeInit(DMA_CHANNEL_0); + CORTEX_NVIC_DisableIRQ(DMA_IRQn); + + for (i=0; i<16; i++) + { + if (Dst_Buffer[i] != Src_Const_Buffer[i]) + { + printf("DMA Flash to RAM ERROR!\r\n"); + test_success = 0; + while (1) + { + WDT_Clear(); + } + } + } + + if (flag_dmaerr) + { + printf("DMA Flash to RAM ERROR!\r\n"); + test_success = 0; + } + else + { + printf("DMA Flash to RAM OK!\r\n"); + test_success = 1; + } + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/target_isr.c new file mode 100644 index 0000000000..5b682de0cf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/target_isr.c @@ -0,0 +1,308 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ + if (DMA_GetINTStatus(DMA_INTSTS_C0DA)) + { + flag_dmaerr = 1; + DMA_ClearINTStatus(DMA_INTSTS_C0DA); + } +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_FlashToRAM/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/main.h new file mode 100644 index 0000000000..4636293d9d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/main.h @@ -0,0 +1,29 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +void ISO78160_DMATransmitErrorHandle(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..1a25557706 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 132 + 132 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/main.c new file mode 100644 index 0000000000..a48135ca83 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/main.c @@ -0,0 +1,156 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +uint8_t Transmit_Buffer[8] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF }; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +void ISO78160_DMATransmitErrorHandle(void) +{ + /* Transmit error handle */ + if (ISO7816_GetINTStatus(ISO78160, ISO7816_INTSTS_TXRTYERR)) + { + ISO7816_ClearINTStatus(ISO78160, ISO7816_INTSTS_TXRTYERR); + + DMA_StopTransmit(DMA_CHANNEL_0, ENABLE); + /* Waiting DMA channel idle */ + while (DMA_GetINTStatus(DMA_INTSTS_C0BUSY)); + DMA_StopTransmit(DMA_CHANNEL_0, DISABLE); + + printf("DMA Transmit error\r\n"); + printf("DMA stop, clear busy, clear stop\r\n"); + } +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ISO7816_InitType ISO7816_InitStruct; + DMA_InitType DMA_InitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* ISO78160 initialization */ + ISO7816_DeInit(ISO78160); + ISO7816_InitStruct.FirstBit = ISO7816_FIRSTBIT_MSB; + ISO7816_InitStruct.Parity = ISO7816_PARITY_EVEN; + ISO7816_InitStruct.Baudrate = 9600; + ISO7816_InitStruct.TXRetry = ISO7816_TXRTY_0; + ISO7816_InitStruct.RXACKLength = ISO7816_RXACKLEN_2; + ISO7816_InitStruct.TXNACKLength = ISO7816_TXNACKLEN_2; + ISO7816_Init(ISO78160, &ISO7816_InitStruct); + + /* Enable ISO78160 transmit error interrupt */ + ISO7816_INTConfig(ISO78160, ISO7816_INT_TXRTYERR, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ISO78160_IRQn, 3); + + /* Channel0 initialization, Transmit_Buffer -> ISO78160->DATA*/ + DMA_DeInit(DMA_CHANNEL_0); + DMA_InitStruct.DestAddr = (uint32_t)&ISO78160->DATA; + DMA_InitStruct.SrcAddr = (uint32_t)&Transmit_Buffer[0]; + DMA_InitStruct.FrameLen = 1 - 1; + DMA_InitStruct.PackLen = 8 - 1; + DMA_InitStruct.ReqSrc = DMA_REQSRC_ISO78160TX; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_BYTE; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FIX; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FEND; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_0); + + /* Enable ISO78160 */ + ISO7816_Cmd(ISO78160, ENABLE); + /* Enable channel 0 */ + DMA_Cmd(DMA_CHANNEL_0, ENABLE); + + /* Waiting for DMA channel0 frame end */ + while (1) + { + if (DMA_GetINTStatus(DMA_INTSTS_C0FE)) + { + DMA_ClearINTStatus(DMA_INTSTS_C0FE); + break; + } + } + + /* Waiting ISO78160 transmit(via DMA channel) done */ + while (!ISO7816_GetFlag(ISO78160, ISO7816_FLAG_DMATXDONE)); + ISO7816_ClearFlag(ISO78160, ISO7816_FLAG_DMATXDONE); + + /* ISO7816/DMA resource release */ + DMA_DeInit(DMA_CHANNEL_0); + ISO7816_DeInit(ISO78160); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/target_isr.c new file mode 100644 index 0000000000..6f0690fb72 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/target_isr.c @@ -0,0 +1,306 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ + ISO78160_DMATransmitErrorHandle(); +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_ISO7816_Transmit/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..06a4d1e163 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..7763b32179 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 121 + 121 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/main.c new file mode 100644 index 0000000000..cebdef5213 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/main.c @@ -0,0 +1,145 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +#define Frame_Size (8) +#define Pack_Size (8) + +uint32_t i; +uint32_t Src_Buffer[Frame_Size*Pack_Size]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + DMA_InitType DMA_InitStruct; + TMR_InitType TMR_InitStruct; + GPIO_InitType GPIO_InitStruct; + uint32_t tmp; + + test_success = 0; + + Clock_Init(); + + /* IOB7, CMOS output mode, output low */ + GPIO_WriteBit(GPIO_B, 7, 0); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + tmp = GPIOBToF_ReadOutputData(GPIOB); + for (i=0; i<(Frame_Size*Pack_Size); i++) + { + tmp ^= GPIO_Pin_7; + Src_Buffer[i] = tmp; + } + + /* Timer1 initialization: + - Clock source: internal clock(APB clock 13107200Hz) + - Overflow interval: 10us */ + TMR_DeInit(TMR1); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 13107200/100000 - 1; + TMR_Init(TMR1, &TMR_InitStruct); + + /* DMA channel0 initialization */ + DMA_DeInit(DMA_CHANNEL_0); + DMA_InitStruct.DestAddr = (uint32_t)&GPIOB->DAT; + DMA_InitStruct.SrcAddr = (uint32_t)&Src_Buffer[0]; + DMA_InitStruct.FrameLen = Frame_Size - 1; + DMA_InitStruct.PackLen = Pack_Size - 1; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_InitStruct.ReqSrc = DMA_REQSRC_TIMER1; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FIX; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FEND; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_WORD; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_0); + + /* Enable Timer1 */ + TMR_Cmd(TMR1, ENABLE); + /* Enable DMA channel 0 */ + DMA_Cmd(DMA_CHANNEL_0, ENABLE); + + /* Waiting for operation complete */ + while (DMA_GetINTStatus(DMA_INTSTS_C0BUSY)); + + /* Resource release */ + DMA_DeInit(DMA_CHANNEL_0); + TMR_DeInit(TMR1); + /* IOB7, forbidden mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_MemoryToPeripheral_Timer/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 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lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..5766e6fe92 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 108 + 108 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/main.c new file mode 100644 index 0000000000..96156ab09d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/main.c @@ -0,0 +1,132 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +#define Buffer_Size (8) + +uint32_t i; +uint8_t Transmit_Buffer[Buffer_Size] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF }; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + SPI_InitType SPI_InitStruct; + DMA_InitType DMA_InitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* SPI1 initialization, master mode */ + SPI_DeviceInit(SPI1); + SPI_InitStruct.Mode = SPI_MODE_MASTER; + SPI_InitStruct.ClockDivision = SPI_CLKDIV_32; + SPI_InitStruct.CSNSoft = SPI_CSNSOFT_DISABLE; + SPI_InitStruct.SPH = SPI_SPH_0; + SPI_InitStruct.SPO = SPI_SPO_0; + SPI_InitStruct.SWAP = SPI_SWAP_DISABLE; + SPI_Init(SPI1, &SPI_InitStruct); + /* Enable SPI1 smart mode */ + SPI_SmartModeCmd(SPI1, ENABLE); + + /* Channel0 initialization, Transmit_Buffer -> SPI1_TXDAT */ + DMA_DeInit(DMA_CHANNEL_0); + DMA_InitStruct.DestAddr = (uint32_t)&SPI1->TXDAT; + DMA_InitStruct.SrcAddr = (uint32_t)&Transmit_Buffer[0]; + DMA_InitStruct.FrameLen = 1 - 1; + DMA_InitStruct.PackLen = Buffer_Size - 1; + DMA_InitStruct.ReqSrc = DMA_REQSRC_SPI1TX; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_BYTE; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FIX; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FEND; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_0); + + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); + /* Enable channel 0 */ + DMA_Cmd(DMA_CHANNEL_0, ENABLE); + + /* Waiting DMA channel's operation done */ + while (DMA_GetINTStatus(DMA_INTSTS_C0BUSY)); + /* Waiting SPI1 transmit(via DMA channel) done */ + while (!SPI_GetStatus(SPI1, SPI_STS_DMATXDONE)); + SPI_ClearStatus(SPI1, SPI_STS_DMATXDONE); + + /* SPI/DMA resource release */ + DMA_DeInit(DMA_CHANNEL_0); + SPI_DeviceInit(SPI1); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_SPI_Transmit/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/main.h new file mode 100644 index 0000000000..747c6ffbb0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/main.h @@ -0,0 +1,30 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +extern __IO uint32_t flag_framend; +extern __IO uint32_t flag_uarterr; + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..81057b9b77 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 129 + 129 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/main.c new file mode 100644 index 0000000000..2fbeda0606 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/main.c @@ -0,0 +1,153 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +uint8_t bsrc[] = "This is a uart5 DMA send test program!\r\n"; +__IO uint32_t flag_framend; +__IO uint32_t flag_uarterr; +__IO uint32_t delay_cycles; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + DMA_InitType DMA_InitStruct; + UART_InitType UART_InitStruct; + uint8_t tx_size; + + test_success = 0; + + Clock_Init(); + + /* UART5 initialization */ + UART_DeInit(UART5); + UART_InitStruct.Baudrate = 115200; + UART_InitStruct.FirstBit = UART_FIRSTBIT_LSB; + UART_InitStruct.Mode = UART_MODE_TX; + UART_InitStruct.Parity = UART_PARITY_NONE; + UART_Init(UART5, &UART_InitStruct); + + /* Enable UART5 transmit error interrupt(transmit overrun) */ + UART_INTConfig(UART5, UART_INT_TXOV, ENABLE); + /* Enable DMA NVIC interrupt */ + NVIC_ClearPendingIRQ(UART5_IRQn); + NVIC_EnableIRQ(UART5_IRQn); + + /* DMA channel2 initialization */ + tx_size = (sizeof(bsrc) / sizeof(bsrc[0])) - 1; + DMA_DeInit(DMA_CHANNEL_2); + DMA_InitStruct.DestAddr = (uint32_t)&UART5->DATA; + DMA_InitStruct.SrcAddr = (uint32_t)&bsrc[0]; + DMA_InitStruct.FrameLen = 1 - 1; + DMA_InitStruct.PackLen = tx_size - 1; + DMA_InitStruct.ContMode = DMA_CONTMODE_DISABLE; + DMA_InitStruct.TransMode = DMA_TRANSMODE_SINGLE; + DMA_InitStruct.ReqSrc = DMA_REQSRC_UART5TX; + DMA_InitStruct.DestAddrMode = DMA_DESTADDRMODE_FIX; + DMA_InitStruct.SrcAddrMode = DMA_SRCADDRMODE_FEND; + DMA_InitStruct.TransSize = DMA_TRANSSIZE_BYTE; + DMA_Init(&DMA_InitStruct, DMA_CHANNEL_2); + + /* Enable DMA channel2 frame end interrupt */ + DMA_INTConfig(DMA_INT_C2FE, ENABLE); + /* Enable DMA NVIC interrupt */ + NVIC_ClearPendingIRQ(DMA_IRQn); + NVIC_EnableIRQ(DMA_IRQn); + + flag_framend = 0; + flag_uarterr = 0; + DMA_Cmd(DMA_CHANNEL_2, ENABLE); + + /* Waiting for DMA channel2 frame end interrupt */ + while (flag_framend == 0); + /* Waiting for UART5 transmit(via DMA channel) complete */ + while(UART_GetFlag(UART5, UART_FLAG_DMATXDONE) == 0); + UART_ClearFlag(UART5, UART_FLAG_DMATXDONE); + + /* DMA channel2, UART5 resource release */ + DMA_DeInit(DMA_CHANNEL_2); + UART_DeInit(UART5); + NVIC_DisableIRQ(DMA_IRQn); + NVIC_DisableIRQ(UART5_IRQn); + + /* Print initialization */ + Stdio_Init(); + if (flag_uarterr) + { + printf("Send finish, transmit error!\r\n"); + test_success = 0; + } + else + { + printf("Send finish, transmit ok!\r\n"); + test_success = 1; + } + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/target_isr.c new file mode 100644 index 0000000000..507eba01f3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/target_isr.c @@ -0,0 +1,313 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ + if (UART_GetINTStatus(UART5, UART_INTSTS_TXOV)) + { + flag_uarterr = 1; + UART_ClearINTStatus(UART5, UART_INTSTS_TXOV); + } +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ + if (DMA_GetINTStatus(DMA_INTSTS_C2FE)) + { + flag_framend = 1; + DMA_ClearINTStatus(DMA_INTSTS_C2FE); + } +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/DMA/DMA_UART_TransmitIT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.ewd 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..4228ef4050 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/template.uvoptx @@ -0,0 +1,694 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U00002CB4F9A3 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 277 + 1 +
2904
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\target_isr.c + + \\template\../Src/target_isr.c\277 + + + 1 + 0 + 279 + 1 +
2910
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\target_isr.c + + \\template\../Src/target_isr.c\279 + + + 2 + 0 + 127 + 1 +
6290
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\main.c + + \\template\../Src/main.c\127 + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + System Viewer\FLASH + 35905 + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..58eed69439 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 134 + 134 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/main.c new file mode 100644 index 0000000000..bae5ee73c3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/main.c @@ -0,0 +1,158 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + uint32_t i; + uint32_t CheckSum; + uint32_t w_buffer[256]; + uint16_t hw_buffer[512]; + uint8_t b_buffer[1024]; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + + for (i=0; i<1024; i++) + { + b_buffer[i] = i % 256; + if ((i%2) == 0) + hw_buffer[i/2] = 0x1234 + i; + if ((i%4) == 0) + w_buffer[i/4] = 0x12345678 + i; + } + + FLASH_Init(FLASH_CSMODE_DISABLE); + FLASH_CycleInit(); + + FLASH_SectorErase(0x10000); //erase 0x10000~0x103FC + FLASH_ProgramByte(0x10000, b_buffer, 1024); //Byte program + for (i = 0; i < 1024; i++) + { + printf("%2x\t", *((__IO uint8_t *)(i + 0x10000))); + if ((i%10) == 9) + printf("\r\n"); + } + printf("\r\n"); + + FLASH_SectorErase(0x10000); //erase 0x10000~0x103FC + FLASH_ProgramHWord(0x10000, hw_buffer, 512); //Half-word program + for (i = 0; i < 1024; i += 2) + { + printf("%4x\t", *((__IO uint16_t *)(i + 0x10000))); + if ((i%10) == 9) + printf("\r\n"); + } + printf("\r\n"); + + FLASH_SectorErase(0x10000); //erase 0x10000~0x103FC + for (i = 0; i < 1024; i++) + { + printf("%2x\t", *((__IO uint8_t *)(i + 0x10000))); + if ((i%10) == 9) + printf("\r\n"); + } + printf("\r\n"); + + FLASH_ProgramWord(0x10000, w_buffer, 256); //Word program + for (i = 0; i < 1024; i += 4) + { +#ifdef __GNUC__ + printf("%8lx\t", *((__IO uint32_t *)(i + 0x10000))); +#else + printf("%8x\t", *((__IO uint32_t *)(i + 0x10000))); +#endif + if ((i%20) == 16) + printf("\r\n"); + } + printf("\r\n"); + + CheckSum = 0; //CheckSum 0x10000~0x103FC + for (i = 0; i < 256; i++) + { + CheckSum += w_buffer[i]; + } + + /* Enable flash(NVIC) interrupt */ + FLASH_INTConfig(FLASH_INT_CS, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(FLASH_IRQn, 0); + + FLASH_SetCheckSumCompValue(CheckSum); + FLASH_SetCheckSumRange(0x10000, 0x103FC); + FLASH_Init(FLASH_CSMODE_ALWAYSON); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/target_isr.c new file mode 100644 index 0000000000..eec38e087f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ + if (FLASH_GetINTStatus(FLASH_INT_CS)) + { + FLASH_ClearINTStatus(FLASH_INT_CS); + //Flash checksum error handling + printf("Flash checksum error\r\n"); + } +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Program/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/main.h new file mode 100644 index 0000000000..ac19a33680 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/main.h @@ -0,0 +1,29 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +void UART5_InterruptService(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..6fe5e358e9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/template.uvoptx @@ -0,0 +1,695 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U0000E6A21FAB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO31 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 65 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + \\template\../../../../Libraries/Lib_Driver/src/lib_flash.c\249 + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + + 1 + 0 + 0x0007FC00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..903d287c03 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARM/template.uvprojx @@ -0,0 +1,652 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..06f06f7716 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 76 + 76 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/main.c new file mode 100644 index 0000000000..5040c4692f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/main.c @@ -0,0 +1,280 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ +void UART5_ProtocolInit(void); + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + + FLASH_Init(FLASH_CSMODE_DISABLE); + FLASH_CycleInit(); + + UART5_ProtocolInit(); + + test_success = 1; + + printf("This is a Flash protection template\r\n"); + printf("===========================================\r\n"); + printf("1. Enable write protection.\r\n"); + printf("2. Disable write protection.\r\n"); + printf("3. Enable ICE protection.\r\n"); + printf("4. Disable ICE protection.\r\n"); + printf("5. Enable read protection.\r\n"); + printf("6. Disable read protection.\r\n"); + printf("===========================================\r\n"); + printf("Please input 1 ~ 6\r\n"); + printf("\r\n"); + + while (1) + { + WDT_Clear(); + } +} + +void UART5_ProtocolInit(void) +{ + UART_InitType UART_InitStruct; + + UART_DeInit(UART5); + UART_StructInit(&UART_InitStruct); + UART_InitStruct.Mode = UART_MODE_TX | UART_MODE_RX; + UART_InitStruct.Baudrate = 115200; + UART_InitStruct.FirstBit = UART_FIRSTBIT_LSB; + UART_InitStruct.Parity = UART_PARITY_NONE; + UART_Init(UART5, &UART_InitStruct); + + UART_INTConfig(UART5, UART_INT_RX, ENABLE); + UART_ClearINTStatus(UART5, UART_INTSTS_RX); + CORTEX_SetPriority_ClearPending_EnableIRQ(UART5_IRQn, 0); +} + +static void Flash_EnableWriteProtectionTest(void) +{ + uint8_t i; + uint8_t wdata[16], rdata[16]; + + for (i=0; i<16; i++) + { + wdata[i] = 17*i; + rdata[i] = 0; + } + + /* Disable Block-12(0x30000~0x33FFF) */ + FLASH_WriteProtection(FLASH_BLOCK_12, DISABLE); + FLASH_SectorErase(0x30000); + FLASH_ProgramByte(0x30000, wdata, 16); + for (i=0; i<16; i++) + rdata[i] = *(__IO uint8_t *)(0x30000+i); + + printf("Block-12(0x30000~0x33FFF) Write Protection disabled\r\n"); + printf("0x30000 ~ 0x3000F write:\r\n"); + for (i=0; i<16; i++) + printf("0x%x\t", wdata[i]); + printf("\r\n"); + printf("0x30000 ~ 0x3000F read:\r\n"); + for (i=0; i<16; i++) + printf("0x%x\t", rdata[i]); + printf("\r\n"); + + /* Enable Block-12(0x30000~0x33FFF) */ + FLASH_WriteProtection(FLASH_BLOCK_12, ENABLE); + FLASH_SectorErase(0x30000); + for (i=0; i<16; i++) + rdata[i] = *(__IO uint8_t *)(0x30000+i); + + printf("Block-12(0x30000~0x33FFF) Write Protection enabled\r\n"); + printf("Sector Erase(0x30000~0x303FF) fail\r\n"); + printf("0x30000 ~ 0x3000F read:\r\n"); + for (i=0; i<16; i++) + printf("0x%x\t", rdata[i]); + printf("\r\n"); + printf("\r\n"); +} + +static void Flash_DisableWriteProtectionTest(void) +{ + uint8_t i; + uint8_t rdata[16]; + + for (i=0; i<16; i++) + { + rdata[i] = 0; + } + + /* Disable Block-12(0x30000~0x33FFF) */ + FLASH_WriteProtection(FLASH_BLOCK_12, DISABLE); + FLASH_SectorErase(0x30000); + for (i=0; i<16; i++) + rdata[i] = *(__IO uint8_t *)(0x30000+i); + + printf("Block-12(0x30000~0x33FFF) Write Protection disabled\r\n"); + printf("Sector Erase(0x30000~0x303FF) OK\r\n"); + printf("0x30000 ~ 0x3000F read:\r\n"); + for (i=0; i<16; i++) + printf("0x%x\t", rdata[i]); + printf("\r\n"); + printf("\r\n"); +} + +static void Flash_EnableICEProtectionTest(void) +{ + FLASH_ICEProtection(ENABLE); + printf("ICE Protection enabled, can not connect target with SWD\r\n"); + printf("\r\n"); +} + +static void Flash_DisableICEProtectionTest(void) +{ + printf("The last sector be erased\r\n"); + printf("ICE Protection disabled, reset target, can connect target with SWD\r\n"); + printf("\r\n"); + + FLASH_ICEProtection(DISABLE); +} + +static void Flash_EnableReadProtectionTest(void) +{ + uint8_t i; + uint8_t rdata[16]; + + FLASH_SetReadProtection(FLASH_BLOCK_12); + FLASH_SectorErase(0x30000); + for (i=0; i<16; i++) + rdata[i] = *(__IO uint8_t *)(0x30000+i); + + printf("Block-12(0x30000~0x33FFF) Read Protection enabled\r\n"); + printf("Sector Erase(0x30000~0x303FF) OK\r\n"); + printf("0x30000 ~ 0x3000F read:\r\n"); + for (i=0; i<16; i++) + printf("0x%x\t", rdata[i]); + printf("\r\n"); + printf("\r\n"); +} + +static void Flash_DisableReadProtectionTest(void) +{ + printf("Read Protection disabled, Chip erase\r\n"); + FLASH_ChipErase(); +} + +void UART5_InterruptService(void) +{ + uint8_t data = 0U; + + /* Error handle */ + if ((UART_GetINTStatus(UART5, UART_INTSTS_RXPE)) ||\ + (UART_GetINTStatus(UART5, UART_INTSTS_RXOV))) + { + UART_ClearINTStatus(UART5, UART_INTSTS_RXPE); + UART_ClearINTStatus(UART5, UART_INTSTS_RXOV); + printf("Recieved data error, data invalid, input again\r\n"); + } + /* Get data */ + else + { + if (UART_GetINTStatus(UART5, UART_INTSTS_RX)) + { + UART_ClearINTStatus(UART5, UART_INTSTS_RX); + data = UART_ReceiveData(UART5); + } + } + + switch (data) + { + case 1: + printf("[1] Enable write protection.\r\n"); + Flash_EnableWriteProtectionTest(); + break; + case 2: + printf("[2] Disable write protection.\r\n"); + Flash_DisableWriteProtectionTest(); + break; + case 3: + printf("[3] Enable ICE protection.\r\n"); + Flash_EnableICEProtectionTest(); + break; + case 4: + printf("[4] Disable ICE protection.\r\n"); + Flash_DisableICEProtectionTest(); + break; + case 5: + printf("[5] Enable read protection.\r\n"); + Flash_EnableReadProtectionTest(); + break; + case 6: + printf("[6] Disable read protection.\r\n"); + Flash_DisableReadProtectionTest(); + break; + default: + printf("Recieved data invalid, input again\r\n"); + break; + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/target_isr.c new file mode 100644 index 0000000000..aa344c738c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/target_isr.c @@ -0,0 +1,306 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ + UART5_InterruptService(); +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/Flash/Flash_Protection_UARTProtocol/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..1fb294b47b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 64 + 64 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..fd25a18c3c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/main.c new file mode 100644 index 0000000000..9aa30ff77a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/main.c @@ -0,0 +1,88 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + PMU_WakeUpPinConfig(GPIO_Pin_6, IOA_EDGEBOTH); + PMU_ClearIOAINTStatus(GPIO_Pin_6); + PMU_INTConfig(PMU_INT_IOAEN, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(PMU_IRQn, 0); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/target_isr.c new file mode 100644 index 0000000000..6dc7c3c683 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/target_isr.c @@ -0,0 +1,308 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ + if (PMU_GetIOAINTStatus(GPIO_Pin_6)) + { + PMU_ClearIOAINTStatus(GPIO_Pin_6); + printf("PMU, IOA6 EXIT\r\n"); + } +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_EXIT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..1fb294b47b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 64 + 64 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..fd25a18c3c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/main.c new file mode 100644 index 0000000000..36167d7854 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/main.c @@ -0,0 +1,135 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} +void Print_CurrentTime(void) +{ + RTC_TimeTypeDef rTime; + + /* Get time */ + RTC_GetTime(&rTime, RTC_INACCURATE); +#ifdef __GNUC__ + printf("20%lx-", rTime.Year); + printf("%02lx-", rTime.Month); + printf("%02lx ", rTime.Date); + printf("Weekday %lx ", rTime.WeekDay); + printf("%02lx:", rTime.Hours); + printf("%02lx:", rTime.Minutes); + printf("%02lx\r\n", rTime.Seconds); +#else + printf("20%x-", rTime.Year); + printf("%02x-", rTime.Month); + printf("%02x ", rTime.Date); + printf("Weekday %x ", rTime.WeekDay); + printf("%02x:", rTime.Hours); + printf("%02x:", rTime.Minutes); + printf("%02x\r\n", rTime.Seconds); +#endif +} +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + PMU_WakeUpPinConfig(GPIO_Pin_6, IOA_EDGEBOTH); + PMU_ClearIOAINTStatus(GPIO_Pin_6); + PMU_INTConfig(PMU_INT_IOAEN, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(PMU_IRQn, 0); + + + /* Selects VDCIN hysteresis */ + PMU_VDCINHYSSEL(PMU_VDCINHYSSEL_200MV); + /* Enable VDCIN detector */ + PMU_VDCINDetectorCmd(ENABLE); + + printf("========================\r\n"); + Print_CurrentTime(); + + test_success = 1; + + while (1) + { + /* If VDCIN drop, enter sleep mode*/ + if (PMU_GetVDCINDropStatus()) + { + /* Disable Watch Dog Timer */ + WDT_Disable(); + + PMU_EnterSleepMode(); + } + else + { + printf("VDCIN is not drop!\r\n"); + while (1); + } + WDT_Clear(); + /* Quit sleep mode, configure clocks/UART print */ + Print_CurrentTime(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/target_isr.c new file mode 100644 index 0000000000..679e1ea99d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ + if (PMU_GetIOAINTStatus(GPIO_Pin_6)) + { + PMU_ClearIOAINTStatus(GPIO_Pin_6); + Stdio_Init(); + printf("PMU, IOA6 EXIT\r\n"); + } +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIOA_WakeUp/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..a1ffdee562 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 72 + 72 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 49681276 + 0 + 0 + 5 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..fd25a18c3c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/main.c new file mode 100644 index 0000000000..7258d16af8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/main.c @@ -0,0 +1,103 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +__IO uint32_t delay_cycles; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* De-initialization UART, UART5 transmit pin(IOB7) as GPIO */ + UART_DeInit(UART5); + + /* Configure IOB7, output CMOS mode */ + GPIO_WriteBit(GPIO_B, 7, 0); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + test_success = 1; + + while (1) + { + /* Uncertain delay, set IOB7 */ + for (delay_cycles=0; delay_cycles<10000; delay_cycles++); + GPIO_WriteBit(GPIO_B, 7, 1); + + /* Uncertain delay, reset IOB7 */ + for (delay_cycles=0; delay_cycles<10000; delay_cycles++); + GPIO_WriteBit(GPIO_B, 7, 0); + + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/GPIO/GPIO_Toggle/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..c10c524977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 59 + 59 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Src/main.c new file mode 100644 index 0000000000..d6d2cd898a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C1024_100KClock/Src/main.c @@ -0,0 +1,148 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +#define BufferSize 1000 +uint8_t Wr_Buffer[BufferSize]; +uint8_t Rd_Buffer[BufferSize]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 26M (AHB Clock divided by 1) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 1; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + I2C_InitType I2C_InitStruct; + I2C_WRType I2C_WRInitStruct; + uint16_t retval; + uint32_t i; + uint8_t State_OK = 1; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + for (i=0; i +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..6e325f4d46 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 279 + 279 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/main.c new file mode 100644 index 0000000000..1d32dac247 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/main.c @@ -0,0 +1,147 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +uint8_t Wr_Buffer[512]; +uint8_t Rd_Buffer[512]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 26M (AHB Clock divided by 1) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 1; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + I2C_InitType I2C_InitStruct; + I2C_WRType I2C_WRInitStruct; + uint16_t retval; + uint32_t i; + uint8_t State_OK = 1; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + for (i=0; i<512; i++) + { + Wr_Buffer[i] = rand() % 256; + Rd_Buffer[i] = 0; + } + + /* I2C initialization */ + I2C_DeInit(I2C_REMAP_DISABLE); + I2C_StructInit(&I2C_InitStruct); + I2C_Init(&I2C_InitStruct); + + /* Enable I2C */ + I2C_Cmd(ENABLE); + + test_success = 1; + + /* Write the entire EEPROM with random numbers */ + I2C_WRInitStruct.SubAddrType = I2C_SUBADDR_2BYTE; + I2C_WRInitStruct.SlaveAddr = 0xA0; + I2C_WRInitStruct.PageRange = 64; + I2C_WRInitStruct.Length = 512; + I2C_WRInitStruct.pBuffer = Wr_Buffer; + I2C_WRInitStruct.SubAddress = 0; + retval = I2C_MasterWriteBytes(&I2C_WRInitStruct); + if (retval) + { + printf("I2C write error!\r\n"); + State_OK = 0; + } + + /* Read datas from EEPROM */ + I2C_WRInitStruct.pBuffer = Rd_Buffer; + retval = I2C_MasterReadBytes(&I2C_WRInitStruct); + if (retval) + { + printf("I2C read error!\r\n"); + State_OK = 0; + } + + I2C_DeInit(I2C_REMAP_DISABLE); + + /* Compare datas */ + for (i=0; i<512; i++) + { + if (Rd_Buffer[i] != Wr_Buffer[i]) + { + State_OK = 0; + break; + } + } + + if (State_OK) + printf("Write/read EEPROM OK!\r\n"); + else + printf("Write/read EEPROM error!\r\n"); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_100KClock/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..6e325f4d46 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 279 + 279 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/main.c new file mode 100644 index 0000000000..bf992f57f0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/main.c @@ -0,0 +1,168 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +uint8_t Wr_Buffer[512]; +uint8_t Rd_Buffer[512]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 26M (AHB Clock divided by 1) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 1; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief TMR3_13M + */ +void TMR3_13M(void) +{ + TMR_InitType TMR_InitStruct; + + TMR_DeInit(TMR3); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 2 -1; + TMR_Init(TMR3, &TMR_InitStruct); + + TMR_Cmd(TMR3, ENABLE); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + I2C_InitType I2C_InitStruct; + I2C_WRType I2C_WRInitStruct; + uint16_t retval; + int i; + uint8_t State_OK = 1; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + for (i=0; i<512; i++) + { + Wr_Buffer[i] = rand() % 256; + Rd_Buffer[i] = 0; + } + + /* Start the TMR3 Base generation with overflow frequency equal to 13107200Hz */ + TMR3_13M(); + + /* I2C initialization */ + I2C_DeInit(I2C_REMAP_DISABLE); + I2C_StructInit(&I2C_InitStruct); + I2C_InitStruct.ClockSource = I2C_CLOCKSOURCE_TIM3OFD8; + I2C_Init(&I2C_InitStruct); + + /* Enable I2C */ + I2C_Cmd(ENABLE); + + test_success = 1; + + /* Write the entire EEPROM with random numbers */ + I2C_WRInitStruct.SubAddrType = I2C_SUBADDR_2BYTE; + I2C_WRInitStruct.SlaveAddr = 0xA0; + I2C_WRInitStruct.PageRange = 64; + I2C_WRInitStruct.Length = 512; + I2C_WRInitStruct.pBuffer = Wr_Buffer; + I2C_WRInitStruct.SubAddress = 0; + retval = I2C_MasterWriteBytes(&I2C_WRInitStruct); + if (retval) + { + printf("I2C write error!\r\n"); + State_OK = 0; + } + + /* Read datas from EEPROM */ + I2C_WRInitStruct.pBuffer = Rd_Buffer; + retval = I2C_MasterReadBytes(&I2C_WRInitStruct); + if (retval) + { + printf("I2C read error!\r\n"); + State_OK = 0; + } + + I2C_DeInit(I2C_REMAP_DISABLE); + TMR_DeInit(TMR3); + + /* Compare datas */ + for (i=0; i<512; i++) + { + if (Rd_Buffer[i] != Wr_Buffer[i]) + { + State_OK = 0; + break; + } + } + + if (State_OK) + printf("Write/read EEPROM OK!\r\n"); + else + printf("Write/read EEPROM error!\r\n"); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/I2C/I2C_EEPROM_AT24C256_1MClock/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/main.h new file mode 100644 index 0000000000..b5ff1a3505 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/main.h @@ -0,0 +1,29 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +void ISO78160_TransmitErrorHandle(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..088664500f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..b7bb72cc76 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 96 + 96 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/main.c new file mode 100644 index 0000000000..58f06b4315 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/main.c @@ -0,0 +1,120 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +void ISO78160_TransmitErrorHandle(void) +{ + /* Transmit error handle */ + if (ISO7816_GetINTStatus(ISO78160, ISO7816_INTSTS_TXRTYERR)) + { + ISO7816_ClearINTStatus(ISO78160, ISO7816_INTSTS_TXRTYERR); + printf("Transmit error\r\n"); + } +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + ISO7816_InitType ISO7816_InitStruct; + uint8_t data[4] = { 0x12, 0x34, 0x56, 0x78 }; + int i; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* ISO78160 initialization */ + ISO7816_DeInit(ISO78160); + ISO7816_InitStruct.FirstBit = ISO7816_FIRSTBIT_MSB; + ISO7816_InitStruct.Parity = ISO7816_PARITY_EVEN; + ISO7816_InitStruct.Baudrate = 9600; + ISO7816_InitStruct.TXRetry = ISO7816_TXRTY_5; + ISO7816_InitStruct.RXACKLength = ISO7816_RXACKLEN_2; + ISO7816_InitStruct.TXNACKLength = ISO7816_TXNACKLEN_2; + ISO7816_Init(ISO78160, &ISO7816_InitStruct); + + /* Enable ISO78160 transmit error interrupt */ + ISO7816_INTConfig(ISO78160, ISO7816_INT_TXRTYERR, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ISO78160_IRQn, 3); + + ISO7816_Cmd(ISO78160, ENABLE); + + for (i=0; i<4; i++) + { + ISO7816_SendData(ISO78160, data[i]); + while (!ISO7816_GetINTStatus(ISO78160, ISO7816_INTSTS_TXDONE)); + ISO7816_ClearINTStatus(ISO78160, ISO7816_INTSTS_TXDONE); + } + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/target_isr.c new file mode 100644 index 0000000000..91e4ad66eb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ + ISO78160_TransmitErrorHandle(); +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/ISO7816/ISO7816_Transmit/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..ed45bdeba0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..2ebf86f188 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 171 + 171 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/main.c new file mode 100644 index 0000000000..c45b27a1c1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/main.c @@ -0,0 +1,235 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +#define lcd_a 0x08 +#define lcd_b 0x04 +#define lcd_c 0x02 + +#define lcd_d 0x10 +#define lcd_e 0x20 +#define lcd_g 0x40 +#define lcd_f 0x80 + +void LCD_Clean() +{ + int i; + for( i=0;i<40;i++) + LCD->FB[i] =0x00; +} + +uint32_t LCD_NTOF(uint32_t num1) +{ + switch (num1) + { + case 0: num1=lcd_a+lcd_b+lcd_c+lcd_d+lcd_e+lcd_f; break; + case 1: num1=lcd_b+lcd_c; break; + case 2: num1=lcd_a+lcd_b+lcd_g+lcd_e+lcd_d; break; + case 3: num1=lcd_a+lcd_b+lcd_g+lcd_c+lcd_d; break; + case 4: num1=lcd_f+lcd_g+lcd_b+lcd_c; break; + case 5: num1=lcd_a+lcd_f+lcd_g+lcd_c+lcd_d; break; + case 6: num1=lcd_a+lcd_f+lcd_e+lcd_d+lcd_c+lcd_g;break; + case 7: num1=lcd_a+lcd_b+lcd_c; break; + case 8: num1=lcd_a+lcd_b+lcd_c+lcd_d+lcd_e+lcd_f+lcd_g; break; + case 9: num1=lcd_a+lcd_b+lcd_c+lcd_d+lcd_f+lcd_g; break; + default: num1=lcd_d; + } + num1= ((num1&0xf0)<<4)+(num1&0x0f); + return num1; +} + +uint32_t hextobcd(uint32_t num) +{ + int num_1,num_2,num_3,num_4,num_5,num_6,num_7,num_8; + num_1=num%10; + num_2=num%100/10; + num_3=num%1000/100; + num_4=num%10000/1000; + num_5=num%100000/10000; + num_6=num%1000000/100000; + num_7=num%10000000/1000000; + num_8=num%100000000/10000000; + + num=num_1+(num_2<<4)+(num_3<<8)+(num_4<<12)+ \ + (num_5<<16)+(num_6<<20)+(num_7<<24)+(num_8<<28); + return num; +} + + +void LCD_Number(uint32_t num) +{ + uint32_t num1,num2,num3,num4,num5,num6,num7,num8; + + num=hextobcd(num); + + num1=(num>>28)&0xf; + LCD->FB[5]=LCD_NTOF(num1); //seg20,seg21 + + num2=(num>>24)&0xf; + LCD->FB[3]=LCD_NTOF(num2)<<16;//seg14,seg15 + + num3=(num>>20)&0xf; + LCD->FB[6]=(LCD_NTOF(num3)&0xff00); //seg25 + LCD->FB[6]|=(LCD_NTOF(num3)&0x00ff)<<16; //seg26 + + num4=(num>>16)&0xf; + LCD->FB[6]|=(LCD_NTOF(num4)&0xff00)<<16; //seg27 + LCD->FB[8]=(LCD_NTOF(num4)&0x00ff)<<16; //seg34 + + num5=(num>>12)&0xf; + LCD->FB[11]=(LCD_NTOF(num5)&0xff00)<<16; //seg47 + LCD->FB[12]=(LCD_NTOF(num5)&0x00ff)<<8; //seg49 + + num6=(num>>8)&0xf; + LCD->FB[13]=(LCD_NTOF(num6)&0xff00)>>8; //seg52 + LCD->FB[13]|=(LCD_NTOF(num6)&0x00ff)<<24; //seg55 + + num7=(num>>4)&0xf; + LCD->FB[14]=(LCD_NTOF(num7)&0xff00)>>8; //seg56 + LCD->FB[14]|=(LCD_NTOF(num7)&0x00ff)<<8; //seg57 + + num8=(num>>0)&0xf; + LCD->FB[14]|=(LCD_NTOF(num8)&0xff00)<<8; //seg58 + LCD->FB[14]|=(LCD_NTOF(num8)&0x00ff)<<24; //seg59 +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + LCD_InitType LCD_InitStruct; + TMR_InitType TMR_InitStruct; + LCD_IOInitType LCD_IOInitStruct; + uint32_t tmp0, tmp1; + uint16_t tmp2; + uint32_t ticks_start; + uint32_t i; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* LCD initialization, configure with default value */ + LCD_DeInit(); + LCD_StructInit(&LCD_InitStruct); + /* Initialize the BKFILL member */ + LCD_InitStruct.BKFILL = LCD_BKFILL_0; + /* Initialize the Drv member */ + LCD_InitStruct.Drv = LCD_DRV_300; + /* Initialize the FBMODE member */ + LCD_InitStruct.FBMODE = LCD_FBMODE_BUFA; + /* Initialize the FRQ member */ + LCD_InitStruct.FRQ = LCD_FRQ_512H; + /* Initialize the SWPR member */ + LCD_InitStruct.SWPR = 0; + /* Initialize the Type member */ + LCD_InitStruct.Type = LCD_TYPE_4COM; + LCD_Init(&LCD_InitStruct); + + LCD_Clean(); + LCD->FB[3] =0X0f080000; + LCD->FB[5] =0X00000E06; + LCD->FB[6] =0X0B000B00; + LCD->FB[11] =0X0B000000; + LCD->FB[12] =0X00000E00; + + tmp0 = BIT0|BIT1|BIT2|BIT3|BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15| \ + BIT20|BIT21|BIT22|BIT23|BIT24|BIT25|BIT26|BIT27; + tmp1 = BIT2|BIT15|BIT17|BIT18|BIT19|BIT20|BIT23|BIT24|BIT25|BIT26|BIT27; + tmp2 = 0; + + /* Enable LCD, configure LCD COMs and SEGs IO(disable I/O) */ + LCD_IOInitStruct.COMMode = LCD_TYPE_4COM; + LCD_IOInitStruct.SegCtrl0 = tmp0; + LCD_IOInitStruct.SegCtrl1 = tmp1; + LCD_IOInitStruct.SegCtrl2 = tmp2; + LCD_Cmd(&LCD_IOInitStruct, ENABLE); + + TMR_DeInit(TMR0); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 0xFFFFFFFF; + TMR_Init(TMR0, &TMR_InitStruct); + /* Enable Timer0 */ + TMR_Cmd(TMR0, ENABLE); + + test_success = 1; + + while (1) + { + for (i=0; i<100; i++) + { + LCD_Number(i); + + WDT_Clear(); + + /* Delay 200ms */ + ticks_start = TMR_GetCurrentValue(TMR0); + while ((ticks_start - TMR_GetCurrentValue(TMR0)) < (13107200/5-1)); + } + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_D1135_DisplayNumber/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..edafc82faf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/template.uvoptx @@ -0,0 +1,656 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 314 + 1 +
5148
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\main.c + + \\template\../Src/main.c\314 + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 1 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..2367cbe894 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 320 + 320 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/main.c new file mode 100644 index 0000000000..f2745f92ad --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/main.c @@ -0,0 +1,345 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +#define Const_LCDRAMLen 17 + +uint8_t guc_LCDRAM[Const_LCDRAMLen]; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + + + +void LCD_Clean() +{ + int i; + for( i=0;i<40;i++) + LCD->FB[i] =0x00; +} + + +#define number9H 1 +#define number9L 0 +#define number8H 3 +#define number8L 2 +#define number7H 5 +#define number7L 4 +#define number6H 7 +#define number6L 6 +#define number5H 9 +#define number5L 8 +#define number4H 11 +#define number4L 10 +#define number3H 13 +#define number3L 12 +#define number2H 15 +#define number2L 14 + +const uint8_t NumAddr[16] = {number9H,number9L,number8H,number8L,number7H,number7L,number6H,number6L,number5H, + number5L,number4H,number4L,number3H,number3L,number2H,number2L}; + + +#define NUM1B BIT4 +#define NUM1G BIT5 +#define NUM1C BIT6 + +#define NUM1A BIT4 +#define NUM1F BIT5 +#define NUM1E BIT6 +#define NUM1D BIT7 + + +const uint8_t NUMTABLE_1L[]= +{ + NUM1B+NUM1C, //0 + NUM1B+NUM1C, //1 + NUM1G+NUM1B, //2 + NUM1B+NUM1G+NUM1C, //3 + NUM1B+NUM1C+NUM1G, //4 + NUM1G+NUM1C, //5 + NUM1G+NUM1C, //6 + NUM1B+NUM1C, //7 + NUM1G+NUM1B+NUM1C, //8 + NUM1B+NUM1G+NUM1C, //9 + + NUM1G+NUM1B+NUM1C, //A + NUM1C+NUM1G, //B + 0, //C + NUM1B+NUM1C+NUM1G, //D + NUM1G, //E + NUM1G, //F +}; + +const uint8_t NUMTABLE_1H[]= +{ + NUM1A+NUM1E+NUM1F+NUM1D, //0 + 0, //1 + NUM1D+NUM1E+NUM1A, //2 + NUM1D+NUM1A, //3 + NUM1F, //4 + NUM1D+NUM1F+NUM1A, //5 + NUM1D+NUM1E+NUM1F+NUM1A, //6 + NUM1A, //7 + NUM1D+NUM1E+NUM1F+NUM1A, //8 + NUM1A+NUM1D+NUM1F, //9 + + NUM1E+NUM1F+NUM1A, //A + NUM1D+NUM1E+NUM1F, //B + NUM1A+NUM1D+NUM1E+NUM1F, //C + NUM1D+NUM1E, //D + NUM1D+NUM1E+NUM1F+NUM1A, //E + NUM1E+NUM1F+NUM1A, //F +}; + +#define N_Resd1H 0xf1 +#define N_Resd1L 0xf0 + +#define LCD_CHAR1H_G (NUM1G) //'-' +#define LCD_CHAR1L_G (0) //'-' +#define LCD_CHAR1H_L (NUM1D+NUM1E+NUM1F) //'L' +#define LCD_CHAR1L_L (0) //'L' +#define LCD_CHAR1H_r (NUM1E+NUM1G) //'r' +#define LCD_CHAR1L_r (0) //'r' +#define LCD_CHAR1H_n (NUM1E+NUM1G) //'n' +#define LCD_CHAR1L_n (NUM1C) //'n' +#define LCD_CHAR1H_o (NUM1D+NUM1E+NUM1G) //'o' +#define LCD_CHAR1L_o (NUM1C) //'o' +#define LCD_CHAR1H_C (NUM1D+NUM1E+NUM1F) //'C' +#define LCD_CHAR1L_C (NUM1A) //'C' +#define LCD_CHAR1H_E (NUM1D+NUM1E+NUM1F+NUM1G) //'E' +#define LCD_CHAR1L_E (NUM1A) //'E' + + +void Disp_Numb(uint32_t data1, uint32_t type) +{ + uint8_t tmpdata, tmptype; + uint8_t i; + uint8_t tmpdisph,tmpdispl; + uint8_t *p; + uint8_t *q; + + for(i=0; i<8; i++) + { + tmpdata = (uint8_t)(data1 & 0x0F); //Get the last digit + tmptype = (uint8_t)(type & 0x0F); + data1 >>= 4; //Right shift + type >>= 4; + + tmpdisph = NUMTABLE_1H[tmpdata]; //Get high display code + tmpdispl = NUMTABLE_1L[tmpdata]; //Get low display code + +// + p = guc_LCDRAM + NumAddr[i*2]; //Digital display buffer + q = guc_LCDRAM + NumAddr[i*2+1]; //Digital display buffer + + *p = 0; //Clear only digits + *q = 0; //Clear only digits + + + switch(tmptype) //type + { + case 0: + *p |= tmpdisph; //show number + *q |= tmpdispl; //show number + + break; + case 1: + *p |= LCD_CHAR1H_G; + *q |= LCD_CHAR1L_G; //show '-' + break; + case 2: //show 'L' + *p |= LCD_CHAR1H_L; + *q |= LCD_CHAR1L_L; + break; + case 3: //show 'r' + *p |= LCD_CHAR1H_r; + *q |= LCD_CHAR1L_r; + break; + case 4: //show 'n' + *p |= LCD_CHAR1H_n; + *q |= LCD_CHAR1L_n; + break; + case 5: //show 'o' + *p |= LCD_CHAR1H_o; + *q |= LCD_CHAR1L_o; + break; + case 6: //ÏÔʾ×Öĸ¡®E¡¯ + *p |= LCD_CHAR1H_E; + *q |= LCD_CHAR1L_E; + break; + case 7: //ÏÔʾ×Öĸ¡®C¡¯ + *p |= LCD_CHAR1H_C; + *q |= LCD_CHAR1L_C; + break; + case 0x0a: + *p |= 0x00; //clear + *q |= 0x00; + break; + default: + break; + } + } +} + + void RefreshLCDRAM(uint8_t *p) + { + + LCD->FB[1] = (((uint32_t)(guc_LCDRAM[2]&0xff) << 24) | ((uint32_t)(guc_LCDRAM[1]&0xff) << 8) | ((uint32_t)(guc_LCDRAM[0]&0xff))); + + LCD->FB[2] = ( ((uint32_t)(guc_LCDRAM[4]&0xff) << 8) | ((uint32_t)(guc_LCDRAM[3]&0xff))); + + LCD->FB[6] = (((uint32_t)(guc_LCDRAM[6]&0xff) << 24) | ((uint32_t)(guc_LCDRAM[5]&0xff) << 16)); + + LCD->FB[7] = (((uint32_t)(guc_LCDRAM[9]&0xff) << 24) |((uint32_t)(guc_LCDRAM[8]&0xff) << 16) | ((uint32_t)(guc_LCDRAM[7]&0xff))); + + LCD->FB[8] = (((uint32_t)(guc_LCDRAM[13]&0xff) << 24) | ((uint32_t)(guc_LCDRAM[12]&0xff) << 16) | ((uint32_t)(guc_LCDRAM[11]&0xff) << 8) | ((uint32_t)(guc_LCDRAM[10]&0xff) )); + + LCD->FB[9] = ( ((uint32_t)(guc_LCDRAM[16]&0xff) << 16) + | ((uint32_t)(guc_LCDRAM[15]&0xff) << 8) | (uint32_t)(guc_LCDRAM[14]&0xff)); + + } + + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + LCD_InitType LCD_InitStruct; + TMR_InitType TMR_InitStruct; + LCD_IOInitType LCD_IOInitStruct; + uint32_t tmp0, tmp1; + uint16_t tmp2; + uint32_t ticks_start; + uint32_t i; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* LCD initialization, configure with default value */ + LCD_DeInit(); + + for(i=0; i<400000; i++) + { + __NOP(); + } + + LCD_StructInit(&LCD_InitStruct); + /* Initialize the BKFILL member */ + LCD_InitStruct.BKFILL = LCD_BKFILL_0; + /* Initialize the Drv member */ + LCD_InitStruct.Drv = LCD_DRV_600; + /* Initialize the FBMODE member */ + LCD_InitStruct.FBMODE = LCD_FBMODE_BUFA; + /* Initialize the FRQ member */ + LCD_InitStruct.FRQ = LCD_FRQ_256H; + /* Initialize the SWPR member */ + LCD_InitStruct.SWPR = 0; + /* Initialize the Type member */ + LCD_InitStruct.Type = LCD_TYPE_8COM; + LCD_Init(&LCD_InitStruct); + + LCD_Clean(); + LCD->FB[3] =0X0f080000; + LCD->FB[5] =0X00000E06; + LCD->FB[6] =0X0B000B00; + LCD->FB[11] =0X0B000000; + LCD->FB[12] =0X00000E00; + + tmp0 = 0xDC0003B0; //PUMA + tmp1 = 0x0000007F; + tmp2 = 0x00000000; + + /* Enable LCD, configure LCD COMs and SEGs IO(disable I/O) */ + LCD_IOInitStruct.COMMode = LCD_TYPE_8COM; + LCD_IOInitStruct.SegCtrl0 = tmp0; + LCD_IOInitStruct.SegCtrl1 = tmp1; + LCD_IOInitStruct.SegCtrl2 = tmp2; + LCD_Cmd(&LCD_IOInitStruct, ENABLE); + + TMR_DeInit(TMR0); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 0xFFFFFFFF; + TMR_Init(TMR0, &TMR_InitStruct); + /* Enable Timer0 */ + TMR_Cmd(TMR0, ENABLE); + + test_success = 1; + + while (1) + { + for (i=000; i<200; i++) + { + Disp_Numb(0x12345678+i, 0x00000000); + RefreshLCDRAM(guc_LCDRAM); + WDT_Clear(); + + /* Delay 200ms */ + ticks_start = TMR_GetCurrentValue(TMR0); + while ((ticks_start - TMR_GetCurrentValue(TMR0)) < (13107200/5-1)); + } + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/LCD/LCD_TS_DH_3541_DisplayNumber/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.ewd @@ -0,0 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+ + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..03ac330afe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400*(n)/1024-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..f3574d0a12 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,638 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..903d287c03 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,652 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..d34bf48793 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 72 + 72 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/main.c new file mode 100644 index 0000000000..4b405a36f4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/main.c @@ -0,0 +1,107 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* AVCC Lower Power Detector ENABLE */ + PMU_AVCCCmd(ENABLE); + PMU_AVCCLVDetectorCmd(ENABLE); + + /* Clear AVCCLV interrupt flag */ + ANA_ClearINTStatus(ANA_INT_AVCCLV); + /* Enable AVCCLV interrupt, ANA NVIC interrupt */ + ANA_INTConfig(ANA_INT_AVCCLV, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 0); + + test_success = 1; + + /* Disable WDT, enter sleep mode */ + printf("Enter sleep mode\r\n"); + WDT_Disable(); + if (PMU_EnterSleepMode()) + { + printf("Enter sleep fail\r\n"); + while (1); + } + + /* Quit sleep mode, Clock initialization */ + Clock_Init(); + Stdio_Init(); + printf("Exit sleep mode\r\n"); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/target_isr.c new file mode 100644 index 0000000000..a25a1c3826 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if (ANA_GetINTStatus(ANA_INT_AVCCLV)) + { + ANA_ClearINTStatus(ANA_INT_AVCCLV); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/AVCCLV_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.ewd @@ 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--- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..d34bf48793 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 72 + 72 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/main.c new file mode 100644 index 0000000000..741b63b250 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/main.c @@ -0,0 +1,106 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /*VDD alarm threshole is 3.6v, Check every 30us */ + PMU_VDDAlarmConfig(PMU_VDDALARM_3_6V, PMU_VDDALARM_CHKFRE_30US); + + /* Clear VDDALARM interrupt flag */ + ANA_ClearINTStatus(ANA_INT_VDDALARM); + /* Enable VDDALARM interrupt, ANA NVIC interrupt */ + ANA_INTConfig(ANA_INT_VDDALARM, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 0); + + test_success = 1; + + /* Disable WDT, enter sleep mode */ + printf("Enter sleep mode\r\n"); + WDT_Disable(); + if (PMU_EnterSleepMode()) + { + printf("Enter sleep fail\r\n"); + while (1); + } + + /* Quit sleep mode, Clock initialization */ + Clock_Init(); + Stdio_Init(); + printf("Exit sleep mode\r\n"); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/target_isr.c new file mode 100644 index 0000000000..06e1dfb1a3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if (ANA_GetINTStatus(ANA_INT_VDDALARM)) + { + ANA_ClearINTStatus(ANA_INT_VDDALARM); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/POWER/VDDAlarm_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..4b2dfcb207 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..1896d9045c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 86 + 86 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/main.c new file mode 100644 index 0000000000..a0e4c8ef7f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/main.c @@ -0,0 +1,110 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + PWM_BaseInitType PWM_BaseInitStruct; + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* De-initialization UART, UART5 transmit pin(IOB7) as GPIO */ + UART_DeInit(UART5); + /* Configure IOB7, output CMOS mode, output low */ + GPIO_WriteBit(GPIO_B, 7, 0); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + /* Enable PWM0 base interrupt, PWM0 NVIC interrupt */ + PWM_BaseINTConfig(PWM0, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(PWM0_IRQn, 0); + + /* Configure PWM0 CCR0 */ + PWM_CCRConfig(PWM0, PWM_CHANNEL_0, 32768-1); + PWM_ClearCounter(PWM0); + /* PWM0 base initialization + - PWM0 clock: 3276800Hz + - Count Mode: Up + Interrupt interval period = 32768/3276800 = 10ms */ + PWM_BaseInitStruct.ClockDivision = PWM_CLKDIV_4; + PWM_BaseInitStruct.ClockSource = PWM_CLKSRC_APB; + PWM_BaseInitStruct.Mode = PWM_MODE_UPCOUNT; + PWM_BaseInit(PWM0, &PWM_BaseInitStruct); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/target_isr.c new file mode 100644 index 0000000000..f125dba92f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/target_isr.c @@ -0,0 +1,310 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ + if (PWM_GetBaseINTStatus(PWM0)) + { + /* Toggle IOB7 */ + GPIOBToF_Write(GPIOB, GPIOB->DAT ^ GPIO_Pin_7); + /* Clear PWM0 base interrupt */ + PWM_ClearBaseINTStatus(PWM0); + } +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_16BitsBaseTimer_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.ewd @@ -0,0 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+ + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..7b3590403e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 99 + 99 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/main.c new file mode 100644 index 0000000000..48e0cdc3ac --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/main.c @@ -0,0 +1,138 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +__IO uint16_t CapData[10] = { 0 }; +__IO uint8_t count; + + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + PWM_BaseInitType PWM_BaseInitStruct; + PWM_ICInitType PWM_ICInitStruct; + GPIO_InitType GPIO_InitStruct; + uint8_t i; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* PWM3 base initialization */ + PWM_BaseStructInit(&PWM_BaseInitStruct); + PWM_BaseInitStruct.ClockDivision = PWM_CLKDIV_2; + PWM_BaseInitStruct.ClockSource = PWM_CLKSRC_APB; + PWM_BaseInitStruct.Mode = PWM_MODE_CONTINUOUS; + PWM_BaseInit(PWM3, &PWM_BaseInitStruct); + + /* PWM3 Channel 0 capture(falling) configuration */ + PWM_ICStructInit(&PWM_ICInitStruct); + PWM_ICInitStruct.Channel = PWM_CHANNEL_0; + PWM_ICInitStruct.CaptureMode = PWM_CM_FALLING; + PWM_ICInit(PWM3, &PWM_ICInitStruct); + + /* IOB0 input mode */ + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + /* Configure PWM3 capture input line: PWM0(IOB0) */ + PWM_ILineConfig(PWM3_IN0, PWM_ILINE_0); + + PWM_ClearCounter(PWM3); + + count = 0; + + MISC_IRQLATConfig(15); + + /* Enable PWM3 Channel capture interrupt, PWM3 NVIC interrupt */ + PWM_ClearChannelINTStatus(PWM3, PWM_CHANNEL_0, PWM_INT_CCIFG); + PWM_ChannelINTConfig(PWM3, PWM_CHANNEL_0, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(PWM3_IRQn, 3); + + test_success = 1; + + while (count < 10) + { + WDT_Clear(); + } + + /* Disable PWM3 timer */ + PWM_BaseStructInit(&PWM_BaseInitStruct); + PWM_BaseInitStruct.Mode = PWM_MODE_STOP; + PWM_BaseInit(PWM3, &PWM_BaseInitStruct); + PWM_ChannelINTConfig(PWM3, PWM_CHANNEL_0, DISABLE); + CORTEX_NVIC_DisableIRQ(PWM3_IRQn); + + for (i=0; i<10; i++) + printf("CapData[%d]\t%d\r\n", i, CapData[i]); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/target_isr.c new file mode 100644 index 0000000000..7f4198934c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/target_isr.c @@ -0,0 +1,319 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern __IO uint8_t count; +extern __IO uint16_t CapData[10]; + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ + /* Error(capture overflow) handle */ + if(PWM_GetChannelINTStatus(PWM3, PWM_CHANNEL_0, PWM_INT_COV)) + { + PWM_ClearChannelINTStatus(PWM3, PWM_CHANNEL_0, PWM_INT_COV); + printf("Capture overflow!\r\n"); + } + + /* Capture handle */ + if(PWM_GetChannelINTStatus(PWM3, PWM_CHANNEL_0, PWM_INT_CCIFG)) + { + PWM_ClearChannelINTStatus(PWM3, PWM_CHANNEL_0, PWM_INT_CCIFG); + CapData[count++] = PWM_GetCapture(PWM3, PWM_CHANNEL_0); + } +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_Capture/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..c82e526df1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 115 + 115 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/main.c new file mode 100644 index 0000000000..ac5d886195 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/main.c @@ -0,0 +1,139 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + PWM_BaseInitType PWM_BaseInitStruct; + PWM_OCInitType PWM_OCInitStruct; + + test_success = 0; + + Clock_Init(); + + /* PWM0 base initialization + - Count mode : CONTINUOUS mode + - Clock source : PCLK 13M + - Clock Divide : divide by 16 */ + PWM_BaseInitStruct.ClockDivision = PWM_CLKDIV_16; + PWM_BaseInitStruct.ClockSource = PWM_CLKSRC_APB; + PWM_BaseInitStruct.Mode = PWM_MODE_CONTINUOUS; + PWM_BaseInit(PWM0, &PWM_BaseInitStruct); + + /** PWM0 channel 0 Initialize: + - Mode : compare mode + - Out Mode : TOGGLE + - Out line : PWM0 output (IOB0) + Output: 6.25Hz + High/Low = 1/1 + */ + PWM_OLineConfig(PWM0_OUT0, PWM_OLINE_0); + PWM_OCInitStruct.Channel = PWM_CHANNEL_0; + PWM_OCInitStruct.OutMode = PWM_OUTMOD_TOGGLE; + PWM_OCInitStruct.Period = 0x8000; + PWM_OCInit(PWM0, &PWM_OCInitStruct); + + /** PWM0 channel 1 Initialize: + - Mode : compare mode + - Out Mode : TOGGLE_RESET + - Out line : PWM1 output (IOB6) + Output: 12.5Hz + High/Low = (0x8000-0x2000)/(0xFFFF-0x6000) = 3/5 + */ + PWM_OLineConfig(PWM0_OUT1, PWM_OLINE_1); + PWM_OCInitStruct.Channel = PWM_CHANNEL_1; + PWM_OCInitStruct.OutMode = PWM_OUTMOD_TOGGLE_RESET; + PWM_OCInitStruct.Period = 0x2000; + PWM_OCInit(PWM0, &PWM_OCInitStruct); + + /** PWM0 channel 2 Initialize: + - Mode : compare mode + - Out Mode : TOGGLE_RESET + - Out line : PWM2 output (IOB13) + Output: 12.5Hz + High/Low = = (0x8000-0x4000)/(0xFFFF-0x4000) = 1/3 + */ + PWM_OLineConfig(PWM0_OUT2, PWM_OLINE_2); + PWM_OCInitStruct.Channel = PWM_CHANNEL_2; + PWM_OCInitStruct.OutMode = PWM_OUTMOD_TOGGLE_RESET; + PWM_OCInitStruct.Period = 0x4000; + PWM_OCInit(PWM0, &PWM_OCInitStruct); + + PWM_ClearCounter(PWM0); + /* Enable PWM0 channel 0/1/2 output */ + PWM_OutputCmd(PWM0, PWM_CHANNEL_0, ENABLE); + PWM_OutputCmd(PWM0, PWM_CHANNEL_1, ENABLE); + PWM_OutputCmd(PWM0, PWM_CHANNEL_2, ENABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PWM/PWM_CompareOutput/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..510b2ab2c5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 112 + 112 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/main.c new file mode 100644 index 0000000000..499102e5c6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/main.c @@ -0,0 +1,136 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + + +#ifdef __GNUC__ + +extern void PMU_EnterIdle_FlashDSTB(void) __attribute__((section(".ram_exec"))); + +/** + * @brief Flash deep standby, enter idle mode. + * @note This function is executed in RAM. + * @param None + * @retval None + */ +void PMU_EnterIdle_FlashDSTB(void) +{ + /* Flash deep standby */ + FLASH->PASS = 0x55AAAA55; + FLASH->DSTB = 0xAA5555AA; + /* Enter Idle mode */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + __WFI(); +} + +#endif + + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStructure; + CLK_InitTypeDef CLK_Struct; + + test_success = 0; + +/* Normal mode */ +if (PMU_GetModeStatus() == 1U) +{ + WDT_Disable(); + + /* Forbidden all GPIOs */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; + GPIOA_Init(GPIOA, &GPIO_InitStructure); + GPIOBToF_Init(GPIOB, &GPIO_InitStructure); + GPIOBToF_Init(GPIOC, &GPIO_InitStructure); + GPIOBToF_Init(GPIOD, &GPIO_InitStructure); + GPIOBToF_Init(GPIOE, &GPIO_InitStructure); + GPIOBToF_Init(GPIOF, &GPIO_InitStructure); + + /* System clock be switched to RTC clock(32768Hz) */ + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_RTCCLK \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_RTCCLK; + CLK_Struct.RTCCLK.Source = CLK_RTCCLKSRC_XTALL; + CLK_Struct.RTCCLK.Divider = CLK_RTCCLKDIV_1; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 1; + CLK_ClockConfig(&CLK_Struct); + + /* Power down BGP/RCH */ + ANA->REG3 |= (ANA_REG3_BGPPD | ANA_REG3_RCHPD); + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCOEN; + /* Power down ADC */ + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + /* Comparator 1 power control */ + ANA->REG3 &= ~ANA_REG3_CMP1PDN; + /* Comparator 2 power control */ + ANA->REG3 &= ~ANA_REG3_CMP2PDN; + /* Power down Tiny ADC */ + ANA->REGF &= ~ANA_REGF_ADTPDN; + /* AVCC power down */ + ANA->REG8 &= ~ANA_REG8_AVCCLDOPD; + /* Power ON LCD */ + LCD->CTRL |= LCD_CTRL_EN; + ANA->REG7 |= BIT1; + /* VDCIN detector control */ + ANA->REGA |= ANA_REGA_VDCINDETPD; + /* VDD detector control */ + ANA->REG9 |= ANA_REG9_VDDDETPD; + + CLK_APBPeriphralCmd(CLK_APBPERIPHRAL_ALL, DISABLE); + CLK_AHBPeriphralCmd(CLK_AHBPERIPHRAL_ALL, DISABLE); + + /* Enter Idle mode */ + PMU_EnterIdle_FlashDSTB(); +} + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Idle_RTCCLK/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..6adb6f1903 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..583c72130e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 87 + 87 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/main.c new file mode 100644 index 0000000000..ca1bde7728 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/main.c @@ -0,0 +1,111 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + PMU_LowPWRTypeDef LowPower_InitStruct; + + test_success = 0; + + /* Clock initialization */ + Clock_Init(); + + /* Disable WDT */ + WDT_Disable(); + + /*------------------ Forbidden all GPIOs ------------------*/ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_All; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + GPIOBToF_Init(GPIOC, &GPIO_InitStruct); + GPIOBToF_Init(GPIOD, &GPIO_InitStruct); + GPIOBToF_Init(GPIOE, &GPIO_InitStruct); + GPIOBToF_Init(GPIOF, &GPIO_InitStruct); + + test_success = 1; + + /*------------------ Low power configuration ------------------*/ + LowPower_InitStruct.AHBPeriphralDisable = PMU_AHB_ALL; + LowPower_InitStruct.APBPeriphralDisable = PMU_APB_ALL; + LowPower_InitStruct.BGPPower = PMU_BGPPWR_OFF; + LowPower_InitStruct.CMP1Power = PMU_CMP1PWR_OFF; + LowPower_InitStruct.CMP2Power = PMU_CMP2PWR_OFF; + LowPower_InitStruct.AVCCPower = PMU_AVCCPWR_ON; + LowPower_InitStruct.TADCPower = PMU_TADCPWR_OFF; + LowPower_InitStruct.VDCINDetector = PMU_VDCINDET_DISABLE; + LowPower_InitStruct.VDDDetector = PMU_VDDDET_DISABLE; + PMU_EnterSleep_LowPower(&LowPower_InitStruct); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/PowerConsumption/PowerConsumption_Sleep/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/lib_conf.h new file mode 100644 index 0000000000..1016be9f02 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/lib_conf.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..b991f9c6ee --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/template.uvoptx @@ -0,0 +1,680 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + ktemp0,0x0A + + + 2 + 1 + ack_used,0x0A + + + 3 + 1 + RTCData,0x0A + + + 4 + 1 + rtcplldivsrc + + + 5 + 1 + PPMx10,0x0A + + + 6 + 1 + cal_value,0x10 + + + 7 + 1 + div_value,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + System Viewer\RTC + 35905 + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..4bc2feaf23 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 59 + 59 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 119 + 119 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/main.c new file mode 100644 index 0000000000..e60fe438fb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/main.c @@ -0,0 +1,265 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} +/** + * @brief Get_Temperature: + * @param [out]T: The pointer of temperature value got by this function + * @retval 1 Function error. + 0 Function successed. + + */ +uint32_t Get_Temperature(int16_t *T) +{ + ADC_InitType ADC_InitStruct; + int16_t adc_data; + + /* ADC interface initialization */ + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.Mode = ADC_MODE_TEMP; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct.ClockFrq = ADC_CLKFRQ_LOW; + ADC_InitStruct.SkipSample = ADC_SKIP_0; + ADC_InitStruct.AverageSample = ADC_AVERAGE_64; + ADC_InitStruct.TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct.Channel = ADC_CHANNEL_TEMP; + ADC_InitStruct.AverageEnable = ADC_CHANNEL_TEMP; + ADC_InitStruct.ResDivEnable = ADC_CHANNEL_NONE; + ADC_Init(&ADC_InitStruct); + + /* Enable ADC */ + ADC_Cmd(ENABLE); + + + /* Start Manual ADC conversion */ + ADC_StartManual(); + /* Waiting Manual ADC conversion done */ + if(ADC_WaitForManual(DELAY_MS(100))) + { + /*Reset ADC*/ + ADC_SoftReset(&ADC_InitStruct); + } + else + { + /* Get ADC data */ + adc_data = ADC_GetADCConversionValue(ADC_CHANNEL_TEMP); + + /*-------------------------- Manual calibration -----------------------------*/ + /* Get temperature original data */ + if (ADC_CalculateValue(ADC_TEMP, adc_data, T)) + { + return 1; + } + } + + /* Disable ADC */ + ADC_Cmd(DISABLE); + + return 0; +} + +void CalRTC(uint32_t rtcplldivsrc, int16_t T) +{ + uint32_t cal_value, div_value; + int16_t ack_used, PPMx10; + int16_t ktemp0, ktemp1, ktemp2, ktemp3; + int16_t Ti; + + /* Get section x temperature */ + ktemp0 = (int16_t)(RTC->ACKTEMP<<8 & 0xFF00); + ktemp1 = (int16_t)((RTC->ACKTEMP ) & 0xFF00); + ktemp2 = (int16_t)((RTC->ACKTEMP >> 8) & 0xFF00); + ktemp3 = (int16_t)((RTC->ACKTEMP >> 16) & 0xFF00); + + /* Calculate temperature(float) */ + Ti = RTC->ACTI; + + /* Get ACK(K parameter) */ + if (T < ktemp0) + ack_used = RTC->ACK[0]; + else if ((T >= ktemp0) && (T < ktemp1)) + ack_used = RTC->ACK[1]; + else if ((T >= ktemp1) && (T < ktemp2)) + ack_used = RTC->ACK[2]; + else if ((T >= ktemp2) && (T < ktemp3)) + ack_used = RTC->ACK[3]; + else + ack_used = RTC->ACK[4]; + + /* Calculate 10*PPM */ + PPMx10 = (int16_t)((((ack_used)*(((T-Ti)*(T-Ti))>>16))>>16) + (int16_t)(RTC->ACP4)); + /* Calculate the value of RTC_CAL, RTC_DIV */ + cal_value = (uint32_t)((((PPMx10*(int16_t)(RTC->ACP5))>>16)) + 1); + div_value = (uint32_t)((rtcplldivsrc>>1) - ((PPMx10*(int16_t)(RTC->ACP6))>>12) - 1); + + /* Write RTC_CAL/RTC_DIV register */ + RTC_WriteRegisters((uint32_t)&RTC->CAL, &cal_value, 1); + RTC->DIV = div_value; +} +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + NVR_RTCINFO RTCData; + TMR_InitType TMR_InitStruct; + uint32_t retval; + int16_t T; + uint32_t nCount; + uint32_t rtcplldivsrc = 26214400UL; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + +/*------------------------- RTC PLL divider output ---------------------------*/ + /* Enable RTC PLL divider output, IOA3 IOA7 */ + GPIOA_AFConfig(PMUIO7_AF_PLLDIV | PMUIO3_AF_PLLDIV, ENABLE); + RTC_PLLDIVConfig(RTC_PLLDIVSOURCE_PLLL, 1); + RTC_PLLDIVOutputCmd(ENABLE); + + /* Ensure AVCC is higher than 2.5V */ + nCount = 0; + while(1) + { + if(!PMU_GetAVCCLVStatus()) + { + nCount++; + } + else + { + nCount = 0; + } + if(nCount>=10) + { + break; + } + /* delay 1ms */ + CORTEX_Delay_nSysClock(DELAY_MS(1)); + } + + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* Get/load RTC NVR information */ + retval = NVR_GetInfo_LoadRTCData(&RTCData, rtcplldivsrc); + if (retval) + { +#ifdef __GNUC__ + printf("Get/load RTC NVR information error, return value 0x%lx\r\n", retval); +#else + printf("Get/load RTC NVR information error, return value 0x%x\r\n", retval); +#endif + } + else + { + printf("Get/load RTC NVR information OK!\r\n"); + } + + /* Timer0 initialization: + - Clock source: internal clock(APB clock 13107200Hz) + - Overflow interval: 5s */ + TMR_DeInit(TMR0); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 13107200*5 - 1; + TMR_Init(TMR0, &TMR_InitStruct); + /* Enable Timer0 */ + TMR_Cmd(TMR0, ENABLE); + + while (1) + { +/*-------------------------- Manual calibration -----------------------------*/ + /* Get temperature */ + if (Get_Temperature(&T)) + { + printf("Calculate temperature, checksum error\r\n"); + } + /* Calibrate RTC_CAL RTC_DIV */ + CalRTC(rtcplldivsrc, T); + + printf("Temperature is %2.3f\r\n", (float)T/256.0); +#ifdef __GNUC__ + printf("DIV 0x%lx\r\n", RTC->DIV); + printf("CAL 0x%lx\r\n", RTC->CAL); +#else + printf("DIV 0x%x\r\n", RTC->DIV); + printf("CAL 0x%x\r\n", RTC->CAL); +#endif + printf("\r\n"); + + test_success = 1; + + /* Delay 5s */ + while (TMR_GetINTStatus(TMR0) == 0) + { + WDT_Clear(); + } + TMR_ClearINTStatus(TMR0); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/target_isr.c new file mode 100644 index 0000000000..93adc10d40 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/target_isr.c @@ -0,0 +1,305 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_ManualCalibration/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..63a5848153 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/main.c new file mode 100644 index 0000000000..3f2d1cf0cb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/main.c @@ -0,0 +1,157 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +void Print_CurrentTime(void) +{ + RTC_TimeTypeDef rTime; + + /* Get time */ + RTC_GetTime(&rTime, RTC_INACCURATE); +#ifdef __GNUC__ + printf("20%lx-", rTime.Year); + printf("%02lx-", rTime.Month); + printf("%02lx ", rTime.Date); + printf("Weekday %lx ", rTime.WeekDay); + printf("%02lx:", rTime.Hours); + printf("%02lx:", rTime.Minutes); + printf("%02lx\r\n", rTime.Seconds); +#else + printf("20%x-", rTime.Year); + printf("%02x-", rTime.Month); + printf("%02x ", rTime.Date); + printf("Weekday %x ", rTime.WeekDay); + printf("%02x:", rTime.Hours); + printf("%02x:", rTime.Minutes); + printf("%02x\r\n", rTime.Seconds); +#endif +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + RTC_TimeTypeDef Time_Struct; + + test_success = 0; + + Clock_Init(); + /* Initializes FLASH 1USCYCLE. */ + FLASH_CycleInit(); + + Stdio_Init(); + + /* Set time */ + /* 2017-10-10 10:10:10 Tuesday */ + Time_Struct.Year = 0x17; + Time_Struct.Month = 0x10; + Time_Struct.Date = 0x10; + Time_Struct.Hours = 0x10; + Time_Struct.Minutes = 0x10; + Time_Struct.Seconds = 0x10; + Time_Struct.WeekDay = 0x02; + RTC_SetTime(&Time_Struct, RTC_INACCURATE); + + /* Configure RTC multi-second/multi-minute wake-up(sleep) function: + These two functions(interrupts) are independent. + - Multi-second, 3sec + - Multi-minute, 1min */ + RTC_WKUMinutesConfig(1); + RTC_WKUSecondsConfig(1); + RTC_WKUSecondsConfig(3); + PMU_SleepWKUSRCConfig_RTC(PMU_RTCEVT_WKUMIN | PMU_RTCEVT_WKUSEC, 0); + + /* Selects VDCIN hysteresis */ + PMU_VDCINHYSSEL(PMU_VDCINHYSSEL_200MV); + /* Enable VDCIN detector */ + PMU_VDCINDetectorCmd(ENABLE); + + test_success = 1; + + printf("========================\r\n"); + Print_CurrentTime(); + + while (1) + { + /* If VDCIN drop, enter sleep mode*/ + if (PMU_GetVDCINDropStatus()) + { + /* Disable Watch Dog Timer */ + WDT_Disable(); + + PMU_EnterSleepMode(); + } + else + { + printf("VDCIN is not drop!\r\n"); + while (1); + } + WDT_Clear(); + /* Quit sleep mode, configure clocks/UART print */ + Stdio_Init(); + Print_CurrentTime(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/target_isr.c new file mode 100644 index 0000000000..2d8c9abd00 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ + RTC_ClearINTStatus(RTC_INTSTS_WKUSEC | RTC_INTSTS_WKUMIN); +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_MulSecMin_WakeUpSleep/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..15b4dd33ff --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 66 + 66 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/main.c new file mode 100644 index 0000000000..817857c4ad --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/main.c @@ -0,0 +1,90 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + + RTC_PLLDIVConfig(RTC_PLLDIVSOURCE_PLLL, 0); + /* Enable IOA3 special function PLLDIV output */ + GPIOA_AFConfig(PMUIO3_AF_PLLDIV, ENABLE); + /* PLLDIV output frequency 1 Hz */ + RTC_PLLDIVConfig(RTC_PLLDIVSOURCE_PLLL, 1); + /* Enable RTC PLLDIV output */ + RTC_PLLDIVOutputCmd(ENABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_PLLDividerOutput_1Hz/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.ewd 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+ + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..fae1519d0c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000014A8F3A5 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 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..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..1ba6457fd7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 131 + 131 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/main.c new file mode 100644 index 0000000000..6b25cece25 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/main.c @@ -0,0 +1,155 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +void Print_CurrentTime(void) +{ + RTC_TimeTypeDef rTime; + + /* Get time */ + RTC_GetTime(&rTime, RTC_ACCURATE); +#ifdef __GNUC__ + printf("20%lx-", rTime.Year); + printf("%02lx-", rTime.Month); + printf("%02lx ", rTime.Date); + printf("Weekday %lx ", rTime.WeekDay); + printf("%02lx:", rTime.Hours); + printf("%02lx:", rTime.Minutes); + printf("%02lx\t", rTime.Seconds); + printf("%02lx\r\n", rTime.SubSeconds); +#else + printf("20%x-", rTime.Year); + printf("%02x-", rTime.Month); + printf("%02x ", rTime.Date); + printf("Weekday %x ", rTime.WeekDay); + printf("%02x:", rTime.Hours); + printf("%02x:", rTime.Minutes); + printf("%02x\t", rTime.Seconds); + printf("%02x\r\n", rTime.SubSeconds); +#endif +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + RTC_TimeTypeDef Time_Struct; + RTC_AlarmTypeDef RTC_AlarmStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + if(PMU_GetResetSource(PMU_RSTSRC_DPORST)) + { + PMU_ClearResetSource(PMU_RSTSRC_DPORST); + /* Set time */ + /* 2017-10-10 10:10:10 0ms */ + Time_Struct.Year = 0x17; + Time_Struct.Month = 0x10; + Time_Struct.Date = 0x10; + Time_Struct.Hours = 0x10; + Time_Struct.Minutes = 0x10; + Time_Struct.Seconds = 0x10; + Time_Struct.WeekDay = 0x02; + Time_Struct.SubSeconds = 0; + RTC_SetTime(&Time_Struct, RTC_ACCURATE); + } + + /* Alarm: 10:20:10 100ms */ + RTC_AlarmStruct.AlarmHours = 0x10; + RTC_AlarmStruct.AlarmMinutes = 0x10; + RTC_AlarmStruct.AlarmSeconds = 0x20; + RTC_AlarmStruct.AlarmSubSeconds = 0x100; + RTC_SetAlarm(&RTC_AlarmStruct, RTC_ACCURATE); + + /* Configure RTC Alarm sleep wakeup source */ + PMU_SleepWKUSRCConfig_RTC(PMU_RTCEVT_ALARM, 0); + + /* Enable RTC Alarm */ + RTC_AlarmCmd(ENABLE); + + test_success = 1; + + printf("========================\r\n"); + Print_CurrentTime(); + + WDT_Disable(); + if(PMU_EnterSleepMode() == 0) + { + printf("Wake up!\r\n"); + } + else + { + printf("MODE is low, Error!\r\n"); + } + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/target_isr.c new file mode 100644 index 0000000000..3dd39b4592 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern void Print_CurrentTime(void); + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ + RTC_ClearINTStatus(RTC_INTSTS_ALARM); + Stdio_Init(); + Print_CurrentTime(); + +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/RTC/RTC_SubSecAlarm/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..1f306b70c2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/template.uvoptx @@ -0,0 +1,656 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 126 + 1 +
2858
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\main.c + + \\template\../Src/main.c\126 + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..c7323fc8dd --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 211 + 211 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/main.c new file mode 100644 index 0000000000..41226590ef --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/main.c @@ -0,0 +1,235 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +const unsigned int nCrcTab_Crc32Poly0x4C11DB7Ref1[256] = +{ + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D, +}; + +const uint8_t SelfTest_Table[16] = \ +{ + 0x00, 0x11, 0x22, 0x33, + 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, + 0xCC, 0xDD, 0xEE, 0xFF +}; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief CRC-32 Calculation. + */ +static unsigned int nCrc32Calculation(const unsigned char *data, \ + unsigned int length, \ + unsigned int poly, \ + unsigned int init, \ + unsigned int xorout, \ + unsigned char reversed) +{ + unsigned int crc = init; + unsigned char i; + + if (reversed == 0) + { + while (length--) + { + crc ^= *data << 24; + data++; + for (i=0; i<8; ++i) + { + if (crc & 0x80000000) + crc = (crc << 1) ^ poly; + else + crc <<= 1; + } + } + } + else + { + poly = (poly & 0x55555555) << 1 | (poly & 0xAAAAAAAA) >> 1; + poly = (poly & 0x33333333) << 2 | (poly & 0xCCCCCCCC) >> 2; + poly = (poly & 0x0F0F0F0F) << 4 | (poly & 0xF0F0F0F0) >> 4; + poly = (poly & 0x00FF00FF) << 8 | (poly & 0xFF00FF00) >> 8; + poly = (poly & 0x0000FFFF) << 16 | (poly & 0xFFFF0000) >> 16; + while (length--) + { + crc ^= *data++; + for (i=0; i<8; ++i) + { + if (crc & 0x00000001) + crc = (crc >> 1) ^ poly; + else + crc = (crc >> 1); + } + } + } + + crc ^= xorout; + return crc; +} +/** + * @brief CRC-32 Calculation by table. + */ +unsigned int nCrc32CalculationByTab(const unsigned char* data, unsigned int length) +{ + unsigned int crc = 0xFFFFFFFF; + unsigned int i; + + for(i=0; i>8)^nCrcTab_Crc32Poly0x4C11DB7Ref1[(crc&0xFF)^(*data)]; + data++; + } + crc = crc^0xFFFFFFFF; + + return crc; +} +/** + * @brief Verify Flash(programmed) CRC-32 value. + * @retval 0: Function succeeded. + * 1: Programmed Flash size error. + * 2: CRC-32 vlaue error. + */ +static unsigned int VerifyFlashProCRC32(void) +{ + uint32_t flash_len, flash_crc32; + uint32_t crc32; + + /* Get CRC-32 informations from flash */ + flash_len = *((__IO uint32_t *)(0x7FFF8)); + flash_crc32 = *((__IO uint32_t *)(0x7FFFC)); + + /* Error: flash_len > Flash max-size */ + if (flash_len > (512*1024)) + { + return 1; + } + + /* Calculate CRC-32 value */ + //crc32 = nCrc32Calculation((const unsigned char *)0, flash_len, 0x04C11DB7, 0xFFFFFFFF, 0xFFFFFFFF, 1); + crc32 = nCrc32CalculationByTab((const unsigned char *)0, flash_len); + if (crc32 != flash_crc32) + { + return 2; + } + + return 0; +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + uint32_t crc32_value, retval; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* CRC-32 self-test */ + crc32_value = nCrc32Calculation(SelfTest_Table, 16, 0x04C11DB7, 0xFFFFFFFF, 0xFFFFFFFF, 1); + if (crc32_value == 0x8407759B) + printf("CRC-32 Calculation self-test passed\r\n"); + else + printf("CRC-32 Calculation self-test failed\r\n"); + + /* Verify Flash(programmed) CRC-32 value */ + retval = VerifyFlashProCRC32(); + if (retval == 0) + { + printf("Verify CRC-32 passed\r\n"); + } + else if (retval == 1) + { + printf("Programmed Flash size error\r\n"); + } + else + { + printf("CRC-32 value error\r\n"); + } + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SD612/SD612_CRC_Test/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/.project new file mode 100644 index 0000000000..f551f59e3c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/.project @@ -0,0 +1,188 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/FM25Q32.c + 1 + PARENT-2-PROJECT_LOC/Src/FM25Q32.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.ewp new file mode 100644 index 0000000000..eb77edb3ce --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.ewp @@ -0,0 +1,2010 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Src\FM25Q32.c + + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/FM25Q32.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/FM25Q32.h new file mode 100644 index 0000000000..c78dede2f9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/FM25Q32.h @@ -0,0 +1,65 @@ + +#ifndef __FM25Q32 +#define __FM25Q32 + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +extern __IO uint32_t nTicks; + +// SPIx be used +#define SPI_Flash SPI3 + +#define CSN_GPIO GPIOD +#define CSN_GPIO_DAT GPIO_D +#define CSN_Pin GPIO_Pin_4 +#define CSN_PinNum 4 + +//FM25Q command +#define FM25Q_WriteEnable 0x06 +#define FM25Q_WriteDisable 0x04 +#define FM25Q_ReadStatusReg_1 0x05 +#define FM25Q_ReadStatusReg_2 0x35 +#define FM25Q_Volatile_SR_WriteEnable 0x50 +#define FM25Q_WriteStatusReg 0x01 +#define FM25Q_SectorErase_4KB 0x20 +#define FM25Q_BlockErase_32KB 0x52 +#define FM25Q_BlockErase_64KB 0xD8 +#define FM25Q_ChipErase 0xC7 +#define FM25Q_ReadData 0x03 +#define FM25Q_PageProgram 0x02 + +void FlashMemory_Test(void); + + +uint32_t System_GetTick(void); +void FlashMem_SPI_Init(void); +void FlashMem_SPI_DeInit(void); +void FlashMem_SPI_SetCSN(uint8_t level); +int32_t FlashMem_SPI_Transfer(uint8_t *w_data, uint8_t *r_data, uint32_t len, uint32_t Timeout); + +int32_t FlashMem_WriteEnable(void); +int32_t FlashMem_WriteDisable(void); + +int32_t FlashMem_WaitForIdle(uint32_t Tickstart, uint32_t Timeout); + +int32_t FlashMem_ReadStaReg_1(uint8_t *data); +int32_t FlashMem_ReadStaReg_2(uint8_t *data); +int32_t FlashMem_WriteStaReg(uint8_t StaReg1, uint8_t StaReg2); + +int32_t FlashMem_SectorErase_4KB(uint32_t addr); +int32_t FlashMem_BlockErase_32KB(uint32_t addr); +int32_t FlashMem_BlockErase_64KB(uint32_t addr); +int32_t FlashMem_ChipErase(void); + +int32_t FlashMem_Read(uint8_t *data, uint32_t addr, uint16_t num, uint32_t Timeout); +int32_t FlashMem_PageWrite(uint8_t *data, uint32_t addr, uint16_t num, uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __FM25Q32 */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/main.h new file mode 100644 index 0000000000..4c06a51a46 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/main.h @@ -0,0 +1,29 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include +#include "FM25Q32.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..f59ce08361 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/template.uvoptx @@ -0,0 +1,633 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\Src\FM25Q32.c + FM25Q32.c + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 6 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 32 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..9fa4598091 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARM/template.uvprojx @@ -0,0 +1,639 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + FM25Q32.c + 1 + ..\Src\FM25Q32.c + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..40bd6a62d8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/template.uvopt @@ -0,0 +1,721 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 141 + 141 + 0 + ..\Src\FM25Q32.c + FM25Q32.c + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 6 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..bd63d6fc61 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/MDK-ARMv4/template.uvproj @@ -0,0 +1,589 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + FM25Q32.c + 1 + ..\Src\FM25Q32.c + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/FM25Q32.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/FM25Q32.c new file mode 100644 index 0000000000..bb754caed1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/FM25Q32.c @@ -0,0 +1,723 @@ +/** + ****************************************************************************** + * @file FM25Q32.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +#include "FM25Q32.h" +#include + +__IO uint32_t nTicks; + +/** + * @brief Get current ticks. + * @param None + * @retval None + */ +uint32_t System_GetTick(void) +{ + return nTicks; +} + +/** + * @brief SPI initialization for flash memory device. + * @param None + * @retval None + */ +void FlashMem_SPI_Init(void) +{ + SPI_InitType SPI_InitStruct; + GPIO_InitType GPIO_InitStruct; + + CORTEX_SystemTick_Config(26214400/1000 - 1); + + /* CSN pin output high */ + GPIO_WriteBit(CSN_GPIO_DAT, CSN_PinNum, 1); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = CSN_Pin; + GPIOBToF_Init(CSN_GPIO, &GPIO_InitStruct); + + SPI_DeviceInit(SPI_Flash); + SPI_StructInit(&SPI_InitStruct); + SPI_InitStruct.ClockDivision = SPI_CLKDIV_2; + SPI_InitStruct.CSNSoft = SPI_CSNSOFT_ENABLE; + SPI_Init(SPI_Flash, &SPI_InitStruct); + + SPI_Cmd(SPI_Flash, ENABLE); +} + +/** + * @brief SPI De-Initialization for flash memory device. + * @param None + * @retval None + */ +void FlashMem_SPI_DeInit(void) +{ + GPIO_InitType GPIO_InitStruct; + + SysTick->CTRL = 0; + + SPI_DeviceInit(SPI_Flash); + + /* CSN pin forbidden */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = CSN_Pin; + GPIOBToF_Init(CSN_GPIO, &GPIO_InitStruct); +} + +/** + * @brief SPI configure CSN pin. + */ +void FlashMem_SPI_SetCSN(uint8_t level) +{ + if (level) GPIO_WriteBit(CSN_GPIO_DAT, CSN_PinNum, 1); + else GPIO_WriteBit(CSN_GPIO_DAT, CSN_PinNum, 0); +} + +/** + * @brief SPI transfer + * @param + * @retval + */ +int32_t FlashMem_SPI_Transfer(uint8_t *w_data, uint8_t *r_data, uint32_t len, uint32_t Timeout) +{ + uint32_t tick_cur, Tickstart; + uint32_t i; + + Tickstart = System_GetTick(); + + for (i=0; i= Tickstart) + { + if ((tick_cur-Tickstart) > Timeout) return -1; + } + else + { + if ((0xFFFFFFFFUL-Tickstart+tick_cur) > Timeout) return -1; + } + } + } + if (w_data == NULL) + SPI_SendData(SPI_Flash, 0x00); + else + SPI_SendData(SPI_Flash, w_data[i]); + + /* Wait until receive FIFO is not empty, receive one byte data */ + while (SPI_GetStatus(SPI_Flash, SPI_STS_RNE) == 0U) + { + if (Timeout == 0UL) return -1; + else + { + tick_cur = System_GetTick(); + if (tick_cur >= Tickstart) + { + if ((tick_cur-Tickstart) > Timeout) return -1; + } + else + { + if ((0xFFFFFFFFUL-Tickstart+tick_cur) > Timeout) return -1; + } + } + } + if (r_data == NULL) + SPI_ReceiveData(SPI_Flash); + else + r_data[i] = SPI_ReceiveData(SPI_Flash); + } + + while (SPI_GetStatus(SPI_Flash, SPI_STS_BSY) == 1U) + { + if (Timeout == 0UL) return -1; + else + { + tick_cur = System_GetTick(); + if (tick_cur >= Tickstart) + { + if ((tick_cur-Tickstart) > Timeout) return -1; + } + else + { + if ((0xFFFFFFFFUL-Tickstart+tick_cur) > Timeout) return -1; + } + } + } + + return 0; +} + +/** + * @brief Write enable + * @param None + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_WriteEnable(void) +{ + uint8_t tmp; + int32_t retval; + + tmp = FM25Q_WriteEnable; + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(&tmp, NULL, 1, 2); + FlashMem_SPI_SetCSN(1); + + return retval; +} + +/** + * @brief Write disbale + * @param None + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_WriteDisable(void) +{ + uint8_t tmp; + int32_t retval; + + tmp = FM25Q_WriteDisable; + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(&tmp, NULL, 1, 2); + FlashMem_SPI_SetCSN(1); + + return retval; +} + +/** + * @brief Read status register 1 + * @param [out]data: The pointer of read data + * @note S7 S6 S5 S4 S3 S2 S1 S0 + * SRP0 SEC TB BP2 BP1 BP0 WEL WIP + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_ReadStaReg_1(uint8_t *data) +{ + uint8_t wBuffer[2] = { FM25Q_ReadStatusReg_1, 0x00 }; + uint8_t rBuffer[2]; + int32_t retval; + + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, rBuffer, 2, 2); + FlashMem_SPI_SetCSN(1); + + *data = rBuffer[1]; + return retval; +} + +/** + * @brief Read status register 2 + * @param [out]data: The pointer of read data + * @note S15 S14 S13 S12 S11 S10 S9 S8 + * SUS CMP LB3 LB2 LB1 LB0 QE SRP1 + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_ReadStaReg_2(uint8_t *data) +{ + uint8_t wBuffer[2] = { FM25Q_ReadStatusReg_2, 0x00 }; + uint8_t rBuffer[2]; + int32_t retval; + + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, rBuffer, 2, 2); + FlashMem_SPI_SetCSN(1); + + *data = rBuffer[1]; + return retval; +} + +/** + * @brief Wait for idle + */ +int32_t FlashMem_WaitForIdle(uint32_t Tickstart, uint32_t Timeout) +{ + uint8_t data; + uint32_t tick_cur; + + do + { + FlashMem_ReadStaReg_1(&data); + + if (Timeout == 0UL) + { + return -1; + } + else + { + tick_cur = System_GetTick(); + if (tick_cur >= Tickstart) + { + if ((tick_cur-Tickstart) > Timeout) + { + return -1; + } + } + else + { + if ((0xFFFFFFFFUL-Tickstart+tick_cur) > Timeout) + { + return -1; + } + } + } + + } while((data & 0x01) == 0x01); + + return 0; +} + +/** + * @brief Write status register 1 and 2 + * @param StaReg1: The value write status register 1 + * StaReg2: The value write status register 2 + * @note register 1 + * S7 S6 S5 S4 S3 S2 S1 S0 + * SRP0 SEC TB BP2 BP1 BP0 WEL WIP + * register 2 + * S15 S14 S13 S12 S11 S10 S9 S8 + * SUS CMP LB3 LB2 LB1 LB0 QE SRP1 + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_WriteStaReg(uint8_t StaReg1, uint8_t StaReg2) +{ + int32_t retval; + uint8_t wBuffer[3]; + uint32_t Tickstart; + + retval = FlashMem_WriteEnable(); + if (retval) return retval; + + wBuffer[0] = FM25Q_Volatile_SR_WriteEnable; + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 1, 2); + FlashMem_SPI_SetCSN(1); + if (retval) return retval; + + wBuffer[0] = FM25Q_WriteStatusReg; + wBuffer[1] = StaReg1; + wBuffer[2] = StaReg2; + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 3, 2); + FlashMem_SPI_SetCSN(1); + if (retval) return retval; + + Tickstart = System_GetTick(); + return FlashMem_WaitForIdle(Tickstart, 2); +} + +/** + * @brief Sector erase(4K-bytes) + * @param addr: The address of specified sector to the erased state of all 1s + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_SectorErase_4KB(uint32_t addr) +{ + int32_t retval; + uint8_t wBuffer[4]; + uint32_t Tickstart; + + retval = FlashMem_WriteEnable(); + if (retval) return retval; + + wBuffer[0] = FM25Q_SectorErase_4KB; + wBuffer[1] = (uint8_t)(addr>>16); + wBuffer[2] = (uint8_t)(addr>>8); + wBuffer[3] = (uint8_t)(addr); + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 4, 2); + FlashMem_SPI_SetCSN(1); + if (retval) return retval; + + Tickstart = System_GetTick(); + return FlashMem_WaitForIdle(Tickstart, 300); +} + +/** + * @brief Block erase(32K-bytes) + * @param addr: The address of specified block to the erased state of all 1s + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_BlockErase_32KB(uint32_t addr) +{ + int32_t retval; + uint8_t wBuffer[4]; + uint32_t Tickstart; + + retval = FlashMem_WriteEnable(); + if (retval) return retval; + + wBuffer[0] = FM25Q_BlockErase_32KB; + wBuffer[1] = (uint8_t)(addr>>16); + wBuffer[2] = (uint8_t)(addr>>8); + wBuffer[3] = (uint8_t)(addr); + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 4, 2); + FlashMem_SPI_SetCSN(1); + if (retval) return retval; + + Tickstart = System_GetTick(); + return FlashMem_WaitForIdle(Tickstart, 1800); +} + +/** + * @brief Block erase(64K-bytes) + * @param addr: The address of specified block to the erased state of all 1s + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_BlockErase_64KB(uint32_t addr) +{ + int32_t retval; + uint8_t wBuffer[4]; + uint32_t Tickstart; + + retval = FlashMem_WriteEnable(); + if (retval) return retval; + + wBuffer[0] = FM25Q_BlockErase_64KB; + wBuffer[1] = (uint8_t)(addr>>16); + wBuffer[2] = (uint8_t)(addr>>8); + wBuffer[3] = (uint8_t)(addr); + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 4, 2); + FlashMem_SPI_SetCSN(1); + if (retval) return retval; + + Tickstart = System_GetTick(); + return FlashMem_WaitForIdle(Tickstart, 2000); +} + +/** + * @brief Chip erase + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_ChipErase(void) +{ + int32_t retval; + uint8_t wBuffer; + uint32_t Tickstart; + + retval = FlashMem_WriteEnable(); + if (retval) return retval; + + wBuffer = FM25Q_ChipErase; + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(&wBuffer, NULL, 1, 2); + FlashMem_SPI_SetCSN(1); + if (retval) return retval; + + Tickstart = System_GetTick(); + return FlashMem_WaitForIdle(Tickstart, 128000); +} + +/** + * @brief Read + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_Read(uint8_t *data, uint32_t addr, uint16_t num, uint32_t Timeout) +{ + int32_t retval; + uint8_t wBuffer[4]; + + wBuffer[0] = FM25Q_ReadData; + wBuffer[1] = (uint8_t)(addr>>16); + wBuffer[2] = (uint8_t)(addr>>8); + wBuffer[3] = (uint8_t)(addr); + + FlashMem_SPI_SetCSN(0); + + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 4, 2); + if (retval) + { + FlashMem_SPI_SetCSN(1); + return retval; + } + + retval = FlashMem_SPI_Transfer(NULL, data, num, Timeout); + FlashMem_SPI_SetCSN(1); + + return retval; +} + +/** + * @brief Page write + * @note This function allows from one byte to 256 bytes (a page) of data to be + * programmed at previously erased (FFh) memory locations + * @retval ARM_DRIVER_OK or Error code(<0) + */ +int32_t FlashMem_PageWrite(uint8_t *data, uint32_t addr, uint16_t num, uint32_t Timeout) +{ + int32_t retval; + uint8_t wBuffer[4]; + uint32_t Tickstart; + + retval = FlashMem_WriteEnable(); + if (retval) return retval; + + wBuffer[0] = FM25Q_PageProgram; + wBuffer[1] = (uint8_t)(addr>>16); + wBuffer[2] = (uint8_t)(addr>>8); + wBuffer[3] = (uint8_t)(addr); + + FlashMem_SPI_SetCSN(0); + retval = FlashMem_SPI_Transfer(wBuffer, NULL, 4, 2); + if (retval) + { + FlashMem_SPI_SetCSN(1); + return retval; + } + + retval = FlashMem_SPI_Transfer(data, NULL, num, 5); + FlashMem_SPI_SetCSN(1); + + if (retval) return retval; + + Tickstart = System_GetTick(); + return FlashMem_WaitForIdle(Tickstart, Timeout); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Error_Handler + */ +void Error_Handler(void) +{ + printf("Errors ocuur!!!\r\n"); + while (1); +} + +uint8_t rData[1024]; +uint8_t wData[1024]; + +/** + * @brief This is a flash memory device test program + */ +void FlashMemory_Test(void) +{ + int32_t retval; + uint32_t i, j; + __IO uint8_t err; + uint32_t Start_Addr; + + /* SPI clock is 6553600 */ + FlashMem_SPI_Init(); + + for (i=0; i<1024; i++) + wData[i] = (uint8_t)(0x33); + + /*- Sector Erase ------------------------------------------------------------------------------------------*/ + Start_Addr = 5*4096; + retval = FlashMem_SectorErase_4KB(Start_Addr); + if (retval) Error_Handler(); + + err = 0; + for (i=0; i<4; i++) + { + retval = FlashMem_Read(rData, 1024*i+Start_Addr, 1024, 15); + if (retval) Error_Handler(); + + for (j=0; j<1024; j++) + { + if (rData[i] != 0xFF) + err = 1; + } + } + if (err) printf("FlashMem_SectorErase_4KB error!\r\n"); + else printf("FlashMem_SectorErase_4KB OK!\r\n"); + + /*- Page write ------------------------------------------------------------------------------------------*/ + err = 0; + retval = FlashMem_PageWrite(wData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData+256, Start_Addr+256, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData+256*2, Start_Addr+256*2, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData+256*3, Start_Addr+256*3, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 1024, 10); + if (retval) Error_Handler(); + + for (i=0; i<1024; i++) + { + if (rData[i] != wData[i]) + err = 1; + } + if (err) printf("FlashMem_PageWrite error!\r\n"); + else printf("FlashMem_PageWrite OK!\r\n"); + + /*- Sector Erase ------------------------------------------------------------------------------------------*/ + retval = FlashMem_SectorErase_4KB(Start_Addr); + if (retval) Error_Handler(); + + err = 0; + for (i=0; i<4; i++) + { + retval = FlashMem_Read(rData, 1024*i+Start_Addr, 1024, 15); + if (retval) Error_Handler(); + + for (j=0; j<1024; j++) + { + if (rData[i] != 0xFF) + err = 1; + } + } + if (err) printf("FlashMem_SectorErase_4KB error!\r\n"); + else printf("FlashMem_SectorErase_4KB OK!\r\n"); + + /*- Block Erase 32KB ------------------------------------------------------------------------------------------*/ + Start_Addr = 55*32*1024; + err = 0; + retval = FlashMem_BlockErase_32KB(Start_Addr); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData+256, Start_Addr+32*1024-256, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData+256, Start_Addr+32*1024-256, 256, 15); + if (retval) Error_Handler(); + + for (i=0; i<512; i++) + { + if (rData[i] != wData[i]) + err = 1; + } + + if (err) printf("FlashMem_BlockErase_32KB[0] error!\r\n"); + else printf("FlashMem_BlockErase_32KB[0] OK!\r\n"); + + retval = FlashMem_BlockErase_32KB(Start_Addr); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData+256, Start_Addr+32*1024-256, 256, 15); + if (retval) Error_Handler(); + + for (i=0; i<512; i++) + { + if (rData[i] != 0xFF) + err = 1; + } + + if (err) printf("FlashMem_BlockErase_32KB[1] error!\r\n"); + else printf("FlashMem_BlockErase_32KB[1] OK!\r\n"); + + /*- Block Erase 64KB ------------------------------------------------------------------------------------------*/ + Start_Addr = 13*64*1024; + err = 0; + retval = FlashMem_BlockErase_64KB(Start_Addr); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData+256, Start_Addr+64*1024-256, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 256, 10); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData+256, Start_Addr+64*1024-256, 256, 15); + if (retval) Error_Handler(); + + for (i=0; i<512; i++) + { + if (rData[i] != wData[i]) + err = 1; + } + + if (err) printf("FlashMem_BlockErase_64KB[0] error!\r\n"); + else printf("FlashMem_BlockErase_64KB[0] OK!\r\n"); + + retval = FlashMem_BlockErase_64KB(Start_Addr); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData+256, Start_Addr+64*1024-256, 256, 15); + if (retval) Error_Handler(); + + for (i=0; i<512; i++) + { + if (rData[i] != 0xFF) + err = 1; + } + + if (err) printf("FlashMem_BlockErase_64KB[1] error!\r\n"); + else printf("FlashMem_BlockErase_64KB[1] OK!\r\n"); + + /*- Chip Erase ------------------------------------------------------------------------------------------*/ + err = 0; + retval = FlashMem_ChipErase(); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_PageWrite(wData+256, Start_Addr+4*1024*1024-256, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData+256, Start_Addr+4*1024*1024-256, 256, 15); + if (retval) Error_Handler(); + + for (i=0; i<512; i++) + { + if (rData[i] != wData[i]) + err = 1; + } + + if (err) printf("FlashMem_ChipErase[0] error!\r\n"); + else printf("FlashMem_ChipErase[0] OK!\r\n"); + + + retval = FlashMem_ChipErase(); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData, Start_Addr, 256, 15); + if (retval) Error_Handler(); + + retval = FlashMem_Read(rData+256, Start_Addr+4*1024*1024-256, 256, 15); + if (retval) Error_Handler(); + + for (i=0; i<512; i++) + { + if (rData[i] != 0xFF) + err = 1; + } + + if (err) printf("FlashMem_ChipErase[1] error!\r\n"); + else printf("FlashMem_ChipErase[1] OK!\r\n"); + + + FlashMem_SPI_DeInit(); + printf("============================ Flash memory device test end! ============================\r\n"); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/main.c new file mode 100644 index 0000000000..cde9617533 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/main.c @@ -0,0 +1,89 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + test_success = 1; + + PMU_AVCCOutputCmd(ENABLE); + + /* Flash memory device test */ + printf("============================ Flash memory device test start! ============================\r\n"); + FlashMemory_Test(); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/target_isr.c new file mode 100644 index 0000000000..5f7af1af14 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + nTicks++; +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_FlashMem_FM25Q32_6MClock_TimeoutDetect/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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+ 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/main.h new file mode 100644 index 0000000000..c0b9433e44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/main.h @@ -0,0 +1,36 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#define Buffer_Size (256) + +extern __IO uint32_t Transmit_Cnt; +extern __IO uint32_t Receive_Cnt; + +extern uint8_t Transmit_Buffer[Buffer_Size]; +extern uint8_t Receive_Buffer[Buffer_Size]; + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..6adb6f1903 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..9342264cae --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 113 + 113 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/main.c new file mode 100644 index 0000000000..c664fe775a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/main.c @@ -0,0 +1,143 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ +uint32_t i; +uint8_t Transmit_Buffer[Buffer_Size]; +uint8_t Receive_Buffer[Buffer_Size]; +__IO uint32_t Transmit_Cnt; /* Increased by 1 when transmit a byte data */ +__IO uint32_t Receive_Cnt; /* Increased by 1 when receive a byte data */ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + SPI_InitType SPI_InitStruct; + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + for (i=0; i 0 */ + SPI_ReceiveFIFOLevelConfig(SPI1, SPI_RXFLEV_0); + + Transmit_Cnt = 0; + Receive_Cnt = 0; + + /* Reset SS, slave be selected, active */ + GPIO_WriteBit(GPIO_B, 6, 0); + + /*Enable SPI1*/ + SPI_Cmd(SPI1, ENABLE); + + /* Enable SPI1 transmit interrupt, enter SPI1 Interrupt Service Routine */ + SPI_INTConfig(SPI1, SPI_INT_TX, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(SPI1_IRQn, 0); + + test_success = 1; + + /* Waiting receive operation done */ + while (Receive_Cnt < Buffer_Size) + { + if(SPI_GetStatus(SPI1, SPI_STS_RNE)) + Receive_Buffer[Receive_Cnt++] = SPI_ReceiveData(SPI1); + } + + /* Set SS, slave be not selected, inactive */ + GPIO_WriteBit(GPIO_B, 6, 1); + + /* SPI resource release */ + SPI_DeviceInit(SPI1); + CORTEX_NVIC_DisableIRQ(SPI1_IRQn); + printf("SPI1 send finish!\r\n"); + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/target_isr.c new file mode 100644 index 0000000000..d40839b8b1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/target_isr.c @@ -0,0 +1,315 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ + if (SPI_GetStatus(SPI1, SPI_STS_TXIF)) + { + while ((Transmit_Cnt < Buffer_Size) && SPI_GetStatus(SPI1, SPI_STS_TNF)) + { + SPI_SendData(SPI1, Transmit_Buffer[Transmit_Cnt++]); + } + if (Transmit_Cnt == Buffer_Size) + { + SPI_INTConfig(SPI1, SPI_INT_TX, DISABLE); + } + SPI_ClearStatus(SPI1, SPI_STS_TXIF); + } +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_TransmitIT_SSUnused/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..1028c49ff5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 141 + 141 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 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+ ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/main.c new file mode 100644 index 0000000000..57ed651ec9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/main.c @@ -0,0 +1,165 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +#define CSN_GPIO GPIOB +#define CSN_GPIO_DAT GPIO_B +#define CSN_Pin GPIO_Pin_9 +#define CSN_PinNum 9 + +uint32_t Transmit_Buffer_32b[4] = { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }; +uint32_t Transmit_Buffer_16b[4] = { 0x1111, 0x2222, 0x3333, 0x4444 }; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Configure SPI CSN pin level. + * @param None + * @retval None + */ +void SPI_CSNConfig(uint8_t level) +{ + if (level) GPIO_WriteBit(CSN_GPIO_DAT, CSN_PinNum, 1); + else GPIO_WriteBit(CSN_GPIO_DAT, CSN_PinNum, 0); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + SPI_InitType SPI_InitStruct; + GPIO_InitType GPIO_InitStruct; + uint8_t i; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* CSN pin output high, inactive */ + GPIO_WriteBit(CSN_GPIO_DAT, CSN_PinNum, 1); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = CSN_Pin; + GPIOBToF_Init(CSN_GPIO, &GPIO_InitStruct); + + /* SPI1 initialization, master mode */ + SPI_DeviceInit(SPI1); + SPI_InitStruct.ClockDivision = SPI_CLKDIV_32; + SPI_InitStruct.Mode = SPI_MODE_MASTER; + SPI_InitStruct.CSNSoft = SPI_CSNSOFT_ENABLE; + SPI_InitStruct.SPH = SPI_SPH_0; + SPI_InitStruct.SPO = SPI_SPO_0; + SPI_InitStruct.SWAP = SPI_SWAP_DISABLE; + SPI_Init(SPI1, &SPI_InitStruct); + + /*Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); + + /* Send 4 32-Bits datas */ + for (i=0; i<4; i++) + { + /* CSN active */ + SPI_CSNConfig(0); + /* Loop while until TXFIFO is empty */ + while (SPI_GetStatus(SPI1, SPI_STS_TFE) == 0); + SPI_SendData(SPI1, (Transmit_Buffer_32b[i]>>24)&0xff); + SPI_SendData(SPI1, (Transmit_Buffer_32b[i]>>16)&0xff); + SPI_SendData(SPI1, (Transmit_Buffer_32b[i]>>8)&0xff); + SPI_SendData(SPI1, (Transmit_Buffer_32b[i])&0xff); + /* While loop until idle */ + while (SPI_GetStatus(SPI1, SPI_STS_BSY) == 1); + /* CSN inactive */ + SPI_CSNConfig(1); + } + printf("SPI1 send 4*32Bits datas finish!\r\n"); + + /* Send 4 16-Bits datas */ + for (i=0; i<4; i++) + { + /* CSN active */ + SPI_CSNConfig(0); + /* Loop while until TXFIFO is empty */ + while (SPI_GetStatus(SPI1, SPI_STS_TFE) == 0); + SPI_SendData(SPI1, (Transmit_Buffer_16b[i]>>8)&0xff); + SPI_SendData(SPI1, (Transmit_Buffer_16b[i])&0xff); + /* While loop until idle */ + while (SPI_GetStatus(SPI1, SPI_STS_BSY) == 1); + /* CSN inactive */ + SPI_CSNConfig(1); + } + printf("SPI1 send 4*16Bits datas finish!\r\n"); + + /* SPI1 and CSN pin release */ + SPI_DeviceInit(SPI1); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = CSN_Pin; + GPIOBToF_Init(CSN_GPIO, &GPIO_InitStruct); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/target_isr.c new file mode 100644 index 0000000000..206935d6c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SPI/SPI_Transmit_16BitsData_32BitsData/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..077860369a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 77 + 77 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/main.c new file mode 100644 index 0000000000..e441ac1f34 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/main.c @@ -0,0 +1,101 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief SysTick interrupt service. + * @param None + * @retval None + */ +void SysTick_IntService(void) +{ + GPIOB->DAT ^= GPIO_Pin_7; +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* IOB7 CMOS-Output mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + /* Enable SysTick timer and its interrupt to generate interrupt(1ms) */ + CORTEX_SystemTick_Config(26214400/1000 - 1); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/target_isr.c new file mode 100644 index 0000000000..00b5712ff1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/target_isr.c @@ -0,0 +1,306 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern void SysTick_IntService(void); +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + SysTick_IntService(); +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_24BitsBaseTimer_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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+ + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 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+ + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..517e05aeb8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 65 + 65 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/main.c new file mode 100644 index 0000000000..eff17ef56d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/main.c @@ -0,0 +1,122 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +__IO uint32_t nTick; + +/** + * @brief SysTick interrupt service. + * @param None + * @retval None + */ +void SysTick_IntService(void) +{ + nTick++; +} + +/** + * @brief Delay N ms. + * @param None + * @retval None + */ +void Delay_ms(uint32_t n) +{ + uint32_t Ticks_start; + + Ticks_start = nTick; + while ((nTick - Ticks_start) < n); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* IOB7 CMOS-Output mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + /* Enable SysTick timer and its interrupt to generate interrupt(1ms) */ + CORTEX_SystemTick_Config(26214400/1000 - 1); + + test_success = 1; + + while (1) + { + /* Toggle IOB7, 5ms */ + Delay_ms(5); + GPIO_WriteBit(GPIO_B, 7, 1); + Delay_ms(5); + GPIO_WriteBit(GPIO_B, 7, 0); + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/target_isr.c new file mode 100644 index 0000000000..6dad605ee0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/target_isr.c @@ -0,0 +1,307 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern __IO uint32_t nTick; +extern void SysTick_IntService(void); + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + SysTick_IntService(); +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..a2f48e09a4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/template.uvoptx @@ -0,0 +1,639 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 1 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 1 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..d82341b33d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARM/template.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 12 + + + + + + ..\..\..\test.ini + + + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..c386f78345 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 61 + 61 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/main.c new file mode 100644 index 0000000000..baddfedcd0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/main.c @@ -0,0 +1,117 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Delay N system-clock cycle. + * @param nClock < 0x1000000 + * @retval None + */ +void Delay_nSysClock(__IO uint32_t nClock) +{ + uint32_t tmp; + + SysTick->LOAD = nClock - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \ + |SysTick_CTRL_ENABLE_Msk; + + do + { + tmp = SysTick->CTRL; + } + while (!(tmp & SysTick_CTRL_COUNTFLAG_Msk)); + + SysTick->CTRL = 0; +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* IOB7 CMOS-Output mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + test_success = 1; + + while (1) + { + /* Toggle IOB7, 10ms */ + Delay_nSysClock(26214400/100); + GPIO_WriteBit(GPIO_B, 7, 1); + Delay_nSysClock(26214400/100); + GPIO_WriteBit(GPIO_B, 7, 0); + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/target_isr.c new file mode 100644 index 0000000000..d700a63a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/target_isr.c @@ -0,0 +1,303 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/SysTick/SysTick_Delay_Polling/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..f3c82d1f38 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 83 + 83 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/main.c new file mode 100644 index 0000000000..167c5452a2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/main.c @@ -0,0 +1,107 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + TMR_InitType TMR_InitStruct; + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* IOB7, CMOS output mode, output low */ + GPIO_WriteBit(GPIO_B, 7, 0); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + /* Timer0 initialization: + - Clock source: internal clock(APB clock 13107200Hz) + - Overflow interval: 10ms */ + TMR_DeInit(TMR0); + TMR_InitStruct.ClockSource = TMR_CLKSRC_INTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 13107200/100 - 1; + TMR_Init(TMR0, &TMR_InitStruct); + + /* Enable Timer0 interrupt */ + TMR_INTConfig(TMR0, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(TMR0_IRQn, 0); + + /* Enable Timer0 */ + TMR_Cmd(TMR0, ENABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/target_isr.c new file mode 100644 index 0000000000..5f30538fda --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ + if (TMR_GetINTStatus(TMR0)) + { + TMR_ClearINTStatus(TMR0); + /* Toggle IOB7 */ + GPIO_WriteBit(GPIO_B, 7, !GPIOBToF_ReadOutputDataBit(GPIOB, GPIO_Pin_7)); + } +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_32BitsBaseTimer_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..7f3b2bc20f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/main.c new file mode 100644 index 0000000000..fdfc3ad811 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/main.c @@ -0,0 +1,112 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + TMR_InitType TMR_InitStruct; + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* Toggle IOB7 in interrupt, CMOS output mode, output low */ + GPIO_WriteBit(GPIO_B, 7, 0); + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + /* Timer external clock input pin(IOB15), input mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15; + GPIOBToF_Init(GPIOB, &GPIO_InitStruct); + + /* Timer0 initialization: + - Clock source: external clock + - Overflow interval: (4+1)/(external clock) */ + TMR_DeInit(TMR0); + TMR_InitStruct.ClockSource = TMR_CLKSRC_EXTERNAL; + TMR_InitStruct.EXTGT = TMR_EXTGT_DISABLE; + TMR_InitStruct.Period = 5 - 1; + TMR_Init(TMR0, &TMR_InitStruct); + + /* Enable Timer0 interrupt */ + TMR_INTConfig(TMR0, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(TMR0_IRQn, 0); + + /* Enable Timer0 */ + TMR_Cmd(TMR0, ENABLE); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/target_isr.c new file mode 100644 index 0000000000..25e0f8dee3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/target_isr.c @@ -0,0 +1,310 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ + if (TMR_GetINTStatus(TMR0)) + { + TMR_ClearINTStatus(TMR0); + /* Toggle IOB7 */ + GPIO_WriteBit(GPIO_B, 7, !GPIOBToF_ReadOutputDataBit(GPIOB, GPIO_Pin_7)); + } +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TIMER/TMR_ExternalClockSource_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.ewd @@ -0,0 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+ + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM 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+ + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/lib_conf.h new file mode 100644 index 0000000000..1016be9f02 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/lib_conf.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..7dee5a1e23 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 93 + 93 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 48 + 48 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/main.c new file mode 100644 index 0000000000..79527a2dde --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/main.c @@ -0,0 +1,135 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; +volatile uint32_t g_nCount; +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + TADCInitType TADC_InitStruct; + GPIO_InitType GPIO_InitStruct; + uint32_t i; + + test_success = 0; + + g_nCount = 0; + + Clock_Init(); + Stdio_Init(); + printf("ADCTiny test. \r\n"); + + TADC_INTConfig(DISABLE); + + /* Forbidden Tiny ADC input pin, IOE6 */ + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIOBToF_Init(GPIOE, &GPIO_InitStruct); + + /* Tiny ADC initialization */ + TADC_DeInit(); + TADC_InitStruct.SignalSel = ADCTINY_SIGNALSEL_IOE6; + TADC_InitStruct.ADTREF1 = ADCTINY_REF1_0_9; + TADC_InitStruct.ADTREF2 = ADCTINY_REF2_1_8; + TADC_InitStruct.ADTREF3 = ADCTINY_REF3_2_7; + TADC_Init(&TADC_InitStruct); + + + /* Enable Tiny ADC */ + TADC_Cmd(ENABLE); + for(i=0; i<800; i++) + { + __NOP(); + } + + TADC_IntTHConfig(ADCTINY_THSEL_1); + for(i=0; i<800; i++) + { + __NOP(); + } + TADC_ClearINTStatus(); + TADC_INTConfig(ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(ANA_IRQn, 3); + + test_success = 1; + + while(1) + { + WDT_Disable(); + Stdio_Init(); + printf("Tiny ADC interrupt, nCount: %d\r\n", (int32_t)g_nCount); + printf("CMPOUT: %d. \r\n", TADC_GetOutput()); + // CORTEX_Delay_nSysClock(26214400/2); + if (PMU_EnterSleepMode()) + { + printf("Current mode is debug mode, failed\r\n"); + } + else + { + printf("Quit sleep mode\r\n"); + } + } + +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/target_isr.c new file mode 100644 index 0000000000..af9bbd985a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/target_isr.c @@ -0,0 +1,309 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern volatile uint32_t g_nCount; +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ + if (TADC_GetINTStatus()) + { + g_nCount++; + TADC_ClearINTStatus(); + } +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/TinyADC/TinyADC/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..864f6d83a0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 67 + 67 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/main.c new file mode 100644 index 0000000000..5d6092ef79 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/main.c @@ -0,0 +1,91 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* How to use printf() via UART. + Compiler Compiler-symbol Description + MDK_ARM __CC_ARM Selects [Use MicroLib], use fputc() to support + EWARM __ICCARM__ Selects [Full] in [Library configuration]->[Library], use fputc() to support + Eclipse __GNUC__ Selects [Do not use syscalls](--specs=nosys.specs), use _write() to support + */ + printf("printf to UART OK!!!\r\n"); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_StdPrint/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..4ff0bbdb69 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 81 + 81 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/main.c new file mode 100644 index 0000000000..2b292d197c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/main.c @@ -0,0 +1,105 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +int i; +uint8_t Transmit_Buffer[4] = { 0x12, 0x34, 0x56, 0x78 }; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + UART_InitType UART_InitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + + /* UART0 initialization */ + UART_DeInit(UART0); + UART_InitStruct.Baudrate = 300; + UART_InitStruct.FirstBit = UART_FIRSTBIT_LSB; + UART_InitStruct.Mode = UART_MODE_TX; + UART_InitStruct.Parity = UART_PARITY_ODD; + UART_Init(UART0, &UART_InitStruct); + + for (i=0; i<4; i++) + { + UART_SendData(UART0, Transmit_Buffer[i]); + while (UART_GetFlag(UART0, UART_FLAG_TXDONE) == 0U); + UART_ClearFlag(UART0, UART_FLAG_TXDONE); + } + + printf("UART0 send(300bps) datas finish!\r\n"); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_300bps/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 0 + + + + + + + + + IJET_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 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$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..2d0cd6f6c2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,638 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 88 + 1 +
4694
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\Src\main.c + + \\template\../Src/main.c\88 + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..35b81dcfdd --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 98 + 98 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/main.c new file mode 100644 index 0000000000..0568f07dc1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/main.c @@ -0,0 +1,122 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + + +/* Private functions ---------------------------------------------------------*/ +uint8_t TX_Buffer[4] = { 0x12, 0x34, 0x56, 0x78 }; +uint32_t nTXLen; +uint8_t RX_Buffer[4] = { 0x00, 0x00, 0x00, 0x00 }; +uint32_t nRXLen; +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + UART_InitType UART_InitStruct; + uint32_t i; + + test_success = 0; + nTXLen = 0; + nRXLen = 0; + + Clock_Init(); + Stdio_Init(); + + /* UART0 initialization */ + UART_DeInit(UART0); + UART_InitStruct.Baudrate = 9600; + UART_InitStruct.FirstBit = UART_FIRSTBIT_LSB; + UART_InitStruct.Mode = UART_MODE_TX|UART_MODE_RX; + UART_InitStruct.Parity = UART_PARITY_ODD; + UART_Init(UART0, &UART_InitStruct); + + UART_INTConfig(UART0,UART_INT_TXDONE, ENABLE); + UART_INTConfig(UART0,UART_INT_RX, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(UART0_IRQn, 0); + + UART_SendData(UART0, TX_Buffer[0]); + nTXLen++; + + while(nTXLen<4) + { + WDT_Clear(); + } + + printf("UART0 send datas finish!\r\n"); + + test_success = 1; + + for(i=0; i<4; i++) + { + if(TX_Buffer[i] != RX_Buffer[i]) + { + printf("UART0 Receive datas error!\r\n"); + } + } + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/target_isr.c new file mode 100644 index 0000000000..9aa8646e5c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/target_isr.c @@ -0,0 +1,328 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +extern uint8_t TX_Buffer[4]; +extern uint32_t nTXLen; +extern uint8_t RX_Buffer[4]; +extern uint32_t nRXLen; +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ + if(UART_GetINTStatus(UART0,UART_INTSTS_TXDONE)) + { + UART_ClearINTStatus(UART0,UART_INTSTS_TXDONE); + + if(nTXLen<4) + { + UART_SendData(UART0, TX_Buffer[nTXLen]); + nTXLen++; + } + } + if(UART_GetINTStatus(UART0,UART_INTSTS_RX)) + { + UART_ClearINTStatus(UART0,UART_INTSTS_RX); + + if(nRXLen<4) + { + RX_Buffer[nRXLen] = UART_ReceiveData(UART0); + nRXLen++; + } + } +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Tranmit_IT/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..821a7784ba --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 71 + 71 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/main.c new file mode 100644 index 0000000000..69322e588f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/main.c @@ -0,0 +1,95 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + UART_InitType UART_InitStruct; + + test_success = 0; + + Clock_Init(); + + /* UART5 initialization */ + UART_DeInit(UART5); + UART_InitStruct.Baudrate = 4800; + UART_InitStruct.FirstBit = UART_FIRSTBIT_LSB; + UART_InitStruct.Mode = UART_MODE_TX; + UART_InitStruct.Parity = UART_PARITY_ODD; + UART_Init(UART5, &UART_InitStruct); + + /* Send data 0x55 */ + UART_SendData(UART5, 0x55); + + test_success = 1; + + while (1) + { + WDT_Clear(); + } +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/target_isr.c new file mode 100644 index 0000000000..1960a41dec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/target_isr.c @@ -0,0 +1,304 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART/UART_Transmit_IrDA/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/main.h new file mode 100644 index 0000000000..8b3102180a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/main.h @@ -0,0 +1,32 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#define Buffer_Size (4) + +extern __IO uint32_t Receive_Cnt; +extern uint8_t Receive_Buffer[Buffer_Size]; + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..7f3b2bc20f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 88 + 88 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Src/main.c new file mode 100644 index 0000000000..1704ff2a2a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_Receive_IT/Src/main.c @@ -0,0 +1,127 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +int i; +__IO uint32_t Receive_Cnt; /* Increased by 1 when receive a byte data */ +uint8_t Receive_Buffer[Buffer_Size]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + U32K_InitType U32K_InitStruct; + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + UART5->BAUDDIV = CLK_GetPCLKFreq()/9600; + UART5->CTRL = UART_CTRL_TXEN; + + /* U32K0 receive line RX0(IOA12), input mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_12; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + /* U32K0 initialization */ + U32K_DeInit(U32K0); + U32K_InitStruct.AutoCal = U32K_AUTOCAL_ON; + U32K_InitStruct.Debsel = U32K_DEBSEL_0; + U32K_InitStruct.Baudrate = 9600; + U32K_InitStruct.FirstBit = U32K_FIRSTBIT_LSB; + U32K_InitStruct.LineSel = U32K_LINE_RX0; + U32K_InitStruct.Parity = U32K_PARITY_EVEN; + U32K_Init(U32K0, &U32K_InitStruct); + + /* Enable U32K0 receive interrupt */ + U32K_INTConfig(U32K0, U32K_INT_RX, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(U32K0_IRQn, 0); + + /* Enable U32K0 */ + Receive_Cnt = 0; + U32K_Cmd(U32K0, ENABLE); + + test_success = 1; + + while (Receive_Cnt < Buffer_Size); + + /* U32K0 resource release */ + U32K_DeInit(U32K0); + CORTEX_NVIC_DisableIRQ(U32K0_IRQn); + /* U32K0 receive line RX0(IOA12), forbidden mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_12; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + for (i=0; i +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ 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$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.ewp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.ewp new file mode 100644 index 0000000000..d26f9ac566 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.ewp @@ -0,0 +1,2007 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + EWARM + + $PROJ_DIR$\startup_target.s + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + FWLib + + Device + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + $PROJ_DIR$\..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/main.h new file mode 100644 index 0000000000..4fc7d7f091 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/main.h @@ -0,0 +1,33 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#define Buffer_MaxSize (64) + +extern __IO uint32_t Receive_Done; +extern __IO uint32_t Receive_Cnt; /* Increased by 1 when receive a byte data */ +extern uint8_t Receive_Buffer[Buffer_MaxSize]; + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#ifndef __V_STDIO_H +#define __V_STDIO_H + +#include +#include "lib_clk.h" + +void Stdio_Init(void); + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..9ea487fcb6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/template.uvoptx @@ -0,0 +1,621 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3cc6e900a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARM/template.uvprojx @@ -0,0 +1,634 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.0.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..ab3bade849 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000021C216BB -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 107 + 107 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 104 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 53 + 53 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Src/main.c new file mode 100644 index 0000000000..9f5724fff0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Examples/UART32K/U32K_WakeUpSleep/Src/main.c @@ -0,0 +1,151 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +volatile unsigned char test_success; + +/* Private functions ---------------------------------------------------------*/ + +int i; +__IO uint32_t Receive_Done; +__IO uint32_t Receive_Cnt; /* Increased by 1 when receive a byte data */ +uint8_t Receive_Buffer[Buffer_MaxSize]; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_6_5MRC; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + U32K_InitType U32K_InitStruct; + GPIO_InitType GPIO_InitStruct; + + test_success = 0; + + Clock_Init(); + FLASH_CycleInit(); + + UART5->BAUDDIV = CLK_GetPCLKFreq()/9600; + UART5->CTRL = UART_CTRL_TXEN; + + /* U32K0 receive line RX0(IOA12), input mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_12; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + /* U32K0 initialization */ + U32K_DeInit(U32K0); + U32K_InitStruct.AutoCal = U32K_AUTOCAL_ON; + U32K_InitStruct.Debsel = U32K_DEBSEL_0; + U32K_InitStruct.Baudrate = 9600; + U32K_InitStruct.FirstBit = U32K_FIRSTBIT_LSB; + U32K_InitStruct.LineSel = U32K_LINE_RX0; + U32K_InitStruct.Parity = U32K_PARITY_NONE; + U32K_Init(U32K0, &U32K_InitStruct); + + /* Wake-up when when receive data */ + U32K_WKUModeConfig(U32K0, U32K_WKUMOD_RX); + + /* Enable U32K0 receive interrupt */ + U32K_INTConfig(U32K0, U32K_INT_RX, ENABLE); + CORTEX_SetPriority_ClearPending_EnableIRQ(U32K0_IRQn, 0); + + /* Enable U32K0 */ + Receive_Cnt = 0; + Receive_Done = 0; + U32K_Cmd(U32K0, ENABLE); + + test_success = 1; + + /* Disable watch dog timer */ + WDT_Disable(); + /* Enter sleep mode */ + if (PMU_EnterSleepMode()) + { + printf("Debug Mode, enter sleep mode fail.\r\n"); + } + + /* Quit sleep mode */ + + /* Waiting receive 0xFE */ + while (Receive_Done == 0) + { + WDT_Clear(); + } + + UART5->BAUDDIV = CLK_GetPCLKFreq()/9600; + UART5->CTRL = UART_CTRL_TXEN; + + /* U32K0 resource release */ + U32K_DeInit(U32K0); + CORTEX_NVIC_DisableIRQ(U32K0_IRQn); + /* U32K0 receive line RX0(IOA12), forbidden mode */ + GPIO_InitStruct.GPIO_Mode = GPIO_MODE_FORBIDDEN; + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_12; + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + for (i=0; i +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/IAR_Kill.bat b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/IAR_Kill.bat new file mode 100644 index 0000000000..a6e07b0aa7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/IAR_Kill.bat @@ -0,0 +1,8 @@ +@echo off + +del /s /a *.lst *.pbi *.cout *.pbd *.browse *.wsdt *.map *.dni *.dep *.ewt *.dbgdt *.tmp 2>nul +for /r . %%d in (.) do rd /s /q "%%d\Debug" 2>nul +for /r . %%d in (.) do rd /s /q "%%d\Release" 2>nul +for /r . %%d in (.) do rd /s /q "%%d\settings" 2>nul + +exit \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_armcc.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_armcc.h new file mode 100644 index 0000000000..4d9d0645d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_armclang.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_armclang.h new file mode 100644 index 0000000000..162a400ea1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_compiler.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_compiler.h new file mode 100644 index 0000000000..94212eb87a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_gcc.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_gcc.h new file mode 100644 index 0000000000..2d9db15a5d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_iccarm.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_iccarm.h new file mode 100644 index 0000000000..11c4af0eba --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_version.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_armv8mbl.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_armv8mbl.h new file mode 100644 index 0000000000..251e4ede3a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_armv8mml.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_armv8mml.h new file mode 100644 index 0000000000..3a3148ea31 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm0.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm0.h new file mode 100644 index 0000000000..f929bba07b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm0plus.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm0plus.h new file mode 100644 index 0000000000..424011ac36 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm1.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm1.h new file mode 100644 index 0000000000..0ed678e3b8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm23.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm23.h new file mode 100644 index 0000000000..acbc5dfea2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm3.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm3.h new file mode 100644 index 0000000000..74bff64be4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm33.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm33.h new file mode 100644 index 0000000000..6cd2db77fe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm4.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm4.h new file mode 100644 index 0000000000..7d56873532 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm7.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm7.h new file mode 100644 index 0000000000..a14dc623b7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_sc000.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_sc000.h new file mode 100644 index 0000000000..9b67c92f3b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_sc300.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_sc300.h new file mode 100644 index 0000000000..3e8a47109a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/mpu_armv7.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/mpu_armv7.h new file mode 100644 index 0000000000..01422033d0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/mpu_armv8.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/mpu_armv8.h new file mode 100644 index 0000000000..62571da5b8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/tz_context.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/CMSIS_Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_CodeRAM.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_CodeRAM.c new file mode 100644 index 0000000000..cee9ba617b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_CodeRAM.c @@ -0,0 +1,33 @@ +/** + ****************************************************************************** + * @file lib_CodeRAM.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Codes executed in SRAM. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_CodeRAM.h" + +/** + * @brief Enter idle mode with flash deep standby. + * @note This function is executed in RAM. + * @param None + * @retval None + */ +__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void) +{ + /* Flash deep standby */ + FLASH->PASS = 0x55AAAA55; + FLASH->DSTB = 0xAA5555AA; + /* Enter Idle mode */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + __WFI(); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_LoadNVR.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_LoadNVR.c new file mode 100644 index 0000000000..e3fbc7c00e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_LoadNVR.c @@ -0,0 +1,700 @@ +/** + ****************************************************************************** + * @file lib_LoadNVR.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Load information from NVR. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_LoadNVR.h" + + +/** + * @breif Loads Analog trim data from NVR manually. + * @note Successful Operation: + * - Load [0x80DC0] or [0x80DD0] to ANA registers(B C D E) + * - Load [0x80DE0] or [0x80DE8] to ANA registers(10) + * @param None + * @retval 0: Function succeeded. + !0: Function failed. + bit[0]=1: Function failed(ANA registers(B C D E) Checksum error). + bit[1]=1: Function failed(ANA registers(10) Checksum error). + */ +uint32_t NVR_LoadANADataManual(void) +{ + uint32_t checksum; + uint32_t op_reg; + uint32_t ana_data; + uint32_t key_reg = 0xFFFFFFFF; + uint32_t ret = 0; + + /* Get Analog data1 */ + ana_data = *NVR_ANA_TRIMDATA1; + op_reg = *NVR_ANA_OPREG1; + /* Calculate checksum1 */ + checksum = ~(ana_data + op_reg + key_reg); + /* Compare checksum1 */ + if (checksum == (*NVR_ANA_CHECKSUM1)) + { + ANA->REGB = (uint8_t)(ana_data); + ANA->REGC = (uint8_t)(ana_data >> 8); + ANA->REGD = (uint8_t)(ana_data >> 16); + ANA->REGE = (uint8_t)(ana_data >> 24); + } + else + { + /* Get Analog data2 */ + ana_data = *NVR_ANA_TRIMDATA2; + op_reg = *NVR_ANA_OPREG2; + /* Calculate checksum2 */ + checksum = ~(ana_data + op_reg + key_reg); + /* Compare checksum2 */ + if (checksum == (*NVR_ANA_CHECKSUM2)) + { + ANA->REGB = (uint8_t)(ana_data); + ANA->REGC = (uint8_t)(ana_data >> 8); + ANA->REGD = (uint8_t)(ana_data >> 16); + ANA->REGE = (uint8_t)(ana_data >> 24); + } + else + { + ret |= BIT0; + } + } + + /* Get Analog data1 */ + ana_data = *NVR_ANA1_REG10; + /* Calculate checksum1 */ + checksum = ~ana_data; + /* Compare checksum1 */ + if (checksum == (*NVR_ANA1_REG10_CHKSUM)) + { + ANA->REG10 = (uint8_t)(ana_data); + } + else + { + /* Get Analog data2 */ + ana_data = *NVR_ANA2_REG10; + /* Calculate checksum2 */ + checksum = ~ana_data; + /* Compare checksum2 */ + if (checksum == (*NVR_ANA2_REG10_CHKSUM)) + { + ANA->REG10 = (uint8_t)(ana_data); + } + else + { + ret |= BIT1; + } + } + + return ret; +} + +/** + * @breif Gets the parameters of ADC voltage measuring. + * @note Voltage(unit:V) = aParameter*ADC_DATA + bParameter + OffsetParameter + * ADC_DATA: ADC channel original data + * aParameter/bParameter/OffsetParameter: Get from this function + * @param [in]Mode: + * NVR_3V_EXTERNAL_NODIV + * NVR_3V_EXTERNAL_RESDIV + * NVR_3V_BAT1_RESDIV + * NVR_3V_BATRTC_RESDIV + * NVR_5V_EXTERNAL_NODIV + * NVR_5V_EXTERNAL_RESDIV + * NVR_5V_BAT1_RESDIV + * NVR_5V_BATRTC_RESDIV + * @param [out]Parameter: The parameters get from NVR + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetVoltageParameters(uint32_t Mode, NVR_ADCVOLPARA *Parameter) +{ + uint32_t checksum; + uint32_t i; + int32_t tmp_int; + + /* Check the parameters */ + assert_parameters(IS_NVR_ADCVOL_MODE(Mode)); + + /*----- Power supply: 5V -----*/ + if (0x100UL & Mode) + { + /* Parameter */ + checksum = 0UL; + for (i=0; i<8; i++) + checksum += *(NVR_5VPARA_BASEADDR1+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VPARA_BASEADDR1+i)) /* Checksum1 error */ + { + checksum = 0UL; + for (i=0; i<8; i++) + checksum += *(NVR_5VPARA_BASEADDR2+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VPARA_BASEADDR2+i)) /* Checksum2 error */ + { + return 1; + } + else + { + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)); + Parameter->aParameter = (float)(tmp_int / 100000.0); + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)+1); + Parameter->bParameter = (float)(tmp_int / 100000.0); + } + } + else + { + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)); + Parameter->aParameter = (float)(tmp_int / 100000.0); + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)+1); + Parameter->bParameter = (float)(tmp_int / 100000.0); + } + /* Offset */ + /* Calculate checksum1 */ + checksum = 0UL; + for (i = 0; i < 4; i++) + checksum += *(NVR_5VADCCHx_NODIV1 + i); + checksum = ~(checksum); + if (checksum != *(NVR_5VADCCHx_NODIV1 + i)) + { + /* Calculate checksum2 */ + checksum = 0UL; + for (i = 0; i < 4; i++) + checksum += *(NVR_5VADCCHx_NODIV2+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VADCCHx_NODIV2 + i)) + { + return 1; + } + else + { + Parameter->OffsetParameter = (float)((int32_t)*(NVR_5VADCCHx_NODIV2 + (Mode-0x100UL))); + return 0; + } + } + else + { + Parameter->OffsetParameter = (float)((int32_t)*(NVR_5VADCCHx_NODIV1 + (Mode-0x100UL))); + return 0; + } + } + /*----- Power supply: 3.3V -----*/ + else + { + checksum = 0UL; + for (i=0; i<8; i++) + checksum += *(NVR_3VPARA_BASEADDR1+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VPARA_BASEADDR1+i)) /* Checksum1 error */ + { + checksum = 0UL; + for (i=0; i<8; i++) + checksum += *(NVR_3VPARA_BASEADDR2+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VPARA_BASEADDR2+i)) /* Checksum2 error */ + { + return 1; + } + else + { + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)); + Parameter->aParameter = (float)(tmp_int / 100000.0); + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)+1); + Parameter->bParameter = (float)(tmp_int / 100000.0); + } + } + else + { + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)); + Parameter->aParameter = (float)(tmp_int / 100000.0); + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)+1); + Parameter->bParameter = (float)(tmp_int / 100000.0); + } + /* Calculate checksum1 */ + checksum = 0UL; + for (i = 0; i < 4; i++) + checksum += *(NVR_3VADCCHx_NODIV1 + i); + checksum = ~(checksum); + if (checksum != *(NVR_3VADCCHx_NODIV1 + i)) + { + /* Calculate checksum2 */ + checksum = 0UL; + for (i = 0; i < 4; i++) + checksum += *(NVR_3VADCCHx_NODIV2+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VADCCHx_NODIV2 + i)) + { + return 1; + } + else + { + Parameter->OffsetParameter = (float)((int32_t)*(NVR_3VADCCHx_NODIV2 + (Mode))); + return 0; + } + } + else + { + Parameter->OffsetParameter = (float)((int32_t)*(NVR_3VADCCHx_NODIV1 + (Mode))); + return 0; + } + } +} + +/** + * @breif Gets RTC parameters(P0 P1 P2). + * @param [out]TempParams The pointer to struct NVR_TempParams. + * @retval 0: Function succeeded. + !0: Function failed. + bit[0]=1: Temperature Measure delta information checksum error, default value 0. + bit[1]=1: P0/P1/P2 paramters checksum error, default value 0 + */ +uint32_t NVR_GetTempParameters(NVR_TempParams *TempParams) +{ + uint32_t checksum; + uint32_t data_u32[4]; + int32_t TempDelta; + uint32_t retval = 0; + +/*------------------------ Temperature Measure delta -------------------------*/ + data_u32[0] = *NVR_REALTEMP1; + data_u32[1] = *NVR_MEATEMP1; + /* Calculate checksum1 */ + checksum = ~(data_u32[0] + data_u32[1]); + if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true + { + TempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1]; + } + else + { + data_u32[0] = *NVR_REALTEMP2; + data_u32[1] = *NVR_MEATEMP2; + /* Calculate checksum2 */ + checksum = ~(data_u32[0] + data_u32[1]); + if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true + { + TempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1]; + } + else + { + TempDelta = 0; + retval |= BIT0; + } + } +/*------------------------------ P parameters --------------------------------*/ + + data_u32[0] = *NVR_RTC1_P1_P0; + data_u32[1] = *NVR_RTC1_P2; + data_u32[2] = *NVR_RTC1_P5_P4; + data_u32[3] = *NVR_RTC1_P7_P6; + + /* Calculate checksum1 */ + checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]); + if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true + { + /* Get information */ + TempParams->RTCTempP0 = (int16_t)(data_u32[0]); + TempParams->RTCTempP1 = (int16_t)(data_u32[0] >> 16); + TempParams->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (TempDelta*256)); + } + else + { + data_u32[0] = *NVR_RTC2_P1_P0; + data_u32[1] = *NVR_RTC2_P2; + data_u32[2] = *NVR_RTC2_P5_P4; + data_u32[3] = *NVR_RTC2_P7_P6; + /* Calculate checksum2 */ + checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]); + if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true + { + /* Get information */ + TempParams->RTCTempP0 = (int16_t)(data_u32[0]); + TempParams->RTCTempP1 = (int16_t)(data_u32[0] >> 16); + TempParams->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (TempDelta*256)); + } + else + { + /* Get information */ + TempParams->RTCTempP0 = 0; + TempParams->RTCTempP1 = 0; + TempParams->RTCTempP2 = 0; + retval |= BIT1; + } + } + return retval; +} + +/** + * @breif Loads RTC ACPx pramameters from NVR to RTC registers. + Get RTC pramameters. + * @param [out]RTCTempData The pointer to struct NVR_RTCINFO. + [in]DivCLKSource The RTC division output clock source frequency + * @retval 0: Function succeeded. + !0: Function not succeeded, load default value to registers. + bit[0]=1: Temperature Measure delta information checksum error, default value 0. + bit[1]=1: P paramters checksum error, default value 0 + bit[2]=1: P4 checksum error, default value is 0 + bit[3]=1: ACKx checksum error, default value 0 + bit[4]=1: ACTI checksum error, default value is 0 + bit[5]=1: ACKTEMP checksum error, defalut value is 0 + */ +uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData, uint32_t DivCLKSource) +{ + uint32_t data_u32[5]; + uint32_t checksum; + float pclk_mul; + uint32_t retval = 0; + +/*------------------------ Temperature Measure delta -------------------------*/ + data_u32[0] = *NVR_REALTEMP1; + data_u32[1] = *NVR_MEATEMP1; + /* Calculate checksum1 */ + checksum = ~(data_u32[0] + data_u32[1]); + if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true + { + RTCTempData->RTCTempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1]; + } + else + { + data_u32[0] = *NVR_REALTEMP2; + data_u32[1] = *NVR_MEATEMP2; + /* Calculate checksum2 */ + checksum = ~(data_u32[0] + data_u32[1]); + if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true + { + RTCTempData->RTCTempDelta = (int32_t)data_u32[0] - (int32_t)data_u32[1]; + } + else + { + RTCTempData->RTCTempDelta = 0; + retval |= BIT0; + } + } + +/*------------------------------ P parameters --------------------------------*/ + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* RTC div output clock source */ + pclk_mul = DivCLKSource / 6553600.0; + + data_u32[0] = *NVR_RTC1_P1_P0; + data_u32[1] = *NVR_RTC1_P2; + data_u32[2] = *NVR_RTC1_P5_P4; + data_u32[3] = *NVR_RTC1_P7_P6; + /* Calculate checksum1 */ + checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]); + if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true + { + /* Get information */ + RTCTempData->RTCTempP0 = (int16_t)(data_u32[0]); + RTCTempData->RTCTempP1 = (int16_t)(data_u32[0] >> 16); + RTCTempData->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256)); + RTCTempData->RTCTempP5 = (int16_t)(data_u32[2] >> 16); + RTCTempData->RTCTempP6 = (int16_t)(data_u32[3] * pclk_mul); + RTCTempData->RTCTempP7 = (int16_t)(data_u32[3] >> 16); + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(data_u32[0] & 0xFFFF); + RTC->ACP1 = (uint16_t)((data_u32[0] >> 16) & 0xFFFF); + RTC->ACP2 = (uint32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256)); + RTC->ACP5 = (uint16_t)((data_u32[2] >> 16) & 0xFFFF); + RTC->ACP6 = ((uint16_t)((int16_t)(data_u32[3] * pclk_mul))); + RTC->ACP7 = (uint16_t)((data_u32[3] >> 16) & 0xFFFF); + } + else + { + data_u32[0] = *NVR_RTC2_P1_P0; + data_u32[1] = *NVR_RTC2_P2; + data_u32[2] = *NVR_RTC2_P5_P4; + data_u32[3] = *NVR_RTC2_P7_P6; + /* Calculate checksum2 */ + checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3]); + if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true + { + /* Get information */ + RTCTempData->RTCTempP0 = (int16_t)(data_u32[0]); + RTCTempData->RTCTempP1 = (int16_t)(data_u32[0] >> 16); + RTCTempData->RTCTempP2 = (int32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256)); + RTCTempData->RTCTempP5 = (int16_t)(data_u32[2] >> 16); + RTCTempData->RTCTempP6 = (int16_t)(data_u32[3] * pclk_mul); + RTCTempData->RTCTempP7 = (int16_t)(data_u32[3] >> 16); + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(data_u32[0] & 0xFFFF); + RTC->ACP1 = (uint16_t)((data_u32[0] >> 16) & 0xFFFF); + RTC->ACP2 = (uint32_t)((int32_t)(data_u32[1]) + (RTCTempData->RTCTempDelta*256)); + RTC->ACP5 = (uint16_t)((data_u32[2] >> 16) & 0xFFFF); + RTC->ACP6 = (uint16_t)((int16_t)(data_u32[3] * pclk_mul)); + RTC->ACP7 = (uint16_t)((data_u32[3] >> 16) & 0xFFFF); + } + else + { + /* Get information */ + RTCTempData->RTCTempP0 = 0; + RTCTempData->RTCTempP1 = 0; + RTCTempData->RTCTempP2 = 0; + RTCTempData->RTCTempP5 = 0; + RTCTempData->RTCTempP6 = 0; + RTCTempData->RTCTempP7 = 0; + retval |= BIT1; + } + } + +/*----------------------------------- P4 -------------------------------------*/ + /* Calculate checksum1 */ + data_u32[0] = *NVR_RTC1_P4; + checksum = ~data_u32[0]; + if (checksum == (*NVR_RTC1_P4_CHKSUM))//checksum1 true + { + /* Get information */ + RTCTempData->RTCTempP4 = (int16_t)data_u32[0]; + RTC->ACP4 = data_u32[0]; + } + else + { + data_u32[0] = *NVR_RTC2_P4; + checksum = ~data_u32[0]; + if (checksum == (*NVR_RTC2_P4_CHKSUM))//checksum2 true + { + /* Get information */ + RTCTempData->RTCTempP4 = (int16_t)data_u32[0]; + RTC->ACP4 = data_u32[0]; + } + else + { + RTCTempData->RTCTempP4 = 0; + + retval |= BIT2; + } + } + +/*-------------------------- RTC ACKx parameters -----------------------------*/ + data_u32[0] = *NVR_RTC1_ACK0; + data_u32[1] = *NVR_RTC1_ACK1; + data_u32[2] = *NVR_RTC1_ACK2; + data_u32[3] = *NVR_RTC1_ACK3; + data_u32[4] = *NVR_RTC1_ACK4; + checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3] + data_u32[4]); + if (checksum == (*NVR_RTC1_ACK_CHKSUM))//checksum1 true + { + /* Get information */ + RTCTempData->RTCTempK0 = data_u32[0]; + RTCTempData->RTCTempK1 = data_u32[1]; + RTCTempData->RTCTempK2 = data_u32[2]; + RTCTempData->RTCTempK3 = data_u32[3]; + RTCTempData->RTCTempK4 = data_u32[4]; + + /* Load data to ACKx register */ + RTC->ACK[0] = data_u32[0]; + RTC->ACK[1] = data_u32[1]; + RTC->ACK[2] = data_u32[2]; + RTC->ACK[3] = data_u32[3]; + RTC->ACK[4] = data_u32[4]; + } + else + { + data_u32[0] = *NVR_RTC2_ACK0; + data_u32[1] = *NVR_RTC2_ACK1; + data_u32[2] = *NVR_RTC2_ACK2; + data_u32[3] = *NVR_RTC2_ACK3; + data_u32[4] = *NVR_RTC2_ACK4; + checksum = ~(data_u32[0] + data_u32[1] + data_u32[2] + data_u32[3] + data_u32[4]); + if (checksum == (*NVR_RTC2_ACK_CHKSUM))//checksum2 true + { + /* Get information */ + RTCTempData->RTCTempK0 = data_u32[0]; + RTCTempData->RTCTempK1 = data_u32[1]; + RTCTempData->RTCTempK2 = data_u32[2]; + RTCTempData->RTCTempK3 = data_u32[3]; + RTCTempData->RTCTempK4 = data_u32[4]; + + /* Load data to ACKx register */ + RTC->ACK[0] = data_u32[0]; + RTC->ACK[1] = data_u32[1]; + RTC->ACK[2] = data_u32[2]; + RTC->ACK[3] = data_u32[3]; + RTC->ACK[4] = data_u32[4]; + } + else + { + /* Get information */ + RTCTempData->RTCTempK0 = 0; + RTCTempData->RTCTempK1 = 0; + RTCTempData->RTCTempK2 = 0; + RTCTempData->RTCTempK3 = 0; + RTCTempData->RTCTempK4 = 0; + + retval |= BIT3; + } + } + +/*-------------------------- RTC ACTI parameters -----------------------------*/ + data_u32[0] = *NVR_RTC1_ACTI; + checksum = ~data_u32[0]; + if (checksum == (*NVR_RTC1_ACTI_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACTI = data_u32[0]; + /* Load data to ACKx register */ + RTC->ACTI = data_u32[0]; + } + else + { + data_u32[0] = *NVR_RTC2_ACTI; + checksum = ~data_u32[0]; + if (checksum == (*NVR_RTC2_ACTI_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACTI = data_u32[0]; + /* Load data to ACKx register */ + RTC->ACTI = data_u32[0]; + } + else + { + /* Get information */ + RTCTempData->RTCACTI = 0; + + retval |= BIT4; + } + } + +/*------------------------- RTC ACKTemp parameters ---------------------------*/ + data_u32[0] = *NVR_RTC1_ACKTEMP; + checksum = ~data_u32[0]; + if (checksum == (*NVR_RTC1_ACKTEMP_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACKTemp = data_u32[0]; + /* Load data to ACKx register */ + RTC->ACKTEMP = data_u32[0]; + } + else + { + data_u32[0] = *NVR_RTC2_ACKTEMP; + checksum = ~data_u32[0]; + if (checksum == (*NVR_RTC2_ACKTEMP_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACKTemp = data_u32[0]; + /* Load data to ACKx register */ + RTC->ACKTEMP = data_u32[0]; + } + else + { + /* Get information */ + RTCTempData->RTCACKTemp = 0; + + retval |= BIT5; + } + } +/*--------------------------------- ACF200 -----------------------------------*/ + RTCTempData->RTCACF200 = (uint32_t)(int32_t)((pclk_mul * 0x320000)); + RTC->ACF200 = (uint32_t)(int32_t)((pclk_mul * 0x320000)); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + return retval; +} + +/** + * @breif Gets Power/Clock Measure result. + * @param [out]MEAResult The pointer to struct NVR_PWRMEARES. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult) +{ + uint32_t avcc_data, dvcc_data, bgp_data, rcl_data, rch_data; + uint32_t checksum; + + avcc_data = *NVR_AVCC_MEA1; + dvcc_data = *NVR_DVCC_MEA1; + bgp_data = *NVR_BGP_MEA1; + rcl_data = *NVR_RCL_MEA1; + rch_data = *NVR_RCH_MEA1; + /* Calculate checksum1 */ + checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data); + if (checksum == (*NVR_PWR_CHECKSUM1)) + { + MEAResult->AVCCMEAResult = avcc_data; + MEAResult->DVCCMEAResult = dvcc_data; + MEAResult->BGPMEAResult = bgp_data; + MEAResult->RCLMEAResult = rcl_data; + MEAResult->RCHMEAResult = rch_data; + return 0; + } + + avcc_data = *NVR_AVCC_MEA2; + dvcc_data = *NVR_DVCC_MEA2; + bgp_data = *NVR_BGP_MEA2; + rcl_data = *NVR_RCL_MEA2; + rch_data = *NVR_RCH_MEA2; + /* Calculate checksum2 */ + checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data); + if (checksum == (*NVR_PWR_CHECKSUM2)) + { + MEAResult->AVCCMEAResult = avcc_data; + MEAResult->DVCCMEAResult = dvcc_data; + MEAResult->BGPMEAResult = bgp_data; + MEAResult->RCLMEAResult = rcl_data; + MEAResult->RCHMEAResult = rch_data; + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Gets Chip ID. + * @param [out]ChipID The pointer to struct NVR_CHIPID. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetChipID(NVR_CHIPID *ChipID) +{ + uint32_t id0, id1; + uint32_t checksum; + + id0 = *NVR_CHIP1_ID0; + id1 = *NVR_CHIP1_ID1; + /* Calculate checksum1 */ + checksum = ~(id0 + id1); + if (checksum == (*NVR_CHIP1_CHECKSUM)) + { + ChipID->ChipID0 = id0; + ChipID->ChipID1 = id1; + return 0; + } + + id0 = *NVR_CHIP2_ID0; + id1 = *NVR_CHIP2_ID1; + /* Calculate checksum2 */ + checksum = ~(id0 + id1); + if (checksum == (*NVR_CHIP2_CHECKSUM)) + { + ChipID->ChipID0 = id0; + ChipID->ChipID1 = id1; + return 0; + } + else + { + return 1; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_cortex.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_cortex.c new file mode 100644 index 0000000000..74c87b8f64 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/lib_cortex.c @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file lib_cortex.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Cortex module driver. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_cortex.h" +#include "core_cm0.h" + +/** + * @brief 1. Clears Pending of a device specific External Interrupt. + * 2. Sets Priority of a device specific External Interrupt. + * 3. Enables a device specific External Interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to target.h file) + * @param Priority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @retval None + */ +void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority)); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(IRQn); + /* Set Interrupt Priority */ + NVIC_SetPriority(IRQn, Priority); + /* Enable Interrupt in NVIC */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly before calling it. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Enable interrupt in NVIC */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Disable interrupt in NVIC */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void CORTEX_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Gets the Pending bit of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval 0 Interrupt status is not pending. + 1 Interrupt status is pending. + */ +uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Get priority for Cortex-M0 system or device specific interrupts */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Clear interrupt pending */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval Interrupt Priority. Value is aligned automatically to the implemented + * priority bits of the microcontroller. + */ +uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M0 system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to target.h file) + * @param Priority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @retval None + */ +void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority)); + /* Get priority for Cortex-M0 system or device specific interrupts */ + NVIC_SetPriority(IRQn, Priority); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum) +{ + return SysTick_Config(TicksNum); +} + +/** + * @brief Delay N system-clock cycle. + * @param nClock < 0x1000000 + * @retval None + */ +void CORTEX_Delay_nSysClock(__IO uint32_t nClock) +{ + uint32_t tmp; + + SysTick->LOAD = nClock; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \ + |SysTick_CTRL_ENABLE_Msk; + + do + { + tmp = SysTick->CTRL; + } + while (!(tmp & SysTick_CTRL_COUNTFLAG_Msk)); + + SysTick->CTRL = 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/system_target.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/system_target.c new file mode 100644 index 0000000000..d8dcc96787 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/device/system_target.c @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file system_target.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief system source file. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "target.h" + +#define NVR_REGINFOCOUNT1 (0x80400) +#define NVR_REGINFOBAKOFFSET (0x100) + +/** + * @brief Setup the microcontroller system + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + uint32_t i,nCount,nValue,nAddress,nChecksum; + + nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1; + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4)) + { + nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET); + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4)) + { + while(1); + } + } + + for(i=0; i=0x40014800) && (nAddress<=0x40015000)) + { + RTC_WriteRegisters(nAddress, &nValue, 1); + } + else + { + *(__IO uint32_t *)(nAddress) = nValue; + } + } +} + +/** + * @brief Initializes registers. + * @param None + * @retval None + */ +void SystemUpdate(void) +{ + +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_CodeRAM.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_CodeRAM.h new file mode 100644 index 0000000000..40dc6f0ec5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_CodeRAM.h @@ -0,0 +1,35 @@ +/** + ****************************************************************************** + * @file lib_CodeRAM.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Codes executed in SRAM. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CODERAM_H +#define __LIB_CODERAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + + +/* Exported Functions ------------------------------------------------------- */ + +__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void) __IN_RAMSECTION; + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CODERAM_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_LoadNVR.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_LoadNVR.h new file mode 100644 index 0000000000..b429b19513 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_LoadNVR.h @@ -0,0 +1,235 @@ +/** + ****************************************************************************** + * @file lib_LoadNVR.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Load information from NVR. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_LOADNVR_H +#define __LIB_LOADNVR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Power Measure Result */ +typedef struct +{ + uint32_t AVCCMEAResult; // LDO33 Measure Result + uint32_t DVCCMEAResult; // LDO15 Measure Result + uint32_t BGPMEAResult; // BGP Measure Result + uint32_t RCLMEAResult; // RCL Measure Result + uint32_t RCHMEAResult; // RCH Measure Result +} NVR_MISCGain; + +/* Chip ID */ +typedef struct +{ + uint32_t ChipID0; // ID word 0 + uint32_t ChipID1; // ID word 1 +} NVR_CHIPID; + +/* Temperature information */ +typedef struct +{ + float TempOffset; +} NVR_TEMPINFO; + +/* LCD information */ +typedef struct +{ + uint32_t MEALCDLDO; // Measure LCD LDO pre trim value + uint32_t MEALCDVol; // VLCD setting +} NVR_LCDINFO; + +/* RTC(temp) information */ +typedef struct +{ + int16_t RTCTempP0; //P0 + int16_t RTCTempP1; //P1 + int32_t RTCTempP2; //P2 + int16_t RTCTempP4; //P4 + int16_t RTCTempP5; //P5 + int16_t RTCTempP6; //P6 + int16_t RTCTempP7; //P7 + int16_t RTCTempK0; //K0 + int16_t RTCTempK1; //K1 + int16_t RTCTempK2; //K2 + int16_t RTCTempK3; //K3 + int16_t RTCTempK4; //K4 + int16_t RTCACTI; //Center temperature + uint32_t RTCACKTemp; //section X temperature + int32_t RTCTempDelta; //Temperature delta + uint32_t RTCACF200; //RTC_ACF200 +} NVR_RTCINFO; + +/* RTC(temp) information */ +typedef struct +{ + int16_t RTCTempP0; //P0 + int16_t RTCTempP1; //P1 + int32_t RTCTempP2; //P2 +} NVR_TempParams; + +/* ADC Voltage Parameters */ +typedef struct +{ + float aParameter; + float bParameter; + float OffsetParameter; +} NVR_ADCVOLPARA; +//Mode +#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None +#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive +#define NVR_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive +#define NVR_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive +#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None +#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive +#define NVR_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive +#define NVR_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive +#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\ + ((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == NVR_3V_BAT1_RESDIV) ||\ + ((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == NVR_5V_BAT1_RESDIV) ||\ + ((__MODE__) == NVR_5V_BATRTC_RESDIV)) + +//VOLMode +#define NVR_MEARES_3V 0 +#define NVR_MEARES_5V 1 +#define IS_MEARES(__VOLMODE__) (((__VOLMODE__) == NVR_MEARES_3V) ||\ + ((__VOLMODE__) == NVR_MEARES_5V)) +/********** NVR Address **********/ +//ADC Voltage Parameters +#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x80C48) +#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x80C6C) +#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x80C00) +#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x80C24) +//RTC DATA +//P4 +#define NVR_RTC1_P4 (__IO uint32_t *)(0x80800) +#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x80804) +#define NVR_RTC2_P4 (__IO uint32_t *)(0x80808) +#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x8080C) +//ACK1~ACK5 +#define NVR_RTC1_ACK0 (__IO uint32_t *)(0x80810) +#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x80814) +#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x80818) +#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x8081C) +#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x80820) +#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x80824) +#define NVR_RTC2_ACK0 (__IO uint32_t *)(0x80828) +#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x8082C) +#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x80830) +#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x80834) +#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x80838) +#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x8083C) +//ACTI +#define NVR_RTC1_ACTI (__IO uint32_t *)(0x80840) +#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x80844) +#define NVR_RTC2_ACTI (__IO uint32_t *)(0x80848) +#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x8084C) +//ACKTEMP +#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x80850) +#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x80854) +#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x80858) +#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x8085C) +//Analog trim data +#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x80DC0) +#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x80DC4) +#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x80DC8) +#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x80DCC) +#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x80DD0) +#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x80DD4) +#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x80DD8) +#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x80DDC) +#define NVR_ANA1_REG10 (__IO uint32_t *)(0x80DE0) +#define NVR_ANA1_REG10_CHKSUM (__IO uint32_t *)(0x80DE4) +#define NVR_ANA2_REG10 (__IO uint32_t *)(0x80DE8) +#define NVR_ANA2_REG10_CHKSUM (__IO uint32_t *)(0x80DEC) +//ADC_CHx +#define NVR_5VADCCHx_NODIV1 (__IO uint32_t *)(0x80C90) +#define NVR_5VADCCHx_RESDIV1 (__IO uint32_t *)(0x80C94) +#define NVR_5VADCCHx_NODIV2 (__IO uint32_t *)(0x80CA4) +#define NVR_5VADCCHx_RESDIV2 (__IO uint32_t *)(0x80CA8) +#define NVR_3VADCCHx_NODIV1 (__IO uint32_t *)(0x80CB8) +#define NVR_3VADCCHx_RESDIV1 (__IO uint32_t *)(0x80CBC) +#define NVR_3VADCCHx_NODIV2 (__IO uint32_t *)(0x80CCC) +#define NVR_3VADCCHx_RESDIV2 (__IO uint32_t *)(0x80CD0) +//BAT Measure Result +#define NVR_5VBAT1 (__IO uint32_t *)(0x80C98) +#define NVR_5VBATRTC1 (__IO uint32_t *)(0x80C9C) +#define NVR_5VBATCHKSUM1 (__IO uint32_t *)(0x80CA0) +#define NVR_5VBAT2 (__IO uint32_t *)(0x80CAC) +#define NVR_5VBATRTC2 (__IO uint32_t *)(0x80CB0) +#define NVR_5VBATCHKSUM2 (__IO uint32_t *)(0x80CB4) +#define NVR_3VBAT1 (__IO uint32_t *)(0x80CC0) +#define NVR_3VBATRTC1 (__IO uint32_t *)(0x80CC4) +#define NVR_3VBATCHKSUM1 (__IO uint32_t *)(0x80CC8) +#define NVR_3VBAT2 (__IO uint32_t *)(0x80CD4) +#define NVR_3VBATRTC2 (__IO uint32_t *)(0x80CD8) +#define NVR_3VBATCHKSUM2 (__IO uint32_t *)(0x80CDC) +//RTC AutoCal Px pramameters +#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x80D10) +#define NVR_RTC1_P2 (__IO uint32_t *)(0x80D14) +#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x80D18) +#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x80D1C) +#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x80D20) +#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x80D24) +#define NVR_RTC2_P2 (__IO uint32_t *)(0x80D28) +#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x80D2C) +#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x80D30) +#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x80D34) +//Power Measure Result +#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x80D38) +#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x80D3C) +#define NVR_BGP_MEA1 (__IO uint32_t *)(0x80D40) +#define NVR_RCL_MEA1 (__IO uint32_t *)(0x80D44) +#define NVR_RCH_MEA1 (__IO uint32_t *)(0x80D48) +#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x80D4C) +#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x80D50) +#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x80D54) +#define NVR_BGP_MEA2 (__IO uint32_t *)(0x80D58) +#define NVR_RCL_MEA2 (__IO uint32_t *)(0x80D5C) +#define NVR_RCH_MEA2 (__IO uint32_t *)(0x80D60) +#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x80D64) +//Chip ID +#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x80D68) +#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x80D6C) +#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x80D70) +#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x80D74) +#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x80D78) +#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x80D7C) +//Temperature information +#define NVR_REALTEMP1 (__IO uint32_t *)(0x80D80) +#define NVR_MEATEMP1 (__IO uint32_t *)(0x80D84) +#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x80D88) +#define NVR_REALTEMP2 (__IO uint32_t *)(0x80D9C) +#define NVR_MEATEMP2 (__IO uint32_t *)(0x80D90) +#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x80D94) + +uint32_t NVR_LoadANADataManual(void); +uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData, uint32_t DivCLKSource); +uint32_t NVR_GetVoltageParameters(uint32_t Mode, NVR_ADCVOLPARA *Parameter); +uint32_t NVR_GetTempParameters(NVR_TempParams *TempParams); +uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult); +uint32_t NVR_GetChipID(NVR_CHIPID *ChipID); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_LOADNVR_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_cortex.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_cortex.h new file mode 100644 index 0000000000..db55de4873 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/lib_cortex.h @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file lib_Cortex.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Cortex module driver. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CORTEX_H +#define __LIB_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + + +#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +/* Exported Functions ------------------------------------------------------- */ +void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority); + +void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn); +uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn); +void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority); +void CORTEX_NVIC_SystemReset(void); +uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum); +void CORTEX_Delay_nSysClock(__IO uint32_t nClock); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CORTEX_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/system_target.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/system_target.h new file mode 100644 index 0000000000..c897151964 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/system_target.h @@ -0,0 +1,41 @@ +/** + ****************************************************************************** + * @file system_target.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief system source file. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __SYSTEM_TARGET_H +#define __SYSTEM_TARGET_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "type_def.h" + +#define NVR_REGINFOCOUNT1 (0x80400) +#define NVR_REGINFOBAKOFFSET (0x100) + +/* ########################### System Configuration ######################### */ + +extern void SystemInit(void); +extern void SystemUpdate(void); + + +#ifdef USE_TARGET_DRIVER + #include "lib_conf.h" +#endif /* USE_TARGET_DRIVER */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_TARGET_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/target.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/target.h new file mode 100644 index 0000000000..91b9ed6642 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/target.h @@ -0,0 +1,2799 @@ +/** +******************************************************************************** +* @file target.h +* @author Application Team +* @version V1.1.0 +* @date 2019-10-28 +* @brief Register define +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, XXXXX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +******************************************************************************** +*/ + +#ifndef TARGET_H +#define TARGET_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== target Specific Interrupt Numbers =========================================== */ + PMU_IRQn = 0, /*!< 0 PMU */ + RTC_IRQn = 1, /*!< 1 RTC */ + U32K0_IRQn = 2, /*!< 2 U32K0 */ + U32K1_IRQn = 3, /*!< 3 U32K1 */ + I2C_IRQn = 4, /*!< 4 I2C */ + SPI1_IRQn = 5, /*!< 5 SPI1 */ + UART0_IRQn = 6, /*!< 6 UART0 */ + UART1_IRQn = 7, /*!< 7 UART1 */ + UART2_IRQn = 8, /*!< 8 UART2 */ + UART3_IRQn = 9, /*!< 9 UART3 */ + UART4_IRQn = 10, /*!< 10 UART4 */ + UART5_IRQn = 11, /*!< 11 UART5 */ + ISO78160_IRQn = 12, /*!< 12 ISO78160 */ + ISO78161_IRQn = 13, /*!< 13 ISO78161 */ + TMR0_IRQn = 14, /*!< 14 TMR0 */ + TMR1_IRQn = 15, /*!< 15 TMR1 */ + TMR2_IRQn = 16, /*!< 16 TMR2 */ + TMR3_IRQn = 17, /*!< 17 TMR3 */ + PWM0_IRQn = 18, /*!< 18 PWM0 */ + PWM1_IRQn = 19, /*!< 19 PWM1 */ + PWM2_IRQn = 20, /*!< 20 PWM2 */ + PWM3_IRQn = 21, /*!< 21 PWM3 */ + DMA_IRQn = 22, /*!< 22 DMA */ + FLASH_IRQn = 23, /*!< 23 FLASH */ + ANA_IRQn = 24, /*!< 24 ANA */ + SPI2_IRQn = 27, /*!< 27 SPI2 */ + SPI3_IRQn = 28 /*!< 28 SPI3 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ANA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The Analog controller is used to control the analog function of TARGET. (ANA) + */ + +typedef struct { /*!< (@ 0x40014200) ANA Structure */ + __IOM uint32_t REG0; /*!< (@ 0x00000000) Analog register 0. */ + __IOM uint32_t REG1; /*!< (@ 0x00000004) Analog register 1. */ + __IOM uint32_t REG2; /*!< (@ 0x00000008) Analog register 2. */ + __IOM uint32_t REG3; /*!< (@ 0x0000000C) Analog register 3. */ + __IOM uint32_t REG4; /*!< (@ 0x00000010) Analog register 4. */ + __IOM uint32_t REG5; /*!< (@ 0x00000014) Analog register 5. */ + __IOM uint32_t REG6; /*!< (@ 0x00000018) Analog register 6. */ + __IOM uint32_t REG7; /*!< (@ 0x0000001C) Analog register 7. */ + __IOM uint32_t REG8; /*!< (@ 0x00000020) Analog register 8. */ + __IOM uint32_t REG9; /*!< (@ 0x00000024) Analog register 9. */ + __IOM uint32_t REGA; /*!< (@ 0x00000028) Analog register 10. */ + __IOM uint32_t REGB; /*!< (@ 0x0000002C) Analog register 11. */ + __IOM uint32_t REGC; /*!< (@ 0x00000030) Analog register 12. */ + __IOM uint32_t REGD; /*!< (@ 0x00000034) Analog register 13. */ + __IOM uint32_t REGE; /*!< (@ 0x00000038) Analog register 14. */ + __IOM uint32_t REGF; /*!< (@ 0x0000003C) Analog register 15. */ + __IOM uint32_t REG10; /*!< (@ 0x00000040) Analog register 16. */ + __IOM uint32_t REG11; /*!< (@ 0x00000044) Analog register 17. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t CTRL; /*!< (@ 0x00000050) Analog control register. */ + __IM uint32_t CMPOUT; /*!< (@ 0x00000054) Comparator result register. */ + __IM uint32_t RESERVED1; + __IM uint32_t ADCSTATE; /*!< (@ 0x0000005C) ADC State register. */ + __IOM uint32_t INTSTS; /*!< (@ 0x00000060) Analog interrupt status register. */ + __IOM uint32_t INTEN; /*!< (@ 0x00000064) Analog interrupt enable register. */ + __IOM uint32_t ADCCTRL0; /*!< (@ 0x00000068) ADC control register. */ + __IOM uint32_t CMPCTL; /*!< (@ 0x0000006C) CMP1/CMP2 control register. */ + __IM uint32_t ADCDATA[16]; /*!< (@ 0x00000070) ADC channel x data register. */ + __IOM uint32_t CMPCNT1; /*!< (@ 0x000000B0) Comparator x counter. */ + __IOM uint32_t CMPCNT2; /*!< (@ 0x000000B4) Comparator x counter. */ + __IOM uint32_t MISC; /*!< (@ 0x000000B8) Analog MISC control register. */ + __IM uint32_t RESERVED2; + __IM uint32_t ADCDOS; /*!< (@ 0x000000C0) ANA_ADCDOS. */ + __IM uint32_t RESERVED3[2]; + __IM uint32_t ADCDCPN; /*!< (@ 0x000000CC) ANA_ADCDCPN. */ + __IM uint32_t RESERVED4[2]; + __IM uint32_t ADCDCNM0; /*!< (@ 0x000000D8) ANA_ADCDCNM0. */ + __IM uint32_t RESERVED5; + __IM uint32_t ADCDATADMA; /*!< (@ 0x000000E0) ANA_ADCDATADMA. */ + __IOM uint32_t CMPTHR; /*!< (@ 0x000000E4) CMP1/CMP2 threshold register. */ + __IOM uint32_t ADCCTRL1; /*!< (@ 0x000000E8) ANA_ADCCTRL1. */ + __IOM uint32_t ADCCTRL2; /*!< (@ 0x000000EC) ANA_ADCCTRL2. */ + __IM uint32_t RESERVED6; + __IOM uint32_t ADCDATATHD1_0; /*!< (@ 0x000000F4) ANA_ADCDATATHD1_0. */ + __IOM uint32_t ADCDATATHD3_2; /*!< (@ 0x000000F8) ANA_ADCDATATHD3_2. */ + __IOM uint32_t ADCDATATHD_CH; /*!< (@ 0x000000FC) ANA_ADCDATATHD_CH. */ +} ANA_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ CRYPT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRYPT accelerate the sign and verify process speed of ECC. (CRYPT) + */ + +typedef struct { /*!< (@ 0x40006000) CRYPT Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) CRYPT control register. */ + __IOM uint32_t PTRA; /*!< (@ 0x00000004) CRYPT pointer A. */ + __IOM uint32_t PTRB; /*!< (@ 0x00000008) CRYPT pointer B. */ + __IOM uint32_t PTRO; /*!< (@ 0x0000000C) CRYPT pointer O. */ + __IM uint32_t CARRY; /*!< (@ 0x00000010) CRYPT carry/borrow bit register. */ +} CRYPT_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA(Direct Memory Access) (DMA) + */ + +typedef struct { /*!< (@ 0x40010000) DMA Structure */ + __IOM uint32_t IE; /*!< (@ 0x00000000) DMA interrupt enable register. */ + __IOM uint32_t STS; /*!< (@ 0x00000004) DMA status register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t C0CTL; /*!< (@ 0x00000010) DMA channel x control register. */ + __IOM uint32_t C0SRC; /*!< (@ 0x00000014) DMA source address register. */ + __IOM uint32_t C0DST; /*!< (@ 0x00000018) DMA channel x destination register. */ + __IOM uint32_t C0LEN; /*!< (@ 0x0000001C) DMA channel x transfer length register. */ + __IOM uint32_t C1CTL; /*!< (@ 0x00000020) DMA channel x control register. */ + __IOM uint32_t C1SRC; /*!< (@ 0x00000024) DMA source address register. */ + __IOM uint32_t C1DST; /*!< (@ 0x00000028) DMA channel x destination register. */ + __IOM uint32_t C1LEN; /*!< (@ 0x0000002C) DMA channel x transfer length register. */ + __IOM uint32_t C2CTL; /*!< (@ 0x00000030) DMA channel x control register. */ + __IOM uint32_t C2SRC; /*!< (@ 0x00000034) DMA source address register. */ + __IOM uint32_t C2DST; /*!< (@ 0x00000038) DMA channel x destination register. */ + __IOM uint32_t C2LEN; /*!< (@ 0x0000003C) DMA channel x transfer length register. */ + __IOM uint32_t C3CTL; /*!< (@ 0x00000040) DMA channel x control register. */ + __IOM uint32_t C3SRC; /*!< (@ 0x00000044) DMA source address register. */ + __IOM uint32_t C3DST; /*!< (@ 0x00000048) DMA channel x destination register. */ + __IOM uint32_t C3LEN; /*!< (@ 0x0000004C) DMA channel x transfer length register. */ + __IOM uint32_t AESCTL; /*!< (@ 0x00000050) DMA AES control register. */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t AESKEY[8]; /*!< (@ 0x00000060) DMA AES key x register. When mode is AES128, + only register KEY3~KEY0 is used. When mode + is AES192, only register KEY5~KEY0 is used. + When mode is AES256, register KEY7~KEY0 + is used. */ +} DMA_Type; /*!< Size = 128 (0x80) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Register (FLASH) + */ + +typedef struct { /*!< (@ 0x000FFF00) FLASH Structure */ + __IM uint32_t RESERVED[42]; + __IOM uint32_t ICEPROT; /*!< (@ 0x000000A8) ICE protect register. */ + __IM uint32_t RDPROT; /*!< (@ 0x000000AC) Flash read protect status register */ + __IOM uint32_t WRPROT; /*!< (@ 0x000000B0) Flash write protect control register */ + __IM uint32_t RESERVED1[2]; + __IM uint32_t STS; /*!< (@ 0x000000BC) Flash programming status register. */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t INTSTS; /*!< (@ 0x000000CC) FLASH Checksum interrupt status */ + __IOM uint32_t CSSADDR; /*!< (@ 0x000000D0) FLASH Checksum start address */ + __IOM uint32_t CSEADDR; /*!< (@ 0x000000D4) FLASH Checksum end address. */ + __IM uint32_t CSVALUE; /*!< (@ 0x000000D8) FLASH Checksum value register */ + __IOM uint32_t CSCVALUE; /*!< (@ 0x000000DC) FLASH Checksum compare value register. */ + __IOM uint32_t PASS; /*!< (@ 0x000000E0) FLASH password register */ + __IOM uint32_t CTRL; /*!< (@ 0x000000E4) FLASH control register. */ + __IOM uint32_t PGADDR; /*!< (@ 0x000000E8) FLASH program address register. */ + __IOM uint32_t PGDATA; /*!< (@ 0x000000EC) FLASH program word data register. */ + __IM uint32_t RESERVED3; + __IOM uint32_t SERASE; /*!< (@ 0x000000F4) FLASH sector erase control register. */ + __IOM uint32_t CERASE; /*!< (@ 0x000000F8) FLASH chip erase control register. */ + __IOM uint32_t DSTB; /*!< (@ 0x000000FC) FLASH deep standby control register. */ +} FLASH_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The GPIO controller is used to control the GPIOs of TARGET. (GPIOA) + */ + +typedef struct { /*!< (@ 0x40014010) GPIOA Structure */ + __IOM uint32_t OEN; /*!< (@ 0x00000000) IOA output enable register */ + __IOM uint32_t IE; /*!< (@ 0x00000004) IOA input enable register */ + __IOM uint32_t DAT; /*!< (@ 0x00000008) IOA data register */ + __IOM uint32_t ATT; /*!< (@ 0x0000000C) IOA attribute register */ + __IOM uint32_t IOAWKUEN; /*!< (@ 0x00000010) IOA wake-up enable register */ + __IM uint32_t STS; /*!< (@ 0x00000014) IOA input status register */ + __IOM uint32_t IOAINTSTS; /*!< (@ 0x00000018) IOA interrupt status register. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t SEL; /*!< (@ 0x00000028) IOA special function select register. */ + __IM uint32_t RESERVED1[5]; + __IOM uint32_t IOANODEG; /*!< (@ 0x00000040) IOA no-deglitch control register. */ +} GPIOA_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The GPIO controller is used to control the GPIOs of TARGET. (GPIO) + */ + +typedef struct { /*!< (@ 0x40000020) GPIO Structure */ + __IOM uint32_t OEN; /*!< (@ 0x00000000) IO output enable register */ + __IOM uint32_t IE; /*!< (@ 0x00000004) IO input enable register */ + __IOM uint32_t DAT; /*!< (@ 0x00000008) IO data register */ + __IOM uint32_t ATT; /*!< (@ 0x0000000C) IO attribute register */ + __IM uint32_t STS; /*!< (@ 0x00000010) IO input status register */ +} GPIO_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOAF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The GPIO controller is used to control the GPIOs of TARGET. (GPIOAF) + */ + +typedef struct { /*!< (@ 0x400000C0) GPIOAF Structure */ + __IOM uint32_t IOB_SEL; /*!< (@ 0x00000000) IOB special function select register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t IOE_SEL; /*!< (@ 0x0000000C) IOE special function select register. */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t IO_MISC; /*!< (@ 0x00000020) IO misc. control register. */ +} GPIOAF_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C-Inter Integrated Circuit (I2C) + */ + +typedef struct { /*!< (@ 0x40010800) I2C Structure */ + __IOM uint32_t DATA; /*!< (@ 0x00000000) I2C data register. */ + __IOM uint32_t ADDR; /*!< (@ 0x00000004) I2C address register. */ + __IOM uint32_t CTRL; /*!< (@ 0x00000008) I2C control/status register. */ + __IM uint32_t STS; /*!< (@ 0x0000000C) I2C status register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t CTRL2; /*!< (@ 0x00000018) I2C interrupt enable register. */ +} I2C_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ ISO7816 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The ISO7816 controller is an enhance UART protocol which is able to do half-duplex communication on the 2 wires bus. (ISO7816) + */ + +typedef struct { /*!< (@ 0x40012000) ISO7816 Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t BAUDDIVL; /*!< (@ 0x00000004) ISO7816 baud-rate low byte register */ + __IOM uint32_t BAUDDIVH; /*!< (@ 0x00000008) ISO7816 baud-rate high byte register */ + __IOM uint32_t DATA; /*!< (@ 0x0000000C) ISO7816 data register. */ + __IOM uint32_t INFO; /*!< (@ 0x00000010) ISO7816 information register. */ + __IOM uint32_t CFG; /*!< (@ 0x00000014) ISO7816 control register. */ + __IOM uint32_t CLK; /*!< (@ 0x00000018) ISO7816 clock divider control register. */ +} ISO7816_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ LCD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The LCD controller is used to display content on the LCD panel. (LCD) + */ + +typedef struct { /*!< (@ 0x40002000) LCD Structure */ + __IOM uint32_t FB[40]; /*!< (@ 0x00000000) LCD Frame buffer x register */ + __IM uint32_t RESERVED[24]; + __IOM uint32_t CTRL; /*!< (@ 0x00000100) LCD control register. */ + __IOM uint32_t CTRL2; /*!< (@ 0x00000104) LCD control register2. */ + __IOM uint32_t SEGCTRL0; /*!< (@ 0x00000108) LCD segment enable control register 0 */ + __IOM uint32_t SEGCTRL1; /*!< (@ 0x0000010C) LCD segment enable control register 1 */ + __IOM uint32_t SEGCTRL2; /*!< (@ 0x00000110) LCD segment enable control register 2 */ +} LCD_Type; /*!< Size = 276 (0x114) */ + + + +/* =========================================================================================================================== */ +/* ================ MISC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The MISC controller is used to control some special function of TARGET, which will be power-off during sleep and deep-sleep mode. (MISC1) + */ + +typedef struct { /*!< (@ 0x40013000) MISC1 Structure */ + __IOM uint32_t SRAMINT; /*!< (@ 0x00000000) SRAM Parity Error Interrupt. */ + __IOM uint32_t SRAMINIT; /*!< (@ 0x00000004) SRAM initialize register. */ + __IM uint32_t PARERR; /*!< (@ 0x00000008) SRAM Parity Error address register. */ + __IOM uint32_t IREN; /*!< (@ 0x0000000C) IR enable control register. */ + __IOM uint32_t DUTYL; /*!< (@ 0x00000010) IR Duty low pulse control register. */ + __IOM uint32_t DUTYH; /*!< (@ 0x00000014) IR Duty high pulse control register. */ + __IOM uint32_t IRQLAT; /*!< (@ 0x00000018) Cortex M0 IRQ latency control register. */ + __IM uint32_t RESERVED; + __IM uint32_t HIADDR; /*!< (@ 0x00000020) AHB invalid access address. */ + __IM uint32_t PIADDR; /*!< (@ 0x00000024) APB invalid access address. */ +} MISC1_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ MISC2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MISC2 controller is in retention domain which will be power-off at deep-sleep mode. (MISC2) + */ + +typedef struct { /*!< (@ 0x40013E00) MISC2 Structure */ + __IOM uint32_t FLASHWC; /*!< (@ 0x00000000) Flash wait cycle register. */ + __IOM uint32_t CLKSEL; /*!< (@ 0x00000004) Clock selection register. */ + __IOM uint32_t CLKDIVH; /*!< (@ 0x00000008) AHB clock divider control register. */ + __IOM uint32_t CLKDIVP; /*!< (@ 0x0000000C) APB clock divider control register. */ + __IOM uint32_t HCLKEN; /*!< (@ 0x00000010) AHB clock enable control register. */ + __IOM uint32_t PCLKEN; /*!< (@ 0x00000014) APB clock enable control register. */ +} MISC2_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit. (PMU) + */ + +typedef struct { /*!< (@ 0x40014000) PMU Structure */ + __IOM uint32_t DSLEEPEN; /*!< (@ 0x00000000) PMU deep sleep enable register. */ + __IOM uint32_t DSLEEPPASS; /*!< (@ 0x00000004) PMU deep sleep password register. */ + __IOM uint32_t CONTROL; /*!< (@ 0x00000008) PMU control register. */ + __IOM uint32_t STS; /*!< (@ 0x0000000C) PMU Status register. */ + __IM uint32_t RESERVED[12]; + __IOM uint32_t WDTPASS; /*!< (@ 0x00000040) Watch dog timing unlock register. */ + __IOM uint32_t WDTEN; /*!< (@ 0x00000044) Watch dog timer enable register. */ + __IOM uint32_t WDTCLR; /*!< (@ 0x00000048) Watch dog timer clear register. */ + __IM uint32_t RESERVED1[237]; + __IOM uint32_t RAM[64]; /*!< (@ 0x00000400) PMU 32 bits Retention RAM x. */ +} PMU_Type; /*!< Size = 1280 (0x500) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timers are 16 bits timers with PWM and capture function. (PWM) + */ + +typedef struct { /*!< (@ 0x40012900) PWM Structure */ + __IOM uint32_t CTL; /*!< (@ 0x00000000) Control register of PWM Timer 0 */ + __IM uint32_t TAR; /*!< (@ 0x00000004) Current count register of PWM Timer x. */ + __IOM uint32_t CCTL[3]; /*!< (@ 0x00000008) Compare/capture control register x(x=0~3) for + PWM timer x. */ + __IOM uint32_t CCR[3]; /*!< (@ 0x00000014) Compare/capture data register x for PWM timer + x. */ +} PWM_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM_SEL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timers are 16 bits timers with PWM and capture function. (PWM_SEL) + */ + +typedef struct { /*!< (@ 0x400129F0) PWM_SEL Structure */ + __IOM uint32_t O_SEL; /*!< (@ 0x00000000) PWM output selection register. */ + __IOM uint32_t I_SEL01; /*!< (@ 0x00000004) Input of PWM0 and PWM1 selection register. */ + __IOM uint32_t I_SEL23; /*!< (@ 0x00000008) Input of PWM2 and PWM3 selection register. */ +} PWM_SEL_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The RTC controller is used to control time calculation and RTC auto calibration function. (RTC) + */ + +typedef struct { /*!< (@ 0x40014800) RTC Structure */ + __IOM uint32_t SEC; /*!< (@ 0x00000000) RTC second register */ + __IOM uint32_t MIN; /*!< (@ 0x00000004) RTC minute register */ + __IOM uint32_t HOUR; /*!< (@ 0x00000008) RTC hour register */ + __IOM uint32_t DAY; /*!< (@ 0x0000000C) RTC day register */ + __IOM uint32_t WEEK; /*!< (@ 0x00000010) RTC week register */ + __IOM uint32_t MON; /*!< (@ 0x00000014) RTC mon register */ + __IOM uint32_t YEAR; /*!< (@ 0x00000018) RTC year register */ + __IOM uint32_t TIME; /*!< (@ 0x0000001C) RTC accurate second/millisecond register */ + __IOM uint32_t WKUSEC; /*!< (@ 0x00000020) RTC wake-up second register. */ + __IOM uint32_t WKUMIN; /*!< (@ 0x00000024) RTC wake-up minute register */ + __IOM uint32_t WKUHOUR; /*!< (@ 0x00000028) RTC wake-up hour register */ + __IOM uint32_t WKUCNT; /*!< (@ 0x0000002C) RTC wake-up counter register */ + __IOM uint32_t CAL; /*!< (@ 0x00000030) RTC calibration register */ + __IOM uint32_t DIV; /*!< (@ 0x00000034) RTC calibration register */ + __IOM uint32_t CTL; /*!< (@ 0x00000038) RTC PLL divider control register. */ + __IOM uint32_t ITV; /*!< (@ 0x0000003C) RTC wake-up interval control */ + __IOM uint32_t SITV; /*!< (@ 0x00000040) RTC wake-up second interval control */ + __IOM uint32_t PWD; /*!< (@ 0x00000044) RTC password control register. */ + __IOM uint32_t CE; /*!< (@ 0x00000048) RTC write enable control register. */ + __IM uint32_t LOAD; /*!< (@ 0x0000004C) RTC read enable control register */ + __IOM uint32_t INTSTS; /*!< (@ 0x00000050) RTC interrupt status control register */ + __IOM uint32_t INTEN; /*!< (@ 0x00000054) RTC interrupt enable control register */ + __IOM uint32_t PSCA; /*!< (@ 0x00000058) RTC clock pre-scaler control register. */ + __IM uint32_t RESERVED[10]; + __IOM uint32_t ACTI; /*!< (@ 0x00000084) RTC auto-calibration center temperature control + register. */ + __IOM uint32_t ACF200; /*!< (@ 0x00000088) RTC auto-calibration 200*frequency control register. */ + __IM uint32_t RESERVED1; + __IOM uint32_t ACP0; /*!< (@ 0x00000090) RTC parameter P0 register. */ + __IOM uint32_t ACP1; /*!< (@ 0x00000094) RTC parameter P1 register. */ + __IOM uint32_t ACP2; /*!< (@ 0x00000098) RTC parameter P2 register. */ + __IM uint32_t ACP3; /*!< (@ 0x0000009C) RTC parameter P3 register. */ + __IOM uint32_t ACP4; /*!< (@ 0x000000A0) RTC parameter P4 register. */ + __IOM uint32_t ACP5; /*!< (@ 0x000000A4) RTC parameter P5 register. */ + __IOM uint32_t ACP6; /*!< (@ 0x000000A8) RTC parameter P6 register. */ + __IOM uint32_t ACP7; /*!< (@ 0x000000AC) RTC parameter P7 register. */ + __IOM uint32_t ACK[5]; /*!< (@ 0x000000B0) RTC auto-calibration parameter Kx control register. */ + __IM uint32_t RESERVED2[2]; + __IM uint32_t WKUCNTR; /*!< (@ 0x000000CC) This register is used to represent the current + WKUCNT value. */ + __IOM uint32_t ACKTEMP; /*!< (@ 0x000000D0) RTC auto-calibration k temperature section control + register. */ + __IOM uint32_t ALARMTIME; /*!< (@ 0x000000D4) RTC alarm accurate second/millisecond. */ + __IOM uint32_t ALARMSEC; /*!< (@ 0x000000D8) RTC alarm inaccurate second */ + __IOM uint32_t ALARMMIN; /*!< (@ 0x000000DC) RTC alarm minute */ + __IOM uint32_t ALARMHOUR; /*!< (@ 0x000000E0) RTC alarm hour */ + __IOM uint32_t ALARMCTL; /*!< (@ 0x000000E4) RTC alarm control */ + __IOM uint32_t ADCUCALK; /*!< (@ 0x000000E8) RTC ADC Ucal K coefficients */ + __IOM uint32_t ADCMACTL; /*!< (@ 0x000000EC) RTC ADC control */ + __IOM uint32_t ADCDTCTL; /*!< (@ 0x000000F0) RTC ADC data control */ +} RTC_Type; /*!< Size = 244 (0xf4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI(Serial Peripheral Interface). (SPI) + */ + +typedef struct { /*!< (@ 0x40011000) SPI Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) SPI Control Register. */ + __IOM uint32_t TXSTS; /*!< (@ 0x00000004) SPI Transmit Status Register. */ + __IOM uint32_t TXDAT; /*!< (@ 0x00000008) SPI Transmit FIFO register. */ + __IOM uint32_t RXSTS; /*!< (@ 0x0000000C) SPI Receive Status Register. */ + __IM uint32_t RXDAT; /*!< (@ 0x00000010) SPI Receive FIFO Register. */ + __IOM uint32_t MISC; /*!< (@ 0x00000014) SPI Misc. Control Register. */ +} SPI_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ TMR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General purpose 32 bits timer, which are used to generate regulate interrupt for CM0. (TMR) + */ + +typedef struct { /*!< (@ 0x40012800) TMR Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register of Timer x */ + __IOM uint32_t VALUE; /*!< (@ 0x00000004) Current count register of Timer x */ + __IOM uint32_t RELOAD; /*!< (@ 0x00000008) Reload register of Timer x. */ + __IOM uint32_t INTSTS; /*!< (@ 0x0000000C) Interrupt status register of Timer x. */ +} TMR_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART(Universal Asynchronous Receiver/Transmitter). (UART) + */ + +typedef struct { /*!< (@ 0x40011800) UART Structure */ + __IOM uint32_t DATA; /*!< (@ 0x00000000) UART data register. */ + __IOM uint32_t STATE; /*!< (@ 0x00000004) UART status register. */ + __IOM uint32_t CTRL; /*!< (@ 0x00000008) UART control register. */ + __IOM uint32_t INTSTS; /*!< (@ 0x0000000C) UART interrupt status register. */ + __IOM uint32_t BAUDDIV; /*!< (@ 0x00000010) UART baud rate divide register. */ + __IOM uint32_t CTRL2; /*!< (@ 0x00000014) UART control register 2. */ +} UART_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ U32K ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The UART 32K controller is used to receive data via UART protocol. (U32K) + */ + +typedef struct { /*!< (@ 0x40014100) U32K Structure */ + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) UART 32K x control register 0. */ + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) UART 32K x control register 1. */ + __IOM uint32_t BAUDDIV; /*!< (@ 0x00000008) UART 32K x baud rate control register. */ + __IM uint32_t DATA; /*!< (@ 0x0000000C) UART 32K x receive data buffer. */ + __IOM uint32_t STS; /*!< (@ 0x00000010) UART 32K x interrupt status register. */ +} U32K_Type; /*!< Size = 20 (0x14) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ANA_BASE 0x40014200UL +#define CRYPT_BASE 0x40006000UL +#define DMA_BASE 0x40010000UL +#define FLASH_BASE 0x000FFF00UL +#define GPIOA_BASE 0x40014010UL +#define GPIOB_BASE 0x40000020UL +#define GPIOC_BASE 0x40000040UL +#define GPIOD_BASE 0x40000060UL +#define GPIOE_BASE 0x40000080UL +#define GPIOF_BASE 0x400000A0UL +#define GPIOAF_BASE 0x400000C0UL +#define I2C_BASE 0x40010800UL +#define ISO78160_BASE 0x40012000UL +#define ISO78161_BASE 0x40012040UL +#define LCD_BASE 0x40002000UL +#define MISC1_BASE 0x40013000UL +#define MISC2_BASE 0x40013E00UL +#define PMU_BASE 0x40014000UL +#define PWM0_BASE 0x40012900UL +#define PWM1_BASE 0x40012920UL +#define PWM2_BASE 0x40012940UL +#define PWM3_BASE 0x40012960UL +#define PWM_SEL_BASE 0x400129F0UL +#define RTC_BASE 0x40014800UL +#define SPI1_BASE 0x40011000UL +#define SPI2_BASE 0x40015800UL +#define SPI3_BASE 0x40016000UL +#define TMR0_BASE 0x40012800UL +#define TMR1_BASE 0x40012820UL +#define TMR2_BASE 0x40012840UL +#define TMR3_BASE 0x40012860UL +#define UART0_BASE 0x40011800UL +#define UART1_BASE 0x40011820UL +#define UART2_BASE 0x40011840UL +#define UART3_BASE 0x40011860UL +#define UART4_BASE 0x40011880UL +#define UART5_BASE 0x400118A0UL +#define U32K0_BASE 0x40014100UL +#define U32K1_BASE 0x40014180UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define ANA ((ANA_Type*) ANA_BASE) +#define CRYPT ((CRYPT_Type*) CRYPT_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define FLASH ((FLASH_Type*) FLASH_BASE) +#define GPIOA ((GPIOA_Type*) GPIOA_BASE) +#define GPIOB ((GPIO_Type*) GPIOB_BASE) +#define GPIOC ((GPIO_Type*) GPIOC_BASE) +#define GPIOD ((GPIO_Type*) GPIOD_BASE) +#define GPIOE ((GPIO_Type*) GPIOE_BASE) +#define GPIOF ((GPIO_Type*) GPIOF_BASE) +#define GPIOAF ((GPIOAF_Type*) GPIOAF_BASE) +#define I2C ((I2C_Type*) I2C_BASE) +#define ISO78160 ((ISO7816_Type*) ISO78160_BASE) +#define ISO78161 ((ISO7816_Type*) ISO78161_BASE) +#define LCD ((LCD_Type*) LCD_BASE) +#define MISC1 ((MISC1_Type*) MISC1_BASE) +#define MISC2 ((MISC2_Type*) MISC2_BASE) +#define PMU ((PMU_Type*) PMU_BASE) +#define PWM0 ((PWM_Type*) PWM0_BASE) +#define PWM1 ((PWM_Type*) PWM1_BASE) +#define PWM2 ((PWM_Type*) PWM2_BASE) +#define PWM3 ((PWM_Type*) PWM3_BASE) +#define PWM_SEL ((PWM_SEL_Type*) PWM_SEL_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define SPI1 ((SPI_Type*) SPI1_BASE) +#define SPI2 ((SPI_Type*) SPI2_BASE) +#define SPI3 ((SPI_Type*) SPI3_BASE) +#define TMR0 ((TMR_Type*) TMR0_BASE) +#define TMR1 ((TMR_Type*) TMR1_BASE) +#define TMR2 ((TMR_Type*) TMR2_BASE) +#define TMR3 ((TMR_Type*) TMR3_BASE) +#define UART0 ((UART_Type*) UART0_BASE) +#define UART1 ((UART_Type*) UART1_BASE) +#define UART2 ((UART_Type*) UART2_BASE) +#define UART3 ((UART_Type*) UART3_BASE) +#define UART4 ((UART_Type*) UART4_BASE) +#define UART5 ((UART_Type*) UART5_BASE) +#define U32K0 ((U32K_Type*) U32K0_BASE) +#define U32K1 ((U32K_Type*) U32K1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ANA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= REG0 ========================================================== */ +#define ANA_REG0_ADCFRQSEL_Pos (0UL) /*!< ANA REG0: ADCFRQSEL (Bit 0) */ +#define ANA_REG0_ADCFRQSEL_Msk (0x1UL) /*!< ANA REG0: ADCFRQSEL (Bitfield-Mask: 0x01) */ +#define ANA_REG0_ADCFRQSEL ANA_REG0_ADCFRQSEL_Msk +/* ========================================================= REG1 ========================================================== */ +#define ANA_REG1_ADCMODESEL_Pos (7UL) /*!< ANA REG1: ADCMODESEL (Bit 7) */ +#define ANA_REG1_ADCMODESEL_Msk (0x80UL) /*!< ANA REG1: ADCMODESEL (Bitfield-Mask: 0x01) */ +#define ANA_REG1_ADCMODESEL ANA_REG1_ADCMODESEL_Msk +/* ========================================================= REG2 ========================================================== */ +#define ANA_REG2_CMP2REFSEL_Pos (5UL) /*!< ANA REG2: CMP2REFSEL (Bit 5) */ +#define ANA_REG2_CMP2REFSEL_Msk (0x20UL) /*!< ANA REG2: CMP2REFSEL (Bitfield-Mask: 0x01) */ +#define ANA_REG2_CMP2REFSEL ANA_REG2_CMP2REFSEL_Msk +#define ANA_REG2_CMP1REFSEL_Pos (4UL) /*!< ANA REG2: CMP1REFSEL (Bit 4) */ +#define ANA_REG2_CMP1REFSEL_Msk (0x10UL) /*!< ANA REG2: CMP1REFSEL (Bitfield-Mask: 0x01) */ +#define ANA_REG2_CMP1REFSEL ANA_REG2_CMP1REFSEL_Msk +#define ANA_REG2_CMP2SEL_Pos (2UL) /*!< ANA REG2: CMP2SEL (Bit 2) */ +#define ANA_REG2_CMP2SEL_Msk (0xcUL) /*!< ANA REG2: CMP2SEL (Bitfield-Mask: 0x03) */ +#define ANA_REG2_CMP2SEL ANA_REG2_CMP2SEL_Msk +#define ANA_REG2_CMP1SEL_Pos (0UL) /*!< ANA REG2: CMP1SEL (Bit 0) */ +#define ANA_REG2_CMP1SEL_Msk (0x3UL) /*!< ANA REG2: CMP1SEL (Bitfield-Mask: 0x03) */ +#define ANA_REG2_CMP1SEL ANA_REG2_CMP1SEL_Msk +/* ========================================================= REG3 ========================================================== */ +#define ANA_REG3_XOHPDN_Pos (7UL) /*!< ANA REG3: XOHPDN (Bit 7) */ +#define ANA_REG3_XOHPDN_Msk (0x80UL) /*!< ANA REG3: XOHPDN (Bitfield-Mask: 0x01) */ +#define ANA_REG3_XOHPDN ANA_REG3_XOHPDN_Msk +#define ANA_REG3_PLLHPDN_Pos (6UL) /*!< ANA REG3: PLLHPDN (Bit 6) */ +#define ANA_REG3_PLLHPDN_Msk (0x40UL) /*!< ANA REG3: PLLHPDN (Bitfield-Mask: 0x01) */ +#define ANA_REG3_PLLHPDN ANA_REG3_PLLHPDN_Msk +#define ANA_REG3_PLLLPDN_Pos (5UL) /*!< ANA REG3: PLLLPDN (Bit 5) */ +#define ANA_REG3_PLLLPDN_Msk (0x20UL) /*!< ANA REG3: PLLLPDN (Bitfield-Mask: 0x01) */ +#define ANA_REG3_PLLLPDN ANA_REG3_PLLLPDN_Msk +#define ANA_REG3_RCHPD_Pos (4UL) /*!< ANA REG3: RCHPD (Bit 4) */ +#define ANA_REG3_RCHPD_Msk (0x10UL) /*!< ANA REG3: RCHPD (Bitfield-Mask: 0x01) */ +#define ANA_REG3_RCHPD ANA_REG3_RCHPD_Msk +#define ANA_REG3_BGPPD_Pos (3UL) /*!< ANA REG3: BGPPD (Bit 3) */ +#define ANA_REG3_BGPPD_Msk (0x8UL) /*!< ANA REG3: BGPPD (Bitfield-Mask: 0x01) */ +#define ANA_REG3_BGPPD ANA_REG3_BGPPD_Msk +#define ANA_REG3_CMP2PDN_Pos (2UL) /*!< ANA REG3: CMP2PDN (Bit 2) */ +#define ANA_REG3_CMP2PDN_Msk (0x4UL) /*!< ANA REG3: CMP2PDN (Bitfield-Mask: 0x01) */ +#define ANA_REG3_CMP2PDN ANA_REG3_CMP2PDN_Msk +#define ANA_REG3_CMP1PDN_Pos (1UL) /*!< ANA REG3: CMP1PDN (Bit 1) */ +#define ANA_REG3_CMP1PDN_Msk (0x2UL) /*!< ANA REG3: CMP1PDN (Bitfield-Mask: 0x01) */ +#define ANA_REG3_CMP1PDN ANA_REG3_CMP1PDN_Msk +/* ========================================================= REG4 ========================================================== */ +/* ========================================================= REG5 ========================================================== */ +#define ANA_REG5_AVCCLVDETPD_Pos (6UL) /*!< ANA REG5: AVCCLVDETPD (Bit 6) */ +#define ANA_REG5_AVCCLVDETPD_Msk (0x40UL) /*!< ANA REG5: AVCCLVDETPD (Bitfield-Mask: 0x01) */ +#define ANA_REG5_AVCCLVDETPD ANA_REG5_AVCCLVDETPD_Msk +#define ANA_REG5_CMP2IT_Pos (2UL) /*!< ANA REG5: CMP2IT (Bit 2) */ +#define ANA_REG5_CMP2IT_Msk (0xcUL) /*!< ANA REG5: CMP2IT (Bitfield-Mask: 0x03) */ +#define ANA_REG5_CMP2IT ANA_REG5_CMP2IT_Msk +#define ANA_REG5_CMP1IT_Pos (0UL) /*!< ANA REG5: CMP1IT (Bit 0) */ +#define ANA_REG5_CMP1IT_Msk (0x3UL) /*!< ANA REG5: CMP1IT (Bitfield-Mask: 0x03) */ +#define ANA_REG5_CMP1IT ANA_REG5_CMP1IT_Msk +/* ========================================================= REG6 ========================================================== */ +#define ANA_REG6_BATRTCDISC_Pos (7UL) /*!< ANA REG6: BATRTCDISC (Bit 7) */ +#define ANA_REG6_BATRTCDISC_Msk (0x80UL) /*!< ANA REG6: BATRTCDISC (Bitfield-Mask: 0x01) */ +#define ANA_REG6_BATRTCDISC ANA_REG6_BATRTCDISC_Msk +#define ANA_REG6_BAT1DISC_Pos (6UL) /*!< ANA REG6: BAT1DISC (Bit 6) */ +#define ANA_REG6_BAT1DISC_Msk (0x40UL) /*!< ANA REG6: BAT1DISC (Bitfield-Mask: 0x01) */ +#define ANA_REG6_BAT1DISC ANA_REG6_BAT1DISC_Msk +#define ANA_REG6_LCDBMODE_Pos (0UL) /*!< ANA REG6: LCDBMODE (Bit 0) */ +#define ANA_REG6_LCDBMODE_Msk (0x1UL) /*!< ANA REG6: LCDBMODE (Bitfield-Mask: 0x01) */ +#define ANA_REG6_LCDBMODE ANA_REG6_LCDBMODE_Msk +/* ========================================================= REG7 ========================================================== */ +#define ANA_REG7_VDCINHYSSEL_Pos (2UL) /*!< ANA REG7: VDCINHYSSEL (Bit 2) */ +#define ANA_REG7_VDCINHYSSEL_Msk (0x4UL) /*!< ANA REG7: VDCINHYSSEL (Bitfield-Mask: 0x01) */ +#define ANA_REG7_VDCINHYSSEL ANA_REG7_VDCINHYSSEL_Msk +/* ========================================================= REG8 ========================================================== */ +#define ANA_REG8_AVCCLDOPD_Pos (7UL) /*!< ANA REG8: AVCCLDOPD (Bit 7) */ +#define ANA_REG8_AVCCLDOPD_Msk (0x80UL) /*!< ANA REG8: AVCCLDOPD (Bitfield-Mask: 0x01) */ +#define ANA_REG8_AVCCLDOPD ANA_REG8_AVCCLDOPD_Msk +#define ANA_REG8_VDDPVDSEL_Pos (4UL) /*!< ANA REG8: VDDPVDSEL (Bit 4) */ +#define ANA_REG8_VDDPVDSEL_Msk (0x70UL) /*!< ANA REG8: VDDPVDSEL (Bitfield-Mask: 0x07) */ +#define ANA_REG8_VDDPVDSEL ANA_REG8_VDDPVDSEL_Msk +#define ANA_REG8_DVCCSEL_Pos (0UL) /*!< ANA REG8: DVCCSEL (Bit 0) */ +#define ANA_REG8_DVCCSEL_Msk (0x3UL) /*!< ANA REG8: DVCCSEL (Bitfield-Mask: 0x03) */ +#define ANA_REG8_DVCCSEL ANA_REG8_DVCCSEL_Msk +/* ========================================================= REG9 ========================================================== */ +#define ANA_REG9_VDDDETPD_Pos (7UL) /*!< ANA REG9: VDDDETPD (Bit 7) */ +#define ANA_REG9_VDDDETPD_Msk (0x80UL) /*!< ANA REG9: VDDDETPD (Bitfield-Mask: 0x01) */ +#define ANA_REG9_VDDDETPD ANA_REG9_VDDDETPD_Msk +#define ANA_REG9_PLLHSEL_Pos (3UL) /*!< ANA REG9: PLLHSEL (Bit 3) */ +#define ANA_REG9_PLLHSEL_Msk (0x78UL) /*!< ANA REG9: PLLHSEL (Bitfield-Mask: 0x0f) */ +#define ANA_REG9_PLLHSEL ANA_REG9_PLLHSEL_Msk +#define ANA_REG9_PLLLSEL_Pos (0UL) /*!< ANA REG9: PLLLSEL (Bit 0) */ +#define ANA_REG9_PLLLSEL_Msk (0x7UL) /*!< ANA REG9: PLLLSEL (Bitfield-Mask: 0x07) */ +#define ANA_REG9_PLLLSEL ANA_REG9_PLLLSEL_Msk +/* ========================================================= REGA ========================================================== */ +#define ANA_REGA_VDCINDETPD_Pos (7UL) /*!< ANA REGA: VDCINDETPD (Bit 7) */ +#define ANA_REGA_VDCINDETPD_Msk (0x80UL) /*!< ANA REGA: VDCINDETPD (Bitfield-Mask: 0x01) */ +#define ANA_REGA_VDCINDETPD ANA_REGA_VDCINDETPD_Msk +/* ========================================================= REGB ========================================================== */ +#define ANA_REGB_RCLTRIM_Pos (0UL) /*!< ANA REGB: RCLTRIM (Bit 0) */ +#define ANA_REGB_RCLTRIM_Msk (0x1fUL) /*!< ANA REGB: RCLTRIM (Bitfield-Mask: 0x1f) */ +#define ANA_REGB_RCLTRIM ANA_REGB_RCLTRIM_Msk +/* ========================================================= REGC ========================================================== */ +#define ANA_REGC_RCHTRIM_Pos (0UL) /*!< ANA REGC: RCHTRIM (Bit 0) */ +#define ANA_REGC_RCHTRIM_Msk (0x3fUL) /*!< ANA REGC: RCHTRIM (Bitfield-Mask: 0x3f) */ +#define ANA_REGC_RCHTRIM ANA_REGC_RCHTRIM_Msk +/* ========================================================= REGD ========================================================== */ +/* ========================================================= REGE ========================================================== */ +#define ANA_REGE_BKPWREN_Pos (7UL) /*!< ANA REGE: BKPWREN (Bit 7) */ +#define ANA_REGE_BKPWREN_Msk (0x80UL) /*!< ANA REGE: BKPWREN (Bitfield-Mask: 0x01) */ +#define ANA_REGE_BKPWREN ANA_REGE_BKPWREN_Msk +/* ========================================================= REGF ========================================================== */ +#define ANA_REGF_ADTREF3SEL_Pos (7UL) /*!< ANA REGF: ADTREF3SEL (Bit 7) */ +#define ANA_REGF_ADTREF3SEL_Msk (0x80UL) /*!< ANA REGF: ADTREF3SEL (Bitfield-Mask: 0x01) */ +#define ANA_REGF_ADTREF3SEL ANA_REGF_ADTREF3SEL_Msk +#define ANA_REGF_ADTREF2SEL_Pos (6UL) /*!< ANA REGF: ADTREF2SEL (Bit 6) */ +#define ANA_REGF_ADTREF2SEL_Msk (0x40UL) /*!< ANA REGF: ADTREF2SEL (Bitfield-Mask: 0x01) */ +#define ANA_REGF_ADTREF2SEL ANA_REGF_ADTREF2SEL_Msk +#define ANA_REGF_ADTREF1SEL_Pos (5UL) /*!< ANA REGF: ADTREF1SEL (Bit 5) */ +#define ANA_REGF_ADTREF1SEL_Msk (0x20UL) /*!< ANA REGF: ADTREF1SEL (Bitfield-Mask: 0x01) */ +#define ANA_REGF_ADTREF1SEL ANA_REGF_ADTREF1SEL_Msk +#define ANA_REGF_ADTSEL_Pos (4UL) /*!< ANA REGF: ADTSEL (Bit 4) */ +#define ANA_REGF_ADTSEL_Msk (0x10UL) /*!< ANA REGF: ADTSEL (Bitfield-Mask: 0x01) */ +#define ANA_REGF_ADTSEL ANA_REGF_ADTSEL_Msk +#define ANA_REGF_ADTPDN_Pos (3UL) /*!< ANA REGF: ADTPDN (Bit 3) */ +#define ANA_REGF_ADTPDN_Msk (0x8UL) /*!< ANA REGF: ADTPDN (Bitfield-Mask: 0x01) */ +#define ANA_REGF_ADTPDN ANA_REGF_ADTPDN_Msk +#define ANA_REGF_AVCCOEN_Pos (2UL) /*!< ANA REGF: AVCCOEN (Bit 2) */ +#define ANA_REGF_AVCCOEN_Msk (0x4UL) /*!< ANA REGF: AVCCOEN (Bitfield-Mask: 0x01) */ +#define ANA_REGF_AVCCOEN ANA_REGF_AVCCOEN_Msk +#define ANA_REGF_BATRTCDETEN_Pos (1UL) /*!< ANA REGF: BATRTCDETEN (Bit 1) */ +#define ANA_REGF_BATRTCDETEN_Msk (0x2UL) /*!< ANA REGF: BATRTCDETEN (Bitfield-Mask: 0x01) */ +#define ANA_REGF_BATRTCDETEN ANA_REGF_BATRTCDETEN_Msk +#define ANA_REGF_BAT1DETEN_Pos (0UL) /*!< ANA REGF: BAT1DETEN (Bit 0) */ +#define ANA_REGF_BAT1DETEN_Msk (0x1UL) /*!< ANA REGF: BAT1DETEN (Bitfield-Mask: 0x01) */ +#define ANA_REGF_BAT1DETEN ANA_REGF_BAT1DETEN_Msk +/* ========================================================= REG10 ========================================================= */ +/* ========================================================= REG11 ========================================================= */ +#define ANA_REG11_VINBUFPD_Pos (7UL) /*!< ANA REG11: VINBUFPD (Bit 7) */ +#define ANA_REG11_VINBUFPD_Msk (0x80UL) /*!< ANA REG11: VINBUFPD (Bitfield-Mask: 0x01) */ +#define ANA_REG11_VINBUFPD ANA_REG11_VINBUFPD_Msk +#define ANA_REG11_REFBUFPD_Pos (6UL) /*!< ANA REG11: REFBUFPD (Bit 6) */ +#define ANA_REG11_REFBUFPD_Msk (0x40UL) /*!< ANA REG11: REFBUFPD (Bitfield-Mask: 0x01) */ +#define ANA_REG11_REFBUFPD ANA_REG11_REFBUFPD_Msk +/* ========================================================= CTRL ========================================================== */ +#define ANA_CTRL_PDNS2_Pos (26UL) /*!< ANA CTRL: PDNS2 (Bit 26) */ +#define ANA_CTRL_PDNS2_Msk (0x4000000UL) /*!< ANA CTRL: PDNS2 (Bitfield-Mask: 0x01) */ +#define ANA_CTRL_PDNS2 ANA_CTRL_PDNS2_Msk +#define ANA_CTRL_CMP2DEB_Pos (22UL) /*!< ANA CTRL: CMP2DEB (Bit 22) */ +#define ANA_CTRL_CMP2DEB_Msk (0xc00000UL) /*!< ANA CTRL: CMP2DEB (Bitfield-Mask: 0x03) */ +#define ANA_CTRL_CMP2DEB ANA_CTRL_CMP2DEB_Msk +#define ANA_CTRL_CMP1DEB_Pos (20UL) /*!< ANA CTRL: CMP1DEB (Bit 20) */ +#define ANA_CTRL_CMP1DEB_Msk (0x300000UL) /*!< ANA CTRL: CMP1DEB (Bitfield-Mask: 0x03) */ +#define ANA_CTRL_CMP1DEB ANA_CTRL_CMP1DEB_Msk +#define ANA_CTRL_RCHTGT_Pos (8UL) /*!< ANA CTRL: RCHTGT (Bit 8) */ +#define ANA_CTRL_RCHTGT_Msk (0xff00UL) /*!< ANA CTRL: RCHTGT (Bitfield-Mask: 0xff) */ +#define ANA_CTRL_RCHTGT ANA_CTRL_RCHTGT_Msk +#define ANA_CTRL_PDNS_Pos (6UL) /*!< ANA CTRL: PDNS (Bit 6) */ +#define ANA_CTRL_PDNS_Msk (0x40UL) /*!< ANA CTRL: PDNS (Bitfield-Mask: 0x01) */ +#define ANA_CTRL_PDNS ANA_CTRL_PDNS_Msk +#define ANA_CTRL_CMP2SEL_Pos (2UL) /*!< ANA CTRL: CMP2SEL (Bit 2) */ +#define ANA_CTRL_CMP2SEL_Msk (0xcUL) /*!< ANA CTRL: CMP2SEL (Bitfield-Mask: 0x03) */ +#define ANA_CTRL_CMP2SEL ANA_CTRL_CMP2SEL_Msk +#define ANA_CTRL_CMP1SEL_Pos (0UL) /*!< ANA CTRL: CMP1SEL (Bit 0) */ +#define ANA_CTRL_CMP1SEL_Msk (0x3UL) /*!< ANA CTRL: CMP1SEL (Bitfield-Mask: 0x03) */ +#define ANA_CTRL_CMP1SEL ANA_CTRL_CMP1SEL_Msk +/* ======================================================== CMPOUT ========================================================= */ +#define ANA_CMPOUT_TADCO_Pos (14UL) /*!< ANA CMPOUT: TADCO (Bit 14) */ +#define ANA_CMPOUT_TADCO_Msk (0xc000UL) /*!< ANA CMPOUT: TADCO (Bitfield-Mask: 0x03) */ +#define ANA_CMPOUT_TADCO ANA_CMPOUT_TADCO_Msk +#define ANA_CMPOUT_AVCCLV_Pos (10UL) /*!< ANA CMPOUT: AVCCLV (Bit 10) */ +#define ANA_CMPOUT_AVCCLV_Msk (0x400UL) /*!< ANA CMPOUT: AVCCLV (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_AVCCLV ANA_CMPOUT_AVCCLV_Msk +#define ANA_CMPOUT_VDCINDROP_Pos (8UL) /*!< ANA CMPOUT: VDCINDROP (Bit 8) */ +#define ANA_CMPOUT_VDCINDROP_Msk (0x100UL) /*!< ANA CMPOUT: VDCINDROP (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_VDCINDROP ANA_CMPOUT_VDCINDROP_Msk +#define ANA_CMPOUT_VDDALARM_Pos (7UL) /*!< ANA CMPOUT: VDDALARM (Bit 7) */ +#define ANA_CMPOUT_VDDALARM_Msk (0x80UL) /*!< ANA CMPOUT: VDDALARM (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_VDDALARM ANA_CMPOUT_VDDALARM_Msk +#define ANA_CMPOUT_CMP2_Pos (3UL) /*!< ANA CMPOUT: CMP2 (Bit 3) */ +#define ANA_CMPOUT_CMP2_Msk (0x8UL) /*!< ANA CMPOUT: CMP2 (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_CMP2 ANA_CMPOUT_CMP2_Msk +#define ANA_CMPOUT_CMP1_Pos (2UL) /*!< ANA CMPOUT: CMP1 (Bit 2) */ +#define ANA_CMPOUT_CMP1_Msk (0x4UL) /*!< ANA CMPOUT: CMP1 (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_CMP1 ANA_CMPOUT_CMP1_Msk +#define ANA_CMPOUT_LOCKL_Pos (1UL) /*!< ANA CMPOUT: LOCKL (Bit 1) */ +#define ANA_CMPOUT_LOCKL_Msk (0x2UL) /*!< ANA CMPOUT: LOCKL (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_LOCKL ANA_CMPOUT_LOCKL_Msk +#define ANA_CMPOUT_LOCKH_Pos (0UL) /*!< ANA CMPOUT: LOCKH (Bit 0) */ +#define ANA_CMPOUT_LOCKH_Msk (0x1UL) /*!< ANA CMPOUT: LOCKH (Bitfield-Mask: 0x01) */ +#define ANA_CMPOUT_LOCKH ANA_CMPOUT_LOCKH_Msk +/* ======================================================= ADCSTATE ======================================================== */ +#define ANA_ADCSTATE_CAL_EN_Pos (5UL) /*!< ANA ADCSTATE: CAL_EN (Bit 5) */ +#define ANA_ADCSTATE_CAL_EN_Msk (0x20UL) /*!< ANA ADCSTATE: CAL_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCSTATE_CAL_EN ANA_ADCSTATE_CAL_EN_Msk +#define ANA_ADCSTATE_RESET_Pos (4UL) /*!< ANA ADCSTATE: RESET (Bit 4) */ +#define ANA_ADCSTATE_RESET_Msk (0x10UL) /*!< ANA ADCSTATE: RESET (Bitfield-Mask: 0x01) */ +#define ANA_ADCSTATE_RESET ANA_ADCSTATE_RESET_Msk +#define ANA_ADCSTATE_ADC_EN_Pos (3UL) /*!< ANA ADCSTATE: ADC_EN (Bit 3) */ +#define ANA_ADCSTATE_ADC_EN_Msk (0x8UL) /*!< ANA ADCSTATE: ADC_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCSTATE_ADC_EN ANA_ADCSTATE_ADC_EN_Msk +#define ANA_ADCSTATE_ADCSTATE_Pos (0UL) /*!< ANA ADCSTATE: ADCSTATE (Bit 0) */ +#define ANA_ADCSTATE_ADCSTATE_Msk (0x7UL) /*!< ANA ADCSTATE: ADCSTATE (Bitfield-Mask: 0x07) */ +#define ANA_ADCSTATE_ADCSTATE ANA_ADCSTATE_ADCSTATE_Msk +/* ======================================================== INTSTS ========================================================= */ +#define ANA_INTSTS_INTSTS21_Pos (21UL) /*!< ANA INTSTS: INTSTS21 (Bit 21) */ +#define ANA_INTSTS_INTSTS21_Msk (0x200000UL) /*!< ANA INTSTS: INTSTS21 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS21 ANA_INTSTS_INTSTS21_Msk +#define ANA_INTSTS_INTSTS20_Pos (20UL) /*!< ANA INTSTS: INTSTS20 (Bit 20) */ +#define ANA_INTSTS_INTSTS20_Msk (0x100000UL) /*!< ANA INTSTS: INTSTS20 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS20 ANA_INTSTS_INTSTS20_Msk +#define ANA_INTSTS_INTSTS19_Pos (19UL) /*!< ANA INTSTS: INTSTS19 (Bit 19) */ +#define ANA_INTSTS_INTSTS19_Msk (0x80000UL) /*!< ANA INTSTS: INTSTS19 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS19 ANA_INTSTS_INTSTS19_Msk +#define ANA_INTSTS_INTSTS18_Pos (18UL) /*!< ANA INTSTS: INTSTS18 (Bit 18) */ +#define ANA_INTSTS_INTSTS18_Msk (0x40000UL) /*!< ANA INTSTS: INTSTS18 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS18 ANA_INTSTS_INTSTS18_Msk +#define ANA_INTSTS_INTSTS17_Pos (17UL) /*!< ANA INTSTS: INTSTS17 (Bit 17) */ +#define ANA_INTSTS_INTSTS17_Msk (0x20000UL) /*!< ANA INTSTS: INTSTS17 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS17 ANA_INTSTS_INTSTS17_Msk +#define ANA_INTSTS_INTSTS16_Pos (16UL) /*!< ANA INTSTS: INTSTS16 (Bit 16) */ +#define ANA_INTSTS_INTSTS16_Msk (0x10000UL) /*!< ANA INTSTS: INTSTS16 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS16 ANA_INTSTS_INTSTS16_Msk +#define ANA_INTSTS_INTSTS15_Pos (15UL) /*!< ANA INTSTS: INTSTS15 (Bit 15) */ +#define ANA_INTSTS_INTSTS15_Msk (0x8000UL) /*!< ANA INTSTS: INTSTS15 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS15 ANA_INTSTS_INTSTS15_Msk +#define ANA_INTSTS_INTSTS14_Pos (14UL) /*!< ANA INTSTS: INTSTS14 (Bit 14) */ +#define ANA_INTSTS_INTSTS14_Msk (0x4000UL) /*!< ANA INTSTS: INTSTS14 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS14 ANA_INTSTS_INTSTS14_Msk +#define ANA_INTSTS_INTSTS13_Pos (13UL) /*!< ANA INTSTS: INTSTS13 (Bit 13) */ +#define ANA_INTSTS_INTSTS13_Msk (0x2000UL) /*!< ANA INTSTS: INTSTS13 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS13 ANA_INTSTS_INTSTS13_Msk +#define ANA_INTSTS_INTSTS12_Pos (12UL) /*!< ANA INTSTS: INTSTS12 (Bit 12) */ +#define ANA_INTSTS_INTSTS12_Msk (0x1000UL) /*!< ANA INTSTS: INTSTS12 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS12 ANA_INTSTS_INTSTS12_Msk +#define ANA_INTSTS_INTSTS11_Pos (11UL) /*!< ANA INTSTS: INTSTS11 (Bit 11) */ +#define ANA_INTSTS_INTSTS11_Msk (0x800UL) /*!< ANA INTSTS: INTSTS11 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS11 ANA_INTSTS_INTSTS11_Msk +#define ANA_INTSTS_INTSTS10_Pos (10UL) /*!< ANA INTSTS: INTSTS10 (Bit 10) */ +#define ANA_INTSTS_INTSTS10_Msk (0x400UL) /*!< ANA INTSTS: INTSTS10 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS10 ANA_INTSTS_INTSTS10_Msk +#define ANA_INTSTS_INTSTS8_Pos (8UL) /*!< ANA INTSTS: INTSTS8 (Bit 8) */ +#define ANA_INTSTS_INTSTS8_Msk (0x100UL) /*!< ANA INTSTS: INTSTS8 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS8 ANA_INTSTS_INTSTS8_Msk +#define ANA_INTSTS_INTSTS7_Pos (7UL) /*!< ANA INTSTS: INTSTS7 (Bit 7) */ +#define ANA_INTSTS_INTSTS7_Msk (0x80UL) /*!< ANA INTSTS: INTSTS7 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS7 ANA_INTSTS_INTSTS7_Msk +#define ANA_INTSTS_INTSTS3_Pos (3UL) /*!< ANA INTSTS: INTSTS3 (Bit 3) */ +#define ANA_INTSTS_INTSTS3_Msk (0x8UL) /*!< ANA INTSTS: INTSTS3 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS3 ANA_INTSTS_INTSTS3_Msk +#define ANA_INTSTS_INTSTS2_Pos (2UL) /*!< ANA INTSTS: INTSTS2 (Bit 2) */ +#define ANA_INTSTS_INTSTS2_Msk (0x4UL) /*!< ANA INTSTS: INTSTS2 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS2 ANA_INTSTS_INTSTS2_Msk +#define ANA_INTSTS_INTSTS1_Pos (1UL) /*!< ANA INTSTS: INTSTS1 (Bit 1) */ +#define ANA_INTSTS_INTSTS1_Msk (0x2UL) /*!< ANA INTSTS: INTSTS1 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS1 ANA_INTSTS_INTSTS1_Msk +#define ANA_INTSTS_INTSTS0_Pos (0UL) /*!< ANA INTSTS: INTSTS0 (Bit 0) */ +#define ANA_INTSTS_INTSTS0_Msk (0x1UL) /*!< ANA INTSTS: INTSTS0 (Bitfield-Mask: 0x01) */ +#define ANA_INTSTS_INTSTS0 ANA_INTSTS_INTSTS0_Msk +/* ========================================================= INTEN ========================================================= */ +#define ANA_INTEN_INTEN21_Pos (21UL) /*!< ANA INTEN: INTEN21 (Bit 21) */ +#define ANA_INTEN_INTEN21_Msk (0x200000UL) /*!< ANA INTEN: INTEN21 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN21 ANA_INTEN_INTEN21_Msk +#define ANA_INTEN_INTEN20_Pos (20UL) /*!< ANA INTEN: INTEN20 (Bit 20) */ +#define ANA_INTEN_INTEN20_Msk (0x100000UL) /*!< ANA INTEN: INTEN20 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN20 ANA_INTEN_INTEN20_Msk +#define ANA_INTEN_INTEN19_Pos (19UL) /*!< ANA INTEN: INTEN19 (Bit 19) */ +#define ANA_INTEN_INTEN19_Msk (0x80000UL) /*!< ANA INTEN: INTEN19 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN19 ANA_INTEN_INTEN19_Msk +#define ANA_INTEN_INTEN18_Pos (18UL) /*!< ANA INTEN: INTEN18 (Bit 18) */ +#define ANA_INTEN_INTEN18_Msk (0x40000UL) /*!< ANA INTEN: INTEN18 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN18 ANA_INTEN_INTEN18_Msk +#define ANA_INTEN_INTEN17_Pos (17UL) /*!< ANA INTEN: INTEN17 (Bit 17) */ +#define ANA_INTEN_INTEN17_Msk (0x20000UL) /*!< ANA INTEN: INTEN17 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN17 ANA_INTEN_INTEN17_Msk +#define ANA_INTEN_INTEN16_Pos (16UL) /*!< ANA INTEN: INTEN16 (Bit 16) */ +#define ANA_INTEN_INTEN16_Msk (0x10000UL) /*!< ANA INTEN: INTEN16 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN16 ANA_INTEN_INTEN16_Msk +#define ANA_INTEN_INTEN15_Pos (15UL) /*!< ANA INTEN: INTEN15 (Bit 15) */ +#define ANA_INTEN_INTEN15_Msk (0x8000UL) /*!< ANA INTEN: INTEN15 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN15 ANA_INTEN_INTEN15_Msk +#define ANA_INTEN_INTEN14_Pos (14UL) /*!< ANA INTEN: INTEN14 (Bit 14) */ +#define ANA_INTEN_INTEN14_Msk (0x4000UL) /*!< ANA INTEN: INTEN14 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN14 ANA_INTEN_INTEN14_Msk +#define ANA_INTEN_INTEN13_Pos (13UL) /*!< ANA INTEN: INTEN13 (Bit 13) */ +#define ANA_INTEN_INTEN13_Msk (0x2000UL) /*!< ANA INTEN: INTEN13 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN13 ANA_INTEN_INTEN13_Msk +#define ANA_INTEN_INTEN12_Pos (12UL) /*!< ANA INTEN: INTEN12 (Bit 12) */ +#define ANA_INTEN_INTEN12_Msk (0x1000UL) /*!< ANA INTEN: INTEN12 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN12 ANA_INTEN_INTEN12_Msk +#define ANA_INTEN_INTEN11_Pos (11UL) /*!< ANA INTEN: INTEN11 (Bit 11) */ +#define ANA_INTEN_INTEN11_Msk (0x800UL) /*!< ANA INTEN: INTEN11 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN11 ANA_INTEN_INTEN11_Msk +#define ANA_INTEN_INTEN10_Pos (10UL) /*!< ANA INTEN: INTEN10 (Bit 10) */ +#define ANA_INTEN_INTEN10_Msk (0x400UL) /*!< ANA INTEN: INTEN10 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN10 ANA_INTEN_INTEN10_Msk +#define ANA_INTEN_INTEN8_Pos (8UL) /*!< ANA INTEN: INTEN8 (Bit 8) */ +#define ANA_INTEN_INTEN8_Msk (0x100UL) /*!< ANA INTEN: INTEN8 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN8 ANA_INTEN_INTEN8_Msk +#define ANA_INTEN_INTEN7_Pos (7UL) /*!< ANA INTEN: INTEN7 (Bit 7) */ +#define ANA_INTEN_INTEN7_Msk (0x80UL) /*!< ANA INTEN: INTEN7 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN7 ANA_INTEN_INTEN7_Msk +#define ANA_INTEN_INTEN3_Pos (3UL) /*!< ANA INTEN: INTEN3 (Bit 3) */ +#define ANA_INTEN_INTEN3_Msk (0x8UL) /*!< ANA INTEN: INTEN3 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN3 ANA_INTEN_INTEN3_Msk +#define ANA_INTEN_INTEN2_Pos (2UL) /*!< ANA INTEN: INTEN2 (Bit 2) */ +#define ANA_INTEN_INTEN2_Msk (0x4UL) /*!< ANA INTEN: INTEN2 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN2 ANA_INTEN_INTEN2_Msk +#define ANA_INTEN_INTEN1_Pos (1UL) /*!< ANA INTEN: INTEN1 (Bit 1) */ +#define ANA_INTEN_INTEN1_Msk (0x2UL) /*!< ANA INTEN: INTEN1 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN1 ANA_INTEN_INTEN1_Msk +#define ANA_INTEN_INTEN0_Pos (0UL) /*!< ANA INTEN: INTEN0 (Bit 0) */ +#define ANA_INTEN_INTEN0_Msk (0x1UL) /*!< ANA INTEN: INTEN0 (Bitfield-Mask: 0x01) */ +#define ANA_INTEN_INTEN0 ANA_INTEN_INTEN0_Msk +/* ======================================================= ADCCTRL0 ======================================================== */ +#define ANA_ADCCTRL0_MTRIG_Pos (31UL) /*!< ANA ADCCTRL0: MTRIG (Bit 31) */ +#define ANA_ADCCTRL0_MTRIG_Msk (0x80000000UL) /*!< ANA ADCCTRL0: MTRIG (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL0_MTRIG ANA_ADCCTRL0_MTRIG_Msk +#define ANA_ADCCTRL0_STOP_Pos (19UL) /*!< ANA ADCCTRL0: STOP (Bit 19) */ +#define ANA_ADCCTRL0_STOP_Msk (0x80000UL) /*!< ANA ADCCTRL0: STOP (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL0_STOP ANA_ADCCTRL0_STOP_Msk +#define ANA_ADCCTRL0_AEN_Pos (16UL) /*!< ANA ADCCTRL0: AEN (Bit 16) */ +#define ANA_ADCCTRL0_AEN_Msk (0x70000UL) /*!< ANA ADCCTRL0: AEN (Bitfield-Mask: 0x07) */ +#define ANA_ADCCTRL0_AEN ANA_ADCCTRL0_AEN_Msk +#define ANA_ADCCTRL0_CLKSRCSEL_Pos (12UL) /*!< ANA ADCCTRL0: CLKSRCSEL (Bit 12) */ +#define ANA_ADCCTRL0_CLKSRCSEL_Msk (0x1000UL) /*!< ANA ADCCTRL0: CLKSRCSEL (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL0_CLKSRCSEL ANA_ADCCTRL0_CLKSRCSEL_Msk +/* ======================================================== CMPCTL ========================================================= */ +#define ANA_CMPCTL_PWR_DEB_SEL_Pos (24UL) /*!< ANA CMPCTL: PWR_DEB_SEL (Bit 24) */ +#define ANA_CMPCTL_PWR_DEB_SEL_Msk (0xff000000UL) /*!< ANA CMPCTL: PWR_DEB_SEL (Bitfield-Mask: 0xff) */ +#define ANA_CMPCTL_PWR_DEB_SEL ANA_CMPCTL_PWR_DEB_SEL_Msk +#define ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos (22UL) /*!< ANA CMPCTL: VDDALARM_CHK_FRQ_SEL (Bit 22) */ +#define ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Msk (0xc00000UL) /*!< ANA CMPCTL: VDDALARM_CHK_FRQ_SEL (Bitfield-Mask: 0x03) */ +#define ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Msk +#define ANA_CMPCTL_CMP2_IO_NODEB_Pos (21UL) /*!< ANA CMPCTL: CMP2_IO_NODEB (Bit 21) */ +#define ANA_CMPCTL_CMP2_IO_NODEB_Msk (0x200000UL) /*!< ANA CMPCTL: CMP2_IO_NODEB (Bitfield-Mask: 0x01) */ +#define ANA_CMPCTL_CMP2_IO_NODEB ANA_CMPCTL_CMP2_IO_NODEB_Msk +#define ANA_CMPCTL_CMP2_INT_MASK_EN_Pos (20UL) /*!< ANA CMPCTL: CMP2_INT_MASK_EN (Bit 20) */ +#define ANA_CMPCTL_CMP2_INT_MASK_EN_Msk (0x100000UL) /*!< ANA CMPCTL: CMP2_INT_MASK_EN (Bitfield-Mask: 0x01) */ +#define ANA_CMPCTL_CMP2_INT_MASK_EN ANA_CMPCTL_CMP2_INT_MASK_EN_Msk +#define ANA_CMPCTL_CMP1_IO_NODEB_Pos (17UL) /*!< ANA CMPCTL: CMP1_IO_NODEB (Bit 17) */ +#define ANA_CMPCTL_CMP1_IO_NODEB_Msk (0x20000UL) /*!< ANA CMPCTL: CMP1_IO_NODEB (Bitfield-Mask: 0x01) */ +#define ANA_CMPCTL_CMP1_IO_NODEB ANA_CMPCTL_CMP1_IO_NODEB_Msk +#define ANA_CMPCTL_CMP1_INT_MASK_EN_Pos (16UL) /*!< ANA CMPCTL: CMP1_INT_MASK_EN (Bit 16) */ +#define ANA_CMPCTL_CMP1_INT_MASK_EN_Msk (0x10000UL) /*!< ANA CMPCTL: CMP1_INT_MASK_EN (Bitfield-Mask: 0x01) */ +#define ANA_CMPCTL_CMP1_INT_MASK_EN ANA_CMPCTL_CMP1_INT_MASK_EN_Msk +#define ANA_CMPCTL_CMP2_CHK_NUM_Pos (12UL) /*!< ANA CMPCTL: CMP2_CHK_NUM (Bit 12) */ +#define ANA_CMPCTL_CMP2_CHK_NUM_Msk (0xf000UL) /*!< ANA CMPCTL: CMP2_CHK_NUM (Bitfield-Mask: 0x0f) */ +#define ANA_CMPCTL_CMP2_CHK_NUM ANA_CMPCTL_CMP2_CHK_NUM_Msk +#define ANA_CMPCTL_CMP2_THR_EN_Pos (11UL) /*!< ANA CMPCTL: CMP2_THR_EN (Bit 11) */ +#define ANA_CMPCTL_CMP2_THR_EN_Msk (0x800UL) /*!< ANA CMPCTL: CMP2_THR_EN (Bitfield-Mask: 0x01) */ +#define ANA_CMPCTL_CMP2_THR_EN ANA_CMPCTL_CMP2_THR_EN_Msk +#define ANA_CMPCTL_CMP2_CHK_FRQ_Pos (8UL) /*!< ANA CMPCTL: CMP2_CHK_FRQ (Bit 8) */ +#define ANA_CMPCTL_CMP2_CHK_FRQ_Msk (0x700UL) /*!< ANA CMPCTL: CMP2_CHK_FRQ (Bitfield-Mask: 0x07) */ +#define ANA_CMPCTL_CMP2_CHK_FRQ ANA_CMPCTL_CMP2_CHK_FRQ_Msk +#define ANA_CMPCTL_CMP1_CHK_NUM_Pos (4UL) /*!< ANA CMPCTL: CMP1_CHK_NUM (Bit 4) */ +#define ANA_CMPCTL_CMP1_CHK_NUM_Msk (0xf0UL) /*!< ANA CMPCTL: CMP1_CHK_NUM (Bitfield-Mask: 0x0f) */ +#define ANA_CMPCTL_CMP1_CHK_NUM ANA_CMPCTL_CMP1_CHK_NUM_Msk +#define ANA_CMPCTL_CMP1_THR_EN_Pos (3UL) /*!< ANA CMPCTL: CMP1_THR_EN (Bit 3) */ +#define ANA_CMPCTL_CMP1_THR_EN_Msk (0x8UL) /*!< ANA CMPCTL: CMP1_THR_EN (Bitfield-Mask: 0x01) */ +#define ANA_CMPCTL_CMP1_THR_EN ANA_CMPCTL_CMP1_THR_EN_Msk +#define ANA_CMPCTL_CMP1_CHK_FRQ_Pos (0UL) /*!< ANA CMPCTL: CMP1_CHK_FRQ (Bit 0) */ +#define ANA_CMPCTL_CMP1_CHK_FRQ_Msk (0x7UL) /*!< ANA CMPCTL: CMP1_CHK_FRQ (Bitfield-Mask: 0x07) */ +#define ANA_CMPCTL_CMP1_CHK_FRQ ANA_CMPCTL_CMP1_CHK_FRQ_Msk +/* ======================================================== ADCDATA ======================================================== */ +#define ANA_ADCDATA_ADCDATA_Pos (0UL) /*!< ANA ADCDATA: ADCDATA (Bit 0) */ +#define ANA_ADCDATA_ADCDATA_Msk (0xffffUL) /*!< ANA ADCDATA: ADCDATA (Bitfield-Mask: 0xffff) */ +#define ANA_ADCDATA_ADCDATA ANA_ADCDATA_ADCDATA_Msk +/* ======================================================== CMPCNT ========================================================= */ +#define ANA_CMPCNT_CNT_Pos (0UL) /*!< ANA CMPCNT: CNT (Bit 0) */ +#define ANA_CMPCNT_CNT_Msk (0xffffffffUL) /*!< ANA CMPCNT: CNT (Bitfield-Mask: 0xffffffff) */ +#define ANA_CMPCNT_CNT ANA_CMPCNT_CNT_Msk +/* ========================================================= MISC ========================================================== */ +#define ANA_MISC_TADCTH_Pos (4UL) /*!< ANA MISC: TADCTH (Bit 4) */ +#define ANA_MISC_TADCTH_Msk (0x30UL) /*!< ANA MISC: TADCTH (Bitfield-Mask: 0x03) */ +#define ANA_MISC_TADCTH ANA_MISC_TADCTH_Msk +/* ======================================================== ADCDOS ========================================================= */ +#define ANA_ADCDOS_DOS_Pos (0UL) /*!< ANA ADCDOS: DOS (Bit 0) */ +#define ANA_ADCDOS_DOS_Msk (0x1ffUL) /*!< ANA ADCDOS: DOS (Bitfield-Mask: 0x1ff) */ +#define ANA_ADCDOS_DOS ANA_ADCDOS_DOS_Msk +/* ======================================================== ADCDCPN ======================================================== */ +#define ANA_ADCDCPN_DCPN4_Pos (27UL) /*!< ANA ADCDCPN: DCPN4 (Bit 27) */ +#define ANA_ADCDCPN_DCPN4_Msk (0xf8000000UL) /*!< ANA ADCDCPN: DCPN4 (Bitfield-Mask: 0x1f) */ +#define ANA_ADCDCPN_DCPN4 ANA_ADCDCPN_DCPN4_Msk +#define ANA_ADCDCPN_DCPN3_Pos (18UL) /*!< ANA ADCDCPN: DCPN3 (Bit 18) */ +#define ANA_ADCDCPN_DCPN3_Msk (0x7fc0000UL) /*!< ANA ADCDCPN: DCPN3 (Bitfield-Mask: 0x1ff) */ +#define ANA_ADCDCPN_DCPN3 ANA_ADCDCPN_DCPN3_Msk +#define ANA_ADCDCPN_DCPN2_Pos (9UL) /*!< ANA ADCDCPN: DCPN2 (Bit 9) */ +#define ANA_ADCDCPN_DCPN2_Msk (0x3fe00UL) /*!< ANA ADCDCPN: DCPN2 (Bitfield-Mask: 0x1ff) */ +#define ANA_ADCDCPN_DCPN2 ANA_ADCDCPN_DCPN2_Msk +#define ANA_ADCDCPN_DCPN1_Pos (0UL) /*!< ANA ADCDCPN: DCPN1 (Bit 0) */ +#define ANA_ADCDCPN_DCPN1_Msk (0x1ffUL) /*!< ANA ADCDCPN: DCPN1 (Bitfield-Mask: 0x1ff) */ +#define ANA_ADCDCPN_DCPN1 ANA_ADCDCPN_DCPN1_Msk +/* ======================================================= ADCDCNM0 ======================================================== */ +#define ANA_ADCDCNM0_NM0_Pos (0UL) /*!< ANA ADCDCNM0: NM0 (Bit 0) */ +#define ANA_ADCDCNM0_NM0_Msk (0x1ffUL) /*!< ANA ADCDCNM0: NM0 (Bitfield-Mask: 0x1ff) */ +#define ANA_ADCDCNM0_NM0 ANA_ADCDCNM0_NM0_Msk +/* ====================================================== ADCDATADMA ======================================================= */ +#define ANA_ADCDATADMA_ADCDATA_DMA_Pos (0UL) /*!< ANA ADCDATADMA: ADCDATA_DMA (Bit 0) */ +#define ANA_ADCDATADMA_ADCDATA_DMA_Msk (0xffffUL) /*!< ANA ADCDATADMA: ADCDATA_DMA (Bitfield-Mask: 0xffff) */ +#define ANA_ADCDATADMA_ADCDATA_DMA ANA_ADCDATADMA_ADCDATA_DMA_Msk +/* ======================================================== CMPTHR ========================================================= */ +#define ANA_CMPTHR_CMP2_THR_Pos (16UL) /*!< ANA CMPTHR: CMP2_THR (Bit 16) */ +#define ANA_CMPTHR_CMP2_THR_Msk (0xffff0000UL) /*!< ANA CMPTHR: CMP2_THR (Bitfield-Mask: 0xffff) */ +#define ANA_CMPTHR_CMP2_THR ANA_CMPTHR_CMP2_THR_Msk +#define ANA_CMPTHR_CMP1_THR_Pos (0UL) /*!< ANA CMPTHR: CMP1_THR (Bit 0) */ +#define ANA_CMPTHR_CMP1_THR_Msk (0xffffUL) /*!< ANA CMPTHR: CMP1_THR (Bitfield-Mask: 0xffff) */ +#define ANA_CMPTHR_CMP1_THR ANA_CMPTHR_CMP1_THR_Msk +/* ======================================================= ADCCTRL1 ======================================================== */ +#define ANA_ADCCTRL1_RESDIV_CHx_Pos (16UL) /*!< ANA ADCCTRL1: RESDIV_CHx (Bit 16) */ +#define ANA_ADCCTRL1_RESDIV_CHx_Msk (0xffff0000UL) /*!< ANA ADCCTRL1: RESDIV_CHx (Bitfield-Mask: 0xffff) */ +#define ANA_ADCCTRL1_RESDIV_CHx ANA_ADCCTRL1_RESDIV_CHx_Msk +#define ANA_ADCCTRL1_UPPER_THD3_EN_Pos (15UL) /*!< ANA ADCCTRL1: UPPER_THD3_EN (Bit 15) */ +#define ANA_ADCCTRL1_UPPER_THD3_EN_Msk (0x8000UL) /*!< ANA ADCCTRL1: UPPER_THD3_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_UPPER_THD3_EN ANA_ADCCTRL1_UPPER_THD3_EN_Msk +#define ANA_ADCCTRL1_LOWER_THD3_EN_Pos (14UL) /*!< ANA ADCCTRL1: LOWER_THD3_EN (Bit 14) */ +#define ANA_ADCCTRL1_LOWER_THD3_EN_Msk (0x4000UL) /*!< ANA ADCCTRL1: LOWER_THD3_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_LOWER_THD3_EN ANA_ADCCTRL1_LOWER_THD3_EN_Msk +#define ANA_ADCCTRL1_UPPER_THD2_EN_Pos (13UL) /*!< ANA ADCCTRL1: UPPER_THD2_EN (Bit 13) */ +#define ANA_ADCCTRL1_UPPER_THD2_EN_Msk (0x2000UL) /*!< ANA ADCCTRL1: UPPER_THD2_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_UPPER_THD2_EN ANA_ADCCTRL1_UPPER_THD2_EN_Msk +#define ANA_ADCCTRL1_LOWER_THD2_EN_Pos (12UL) /*!< ANA ADCCTRL1: LOWER_THD2_EN (Bit 12) */ +#define ANA_ADCCTRL1_LOWER_THD2_EN_Msk (0x1000UL) /*!< ANA ADCCTRL1: LOWER_THD2_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_LOWER_THD2_EN ANA_ADCCTRL1_LOWER_THD2_EN_Msk +#define ANA_ADCCTRL1_UPPER_THD1_EN_Pos (11UL) /*!< ANA ADCCTRL1: UPPER_THD1_EN (Bit 11) */ +#define ANA_ADCCTRL1_UPPER_THD1_EN_Msk (0x800UL) /*!< ANA ADCCTRL1: UPPER_THD1_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_UPPER_THD1_EN ANA_ADCCTRL1_UPPER_THD1_EN_Msk +#define ANA_ADCCTRL1_LOWER_THD1_EN_Pos (10UL) /*!< ANA ADCCTRL1: LOWER_THD1_EN (Bit 10) */ +#define ANA_ADCCTRL1_LOWER_THD1_EN_Msk (0x400UL) /*!< ANA ADCCTRL1: LOWER_THD1_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_LOWER_THD1_EN ANA_ADCCTRL1_LOWER_THD1_EN_Msk +#define ANA_ADCCTRL1_UPPER_THD0_EN_Pos (9UL) /*!< ANA ADCCTRL1: UPPER_THD0_EN (Bit 9) */ +#define ANA_ADCCTRL1_UPPER_THD0_EN_Msk (0x200UL) /*!< ANA ADCCTRL1: UPPER_THD0_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_UPPER_THD0_EN ANA_ADCCTRL1_UPPER_THD0_EN_Msk +#define ANA_ADCCTRL1_LOWER_THD0_EN_Pos (8UL) /*!< ANA ADCCTRL1: LOWER_THD0_EN (Bit 8) */ +#define ANA_ADCCTRL1_LOWER_THD0_EN_Msk (0x100UL) /*!< ANA ADCCTRL1: LOWER_THD0_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL1_LOWER_THD0_EN ANA_ADCCTRL1_LOWER_THD0_EN_Msk +/* ======================================================= ADCCTRL2 ======================================================== */ +#define ANA_ADCCTRL2_SCAN_CHx_Pos (16UL) /*!< ANA ADCCTRL2: SCAN_CHx (Bit 16) */ +#define ANA_ADCCTRL2_SCAN_CHx_Msk (0xffff0000UL) /*!< ANA ADCCTRL2: SCAN_CHx (Bitfield-Mask: 0xffff) */ +#define ANA_ADCCTRL2_SCAN_CHx ANA_ADCCTRL2_SCAN_CHx_Msk +#define ANA_ADCCTRL2_CONV_ERR_Pos (11UL) /*!< ANA ADCCTRL2: CONV_ERR (Bit 11) */ +#define ANA_ADCCTRL2_CONV_ERR_Msk (0x800UL) /*!< ANA ADCCTRL2: CONV_ERR (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_CONV_ERR ANA_ADCCTRL2_CONV_ERR_Msk +#define ANA_ADCCTRL2_CAL_ERR_Pos (10UL) /*!< ANA ADCCTRL2: CAL_ERR (Bit 10) */ +#define ANA_ADCCTRL2_CAL_ERR_Msk (0x400UL) /*!< ANA ADCCTRL2: CAL_ERR (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_CAL_ERR ANA_ADCCTRL2_CAL_ERR_Msk +#define ANA_ADCCTRL2_CONV_ERR_CLR_Pos (9UL) /*!< ANA ADCCTRL2: CONV_ERR_CLR (Bit 9) */ +#define ANA_ADCCTRL2_CONV_ERR_CLR_Msk (0x200UL) /*!< ANA ADCCTRL2: CONV_ERR_CLR (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_CONV_ERR_CLR ANA_ADCCTRL2_CONV_ERR_CLR_Msk +#define ANA_ADCCTRL2_CAL_ERR_CLR_Pos (8UL) /*!< ANA ADCCTRL2: CAL_ERR_CLR (Bit 8) */ +#define ANA_ADCCTRL2_CAL_ERR_CLR_Msk (0x100UL) /*!< ANA ADCCTRL2: CAL_ERR_CLR (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_CAL_ERR_CLR ANA_ADCCTRL2_CAL_ERR_CLR_Msk +#define ANA_ADCCTRL2_ADC_CAL_DONE_Pos (7UL) /*!< ANA ADCCTRL2: ADC_CAL_DONE (Bit 7) */ +#define ANA_ADCCTRL2_ADC_CAL_DONE_Msk (0x80UL) /*!< ANA ADCCTRL2: ADC_CAL_DONE (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_ADC_CAL_DONE ANA_ADCCTRL2_ADC_CAL_DONE_Msk +#define ANA_ADCCTRL2_ADC_EN_TRG_CAL_Pos (6UL) /*!< ANA ADCCTRL2: ADC_EN_TRG_CAL (Bit 6) */ +#define ANA_ADCCTRL2_ADC_EN_TRG_CAL_Msk (0x40UL) /*!< ANA ADCCTRL2: ADC_EN_TRG_CAL (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_ADC_EN_TRG_CAL ANA_ADCCTRL2_ADC_EN_TRG_CAL_Msk +#define ANA_ADCCTRL2_BUSY_Pos (5UL) /*!< ANA ADCCTRL2: BUSY (Bit 5) */ +#define ANA_ADCCTRL2_BUSY_Msk (0x20UL) /*!< ANA ADCCTRL2: BUSY (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_BUSY ANA_ADCCTRL2_BUSY_Msk +#define ANA_ADCCTRL2_ADCCR_Pos (3UL) /*!< ANA ADCCTRL2: ADCCR (Bit 3) */ +#define ANA_ADCCTRL2_ADCCR_Msk (0x8UL) /*!< ANA ADCCTRL2: ADCCR (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_ADCCR ANA_ADCCTRL2_ADCCR_Msk +#define ANA_ADCCTRL2_RESET_Pos (1UL) /*!< ANA ADCCTRL2: RESET (Bit 1) */ +#define ANA_ADCCTRL2_RESET_Msk (0x2UL) /*!< ANA ADCCTRL2: RESET (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_RESET ANA_ADCCTRL2_RESET_Msk +#define ANA_ADCCTRL2_ADC_EN_Pos (0UL) /*!< ANA ADCCTRL2: ADC_EN (Bit 0) */ +#define ANA_ADCCTRL2_ADC_EN_Msk (0x1UL) /*!< ANA ADCCTRL2: ADC_EN (Bitfield-Mask: 0x01) */ +#define ANA_ADCCTRL2_ADC_EN ANA_ADCCTRL2_ADC_EN_Msk +/* ===================================================== ADCDATATHD1_0 ===================================================== */ +#define ANA_ADCDATATHD1_0_UPPER_THD1_Pos (24UL) /*!< ANA ADCDATATHD1_0: UPPER_THD1 (Bit 24) */ +#define ANA_ADCDATATHD1_0_UPPER_THD1_Msk (0xff000000UL) /*!< ANA ADCDATATHD1_0: UPPER_THD1 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD1_0_UPPER_THD1 ANA_ADCDATATHD1_0_UPPER_THD1_Msk +#define ANA_ADCDATATHD1_0_LOWER_THD1_Pos (16UL) /*!< ANA ADCDATATHD1_0: LOWER_THD1 (Bit 16) */ +#define ANA_ADCDATATHD1_0_LOWER_THD1_Msk (0xff0000UL) /*!< ANA ADCDATATHD1_0: LOWER_THD1 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD1_0_LOWER_THD1 ANA_ADCDATATHD1_0_LOWER_THD1_Msk +#define ANA_ADCDATATHD1_0_UPPER_THD0_Pos (8UL) /*!< ANA ADCDATATHD1_0: UPPER_THD0 (Bit 8) */ +#define ANA_ADCDATATHD1_0_UPPER_THD0_Msk (0xff00UL) /*!< ANA ADCDATATHD1_0: UPPER_THD0 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD1_0_UPPER_THD0 ANA_ADCDATATHD1_0_UPPER_THD0_Msk +#define ANA_ADCDATATHD1_0_LOWER_THD0_Pos (0UL) /*!< ANA ADCDATATHD1_0: LOWER_THD0 (Bit 0) */ +#define ANA_ADCDATATHD1_0_LOWER_THD0_Msk (0xffUL) /*!< ANA ADCDATATHD1_0: LOWER_THD0 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD1_0_LOWER_THD0 ANA_ADCDATATHD1_0_LOWER_THD0_Msk +/* ===================================================== ADCDATATHD3_2 ===================================================== */ +#define ANA_ADCDATATHD3_2_UPPER_THD3_Pos (24UL) /*!< ANA ADCDATATHD3_2: UPPER_THD3 (Bit 24) */ +#define ANA_ADCDATATHD3_2_UPPER_THD3_Msk (0xff000000UL) /*!< ANA ADCDATATHD3_2: UPPER_THD3 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD3_2_UPPER_THD3 ANA_ADCDATATHD3_2_UPPER_THD3_Msk +#define ANA_ADCDATATHD3_2_LOWER_THD3_Pos (16UL) /*!< ANA ADCDATATHD3_2: LOWER_THD3 (Bit 16) */ +#define ANA_ADCDATATHD3_2_LOWER_THD3_Msk (0xff0000UL) /*!< ANA ADCDATATHD3_2: LOWER_THD3 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD3_2_LOWER_THD3 ANA_ADCDATATHD3_2_LOWER_THD3_Msk +#define ANA_ADCDATATHD3_2_UPPER_THD2_Pos (8UL) /*!< ANA ADCDATATHD3_2: UPPER_THD2 (Bit 8) */ +#define ANA_ADCDATATHD3_2_UPPER_THD2_Msk (0xff00UL) /*!< ANA ADCDATATHD3_2: UPPER_THD2 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD3_2_UPPER_THD2 ANA_ADCDATATHD3_2_UPPER_THD2_Msk +#define ANA_ADCDATATHD3_2_LOWER_THD2_Pos (0UL) /*!< ANA ADCDATATHD3_2: LOWER_THD2 (Bit 0) */ +#define ANA_ADCDATATHD3_2_LOWER_THD2_Msk (0xffUL) /*!< ANA ADCDATATHD3_2: LOWER_THD2 (Bitfield-Mask: 0xff) */ +#define ANA_ADCDATATHD3_2_LOWER_THD2 ANA_ADCDATATHD3_2_LOWER_THD2_Msk +/* ===================================================== ADCDATATHD_CH ===================================================== */ +#define ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Pos (31UL) /*!< ANA ADCDATATHD_CH: UPPER_THD3_TRGED (Bit 31) */ +#define ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Msk (0x80000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD3_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_UPPER_THD3_TRGED ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Msk +#define ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Pos (30UL) /*!< ANA ADCDATATHD_CH: LOWER_THD3_TRGED (Bit 30) */ +#define ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Msk (0x40000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD3_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_LOWER_THD3_TRGED ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Msk +#define ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Pos (29UL) /*!< ANA ADCDATATHD_CH: UPPER_THD2_TRGED (Bit 29) */ +#define ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Msk (0x20000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD2_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_UPPER_THD2_TRGED ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Msk +#define ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Pos (28UL) /*!< ANA ADCDATATHD_CH: LOWER_THD2_TRGED (Bit 28) */ +#define ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Msk (0x10000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD2_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_LOWER_THD2_TRGED ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Msk +#define ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Pos (27UL) /*!< ANA ADCDATATHD_CH: UPPER_THD1_TRGED (Bit 27) */ +#define ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Msk (0x8000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD1_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_UPPER_THD1_TRGED ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Msk +#define ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Pos (26UL) /*!< ANA ADCDATATHD_CH: LOWER_THD1_TRGED (Bit 26) */ +#define ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Msk (0x4000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD1_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_LOWER_THD1_TRGED ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Msk +#define ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Pos (25UL) /*!< ANA ADCDATATHD_CH: UPPER_THD0_TRGED (Bit 25) */ +#define ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Msk (0x2000000UL) /*!< ANA ADCDATATHD_CH: UPPER_THD0_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_UPPER_THD0_TRGED ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Msk +#define ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Pos (24UL) /*!< ANA ADCDATATHD_CH: LOWER_THD0_TRGED (Bit 24) */ +#define ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Msk (0x1000000UL) /*!< ANA ADCDATATHD_CH: LOWER_THD0_TRGED (Bitfield-Mask: 0x01) */ +#define ANA_ADCDATATHD_CH_LOWER_THD0_TRGED ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Msk +#define ANA_ADCDATATHD_CH_THD3_SEL_Pos (22UL) /*!< ANA ADCDATATHD_CH: THD3_SEL (Bit 22) */ +#define ANA_ADCDATATHD_CH_THD3_SEL_Msk (0xc00000UL) /*!< ANA ADCDATATHD_CH: THD3_SEL (Bitfield-Mask: 0x03) */ +#define ANA_ADCDATATHD_CH_THD3_SEL ANA_ADCDATATHD_CH_THD3_SEL_Msk +#define ANA_ADCDATATHD_CH_THD2_SEL_Pos (20UL) /*!< ANA ADCDATATHD_CH: THD2_SEL (Bit 20) */ +#define ANA_ADCDATATHD_CH_THD2_SEL_Msk (0x300000UL) /*!< ANA ADCDATATHD_CH: THD2_SEL (Bitfield-Mask: 0x03) */ +#define ANA_ADCDATATHD_CH_THD2_SEL ANA_ADCDATATHD_CH_THD2_SEL_Msk +#define ANA_ADCDATATHD_CH_THD1_SEL_Pos (18UL) /*!< ANA ADCDATATHD_CH: THD1_SEL (Bit 18) */ +#define ANA_ADCDATATHD_CH_THD1_SEL_Msk (0xc0000UL) /*!< ANA ADCDATATHD_CH: THD1_SEL (Bitfield-Mask: 0x03) */ +#define ANA_ADCDATATHD_CH_THD1_SEL ANA_ADCDATATHD_CH_THD1_SEL_Msk +#define ANA_ADCDATATHD_CH_THD0_SEL_Pos (16UL) /*!< ANA ADCDATATHD_CH: THD0_SEL (Bit 16) */ +#define ANA_ADCDATATHD_CH_THD0_SEL_Msk (0x30000UL) /*!< ANA ADCDATATHD_CH: THD0_SEL (Bitfield-Mask: 0x03) */ +#define ANA_ADCDATATHD_CH_THD0_SEL ANA_ADCDATATHD_CH_THD0_SEL_Msk +#define ANA_ADCDATATHD_CH_THD3_CH_Pos (12UL) /*!< ANA ADCDATATHD_CH: THD3_CH (Bit 12) */ +#define ANA_ADCDATATHD_CH_THD3_CH_Msk (0xf000UL) /*!< ANA ADCDATATHD_CH: THD3_CH (Bitfield-Mask: 0x0f) */ +#define ANA_ADCDATATHD_CH_THD3_CH ANA_ADCDATATHD_CH_THD3_CH_Msk +#define ANA_ADCDATATHD_CH_THD2_CH_Pos (8UL) /*!< ANA ADCDATATHD_CH: THD2_CH (Bit 8) */ +#define ANA_ADCDATATHD_CH_THD2_CH_Msk (0xf00UL) /*!< ANA ADCDATATHD_CH: THD2_CH (Bitfield-Mask: 0x0f) */ +#define ANA_ADCDATATHD_CH_THD2_CH ANA_ADCDATATHD_CH_THD2_CH_Msk +#define ANA_ADCDATATHD_CH_THD1_CH_Pos (4UL) /*!< ANA ADCDATATHD_CH: THD1_CH (Bit 4) */ +#define ANA_ADCDATATHD_CH_THD1_CH_Msk (0xf0UL) /*!< ANA ADCDATATHD_CH: THD1_CH (Bitfield-Mask: 0x0f) */ +#define ANA_ADCDATATHD_CH_THD1_CH ANA_ADCDATATHD_CH_THD1_CH_Msk +#define ANA_ADCDATATHD_CH_THD0_CH_Pos (0UL) /*!< ANA ADCDATATHD_CH: THD0_CH (Bit 0) */ +#define ANA_ADCDATATHD_CH_THD0_CH_Msk (0xfUL) /*!< ANA ADCDATATHD_CH: THD0_CH (Bitfield-Mask: 0x0f) */ +#define ANA_ADCDATATHD_CH_THD0_CH ANA_ADCDATATHD_CH_THD0_CH_Msk + + +/* =========================================================================================================================== */ +/* ================ CRYPT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define CRYPT_CTRL_NOSTOP_Pos (15UL) /*!< CRYPT CTRL: NOSTOP (Bit 15) */ +#define CRYPT_CTRL_NOSTOP_Msk (0x8000UL) /*!< CRYPT CTRL: NOSTOP (Bitfield-Mask: 0x01) */ +#define CRYPT_CTRL_NOSTOP CRYPT_CTRL_NOSTOP_Msk +#define CRYPT_CTRL_LENGTH_Pos (8UL) /*!< CRYPT CTRL: LENGTH (Bit 8) */ +#define CRYPT_CTRL_LENGTH_Msk (0xf00UL) /*!< CRYPT CTRL: LENGTH (Bitfield-Mask: 0x0f) */ +#define CRYPT_CTRL_LENGTH CRYPT_CTRL_LENGTH_Msk +#define CRYPT_CTRL_MODE_Pos (4UL) /*!< CRYPT CTRL: MODE (Bit 4) */ +#define CRYPT_CTRL_MODE_Msk (0x70UL) /*!< CRYPT CTRL: MODE (Bitfield-Mask: 0x07) */ +#define CRYPT_CTRL_MODE CRYPT_CTRL_MODE_Msk +#define CRYPT_CTRL_ACT_Pos (0UL) /*!< CRYPT CTRL: ACT (Bit 0) */ +#define CRYPT_CTRL_ACT_Msk (0x1UL) /*!< CRYPT CTRL: ACT (Bitfield-Mask: 0x01) */ +#define CRYPT_CTRL_ACT CRYPT_CTRL_ACT_Msk +/* ========================================================= PTRA ========================================================== */ +#define CRYPT_PTRA_PTRA_Pos (0UL) /*!< CRYPT PTRA: PTRA (Bit 0) */ +#define CRYPT_PTRA_PTRA_Msk (0xffffUL) /*!< CRYPT PTRA: PTRA (Bitfield-Mask: 0xffff) */ +#define CRYPT_PTRA_PTRA CRYPT_PTRA_PTRA_Msk +/* ========================================================= PTRB ========================================================== */ +#define CRYPT_PTRB_PTRB_Pos (0UL) /*!< CRYPT PTRB: PTRB (Bit 0) */ +#define CRYPT_PTRB_PTRB_Msk (0xffffUL) /*!< CRYPT PTRB: PTRB (Bitfield-Mask: 0xffff) */ +#define CRYPT_PTRB_PTRB CRYPT_PTRB_PTRB_Msk +/* ========================================================= PTRO ========================================================== */ +#define CRYPT_PTRO_PTRO_Pos (0UL) /*!< CRYPT PTRO: PTRO (Bit 0) */ +#define CRYPT_PTRO_PTRO_Msk (0xffffUL) /*!< CRYPT PTRO: PTRO (Bitfield-Mask: 0xffff) */ +#define CRYPT_PTRO_PTRO CRYPT_PTRO_PTRO_Msk +/* ========================================================= CARRY ========================================================= */ +#define CRYPT_CARRY_CARRY_Pos (0UL) /*!< CRYPT CARRY: CARRY (Bit 0) */ +#define CRYPT_CARRY_CARRY_Msk (0x1UL) /*!< CRYPT CARRY: CARRY (Bitfield-Mask: 0x01) */ +#define CRYPT_CARRY_CARRY CRYPT_CARRY_CARRY_Msk + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IE =========================================================== */ +#define DMA_IE_C3DAIE_Pos (11UL) /*!< DMA IE: C3DAIE (Bit 11) */ +#define DMA_IE_C3DAIE_Msk (0x800UL) /*!< DMA IE: C3DAIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C3DAIE DMA_IE_C3DAIE_Msk +#define DMA_IE_C2DAIE_Pos (10UL) /*!< DMA IE: C2DAIE (Bit 10) */ +#define DMA_IE_C2DAIE_Msk (0x400UL) /*!< DMA IE: C2DAIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C2DAIE DMA_IE_C2DAIE_Msk +#define DMA_IE_C1DAIE_Pos (9UL) /*!< DMA IE: C1DAIE (Bit 9) */ +#define DMA_IE_C1DAIE_Msk (0x200UL) /*!< DMA IE: C1DAIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C1DAIE DMA_IE_C1DAIE_Msk +#define DMA_IE_C0DAIE_Pos (8UL) /*!< DMA IE: C0DAIE (Bit 8) */ +#define DMA_IE_C0DAIE_Msk (0x100UL) /*!< DMA IE: C0DAIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C0DAIE DMA_IE_C0DAIE_Msk +#define DMA_IE_C3FEIE_Pos (7UL) /*!< DMA IE: C3FEIE (Bit 7) */ +#define DMA_IE_C3FEIE_Msk (0x80UL) /*!< DMA IE: C3FEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C3FEIE DMA_IE_C3FEIE_Msk +#define DMA_IE_C2FEIE_Pos (6UL) /*!< DMA IE: C2FEIE (Bit 6) */ +#define DMA_IE_C2FEIE_Msk (0x40UL) /*!< DMA IE: C2FEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C2FEIE DMA_IE_C2FEIE_Msk +#define DMA_IE_C1FEIE_Pos (5UL) /*!< DMA IE: C1FEIE (Bit 5) */ +#define DMA_IE_C1FEIE_Msk (0x20UL) /*!< DMA IE: C1FEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C1FEIE DMA_IE_C1FEIE_Msk +#define DMA_IE_C0FEIE_Pos (4UL) /*!< DMA IE: C0FEIE (Bit 4) */ +#define DMA_IE_C0FEIE_Msk (0x10UL) /*!< DMA IE: C0FEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C0FEIE DMA_IE_C0FEIE_Msk +#define DMA_IE_C3PEIE_Pos (3UL) /*!< DMA IE: C3PEIE (Bit 3) */ +#define DMA_IE_C3PEIE_Msk (0x8UL) /*!< DMA IE: C3PEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C3PEIE DMA_IE_C3PEIE_Msk +#define DMA_IE_C2PEIE_Pos (2UL) /*!< DMA IE: C2PEIE (Bit 2) */ +#define DMA_IE_C2PEIE_Msk (0x4UL) /*!< DMA IE: C2PEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C2PEIE DMA_IE_C2PEIE_Msk +#define DMA_IE_C1PEIE_Pos (1UL) /*!< DMA IE: C1PEIE (Bit 1) */ +#define DMA_IE_C1PEIE_Msk (0x2UL) /*!< DMA IE: C1PEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C1PEIE DMA_IE_C1PEIE_Msk +#define DMA_IE_C0PEIE_Pos (0UL) /*!< DMA IE: C0PEIE (Bit 0) */ +#define DMA_IE_C0PEIE_Msk (0x1UL) /*!< DMA IE: C0PEIE (Bitfield-Mask: 0x01) */ +#define DMA_IE_C0PEIE DMA_IE_C0PEIE_Msk +/* ========================================================== STS ========================================================== */ +#define DMA_STS_C3DA_Pos (15UL) /*!< DMA STS: C3DA (Bit 15) */ +#define DMA_STS_C3DA_Msk (0x8000UL) /*!< DMA STS: C3DA (Bitfield-Mask: 0x01) */ +#define DMA_STS_C3DA DMA_STS_C3DA_Msk +#define DMA_STS_C2DA_Pos (14UL) /*!< DMA STS: C2DA (Bit 14) */ +#define DMA_STS_C2DA_Msk (0x4000UL) /*!< DMA STS: C2DA (Bitfield-Mask: 0x01) */ +#define DMA_STS_C2DA DMA_STS_C2DA_Msk +#define DMA_STS_C1DA_Pos (13UL) /*!< DMA STS: C1DA (Bit 13) */ +#define DMA_STS_C1DA_Msk (0x2000UL) /*!< DMA STS: C1DA (Bitfield-Mask: 0x01) */ +#define DMA_STS_C1DA DMA_STS_C1DA_Msk +#define DMA_STS_C0DA_Pos (12UL) /*!< DMA STS: C0DA (Bit 12) */ +#define DMA_STS_C0DA_Msk (0x1000UL) /*!< DMA STS: C0DA (Bitfield-Mask: 0x01) */ +#define DMA_STS_C0DA DMA_STS_C0DA_Msk +#define DMA_STS_C3FE_Pos (11UL) /*!< DMA STS: C3FE (Bit 11) */ +#define DMA_STS_C3FE_Msk (0x800UL) /*!< DMA STS: C3FE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C3FE DMA_STS_C3FE_Msk +#define DMA_STS_C2FE_Pos (10UL) /*!< DMA STS: C2FE (Bit 10) */ +#define DMA_STS_C2FE_Msk (0x400UL) /*!< DMA STS: C2FE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C2FE DMA_STS_C2FE_Msk +#define DMA_STS_C1FE_Pos (9UL) /*!< DMA STS: C1FE (Bit 9) */ +#define DMA_STS_C1FE_Msk (0x200UL) /*!< DMA STS: C1FE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C1FE DMA_STS_C1FE_Msk +#define DMA_STS_C0FE_Pos (8UL) /*!< DMA STS: C0FE (Bit 8) */ +#define DMA_STS_C0FE_Msk (0x100UL) /*!< DMA STS: C0FE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C0FE DMA_STS_C0FE_Msk +#define DMA_STS_C3PE_Pos (7UL) /*!< DMA STS: C3PE (Bit 7) */ +#define DMA_STS_C3PE_Msk (0x80UL) /*!< DMA STS: C3PE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C3PE DMA_STS_C3PE_Msk +#define DMA_STS_C2PE_Pos (6UL) /*!< DMA STS: C2PE (Bit 6) */ +#define DMA_STS_C2PE_Msk (0x40UL) /*!< DMA STS: C2PE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C2PE DMA_STS_C2PE_Msk +#define DMA_STS_C1PE_Pos (5UL) /*!< DMA STS: C1PE (Bit 5) */ +#define DMA_STS_C1PE_Msk (0x20UL) /*!< DMA STS: C1PE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C1PE DMA_STS_C1PE_Msk +#define DMA_STS_C0PE_Pos (4UL) /*!< DMA STS: C0PE (Bit 4) */ +#define DMA_STS_C0PE_Msk (0x10UL) /*!< DMA STS: C0PE (Bitfield-Mask: 0x01) */ +#define DMA_STS_C0PE DMA_STS_C0PE_Msk +#define DMA_STS_C3BUSY_Pos (3UL) /*!< DMA STS: C3BUSY (Bit 3) */ +#define DMA_STS_C3BUSY_Msk (0x8UL) /*!< DMA STS: C3BUSY (Bitfield-Mask: 0x01) */ +#define DMA_STS_C3BUSY DMA_STS_C3BUSY_Msk +#define DMA_STS_C2BUSY_Pos (2UL) /*!< DMA STS: C2BUSY (Bit 2) */ +#define DMA_STS_C2BUSY_Msk (0x4UL) /*!< DMA STS: C2BUSY (Bitfield-Mask: 0x01) */ +#define DMA_STS_C2BUSY DMA_STS_C2BUSY_Msk +#define DMA_STS_C1BUSY_Pos (1UL) /*!< DMA STS: C1BUSY (Bit 1) */ +#define DMA_STS_C1BUSY_Msk (0x2UL) /*!< DMA STS: C1BUSY (Bitfield-Mask: 0x01) */ +#define DMA_STS_C1BUSY DMA_STS_C1BUSY_Msk +#define DMA_STS_C0BUSY_Pos (0UL) /*!< DMA STS: C0BUSY (Bit 0) */ +#define DMA_STS_C0BUSY_Msk (0x1UL) /*!< DMA STS: C0BUSY (Bitfield-Mask: 0x01) */ +#define DMA_STS_C0BUSY DMA_STS_C0BUSY_Msk +/* ========================================================= CCTL ========================================================== */ +#define DMA_CCTL_FLEN_Pos (24UL) /*!< DMA CCTL: FLEN (Bit 24) */ +#define DMA_CCTL_FLEN_Msk (0xff000000UL) /*!< DMA CCTL: FLEN (Bitfield-Mask: 0xff) */ +#define DMA_CCTL_FLEN DMA_CCTL_FLEN_Msk +#define DMA_CCTL_PLEN_Pos (16UL) /*!< DMA CCTL: PLEN (Bit 16) */ +#define DMA_CCTL_PLEN_Msk (0xff0000UL) /*!< DMA CCTL: PLEN (Bitfield-Mask: 0xff) */ +#define DMA_CCTL_PLEN DMA_CCTL_PLEN_Msk +#define DMA_CCTL_STOP_Pos (15UL) /*!< DMA CCTL: STOP (Bit 15) */ +#define DMA_CCTL_STOP_Msk (0x8000UL) /*!< DMA CCTL: STOP (Bitfield-Mask: 0x01) */ +#define DMA_CCTL_STOP DMA_CCTL_STOP_Msk +#define DMA_CCTL_AESEN_Pos (14UL) /*!< DMA CCTL: AESEN (Bit 14) */ +#define DMA_CCTL_AESEN_Msk (0x4000UL) /*!< DMA CCTL: AESEN (Bitfield-Mask: 0x01) */ +#define DMA_CCTL_AESEN DMA_CCTL_AESEN_Msk +#define DMA_CCTL_CONT_Pos (13UL) /*!< DMA CCTL: CONT (Bit 13) */ +#define DMA_CCTL_CONT_Msk (0x2000UL) /*!< DMA CCTL: CONT (Bitfield-Mask: 0x01) */ +#define DMA_CCTL_CONT DMA_CCTL_CONT_Msk +#define DMA_CCTL_TMODE_Pos (12UL) /*!< DMA CCTL: TMODE (Bit 12) */ +#define DMA_CCTL_TMODE_Msk (0x1000UL) /*!< DMA CCTL: TMODE (Bitfield-Mask: 0x01) */ +#define DMA_CCTL_TMODE DMA_CCTL_TMODE_Msk +#define DMA_CCTL_DMASEL_Pos (7UL) /*!< DMA CCTL: DMASEL (Bit 7) */ +#define DMA_CCTL_DMASEL_Msk (0xf80UL) /*!< DMA CCTL: DMASEL (Bitfield-Mask: 0x1f) */ +#define DMA_CCTL_DMASEL DMA_CCTL_DMASEL_Msk +#define DMA_CCTL_DMODE_Pos (5UL) /*!< DMA CCTL: DMODE (Bit 5) */ +#define DMA_CCTL_DMODE_Msk (0x60UL) /*!< DMA CCTL: DMODE (Bitfield-Mask: 0x03) */ +#define DMA_CCTL_DMODE DMA_CCTL_DMODE_Msk +#define DMA_CCTL_SMODE_Pos (3UL) /*!< DMA CCTL: SMODE (Bit 3) */ +#define DMA_CCTL_SMODE_Msk (0x18UL) /*!< DMA CCTL: SMODE (Bitfield-Mask: 0x03) */ +#define DMA_CCTL_SMODE DMA_CCTL_SMODE_Msk +#define DMA_CCTL_SIZE_Pos (1UL) /*!< DMA CCTL: SIZE (Bit 1) */ +#define DMA_CCTL_SIZE_Msk (0x6UL) /*!< DMA CCTL: SIZE (Bitfield-Mask: 0x03) */ +#define DMA_CCTL_SIZE DMA_CCTL_SIZE_Msk +#define DMA_CCTL_EN_Pos (0UL) /*!< DMA CCTL: EN (Bit 0) */ +#define DMA_CCTL_EN_Msk (0x1UL) /*!< DMA CCTL: EN (Bitfield-Mask: 0x01) */ +#define DMA_CCTL_EN DMA_CCTL_EN_Msk +/* ========================================================= CSRC ========================================================== */ +#define DMA_CSRC_SRC_Pos (0UL) /*!< DMA CSRC: SRC (Bit 0) */ +#define DMA_CSRC_SRC_Msk (0xffffffffUL) /*!< DMA CSRC: SRC (Bitfield-Mask: 0xffffffff) */ +#define DMA_CSRC_SRC DMA_CSRC_SRC_Msk +/* ========================================================= CDST ========================================================== */ +#define DMA_CDST_DST_Pos (0UL) /*!< DMA CDST: DST (Bit 0) */ +#define DMA_CDST_DST_Msk (0xffffffffUL) /*!< DMA CDST: DST (Bitfield-Mask: 0xffffffff) */ +#define DMA_CDST_DST DMA_CDST_DST_Msk +/* ========================================================= CLEN ========================================================== */ +#define DMA_CLEN_CFLEN_Pos (8UL) /*!< DMA CLEN: CFLEN (Bit 8) */ +#define DMA_CLEN_CFLEN_Msk (0xff00UL) /*!< DMA CLEN: CFLEN (Bitfield-Mask: 0xff) */ +#define DMA_CLEN_CFLEN DMA_CLEN_CFLEN_Msk +#define DMA_CLEN_CPLEN_Pos (0UL) /*!< DMA CLEN: CPLEN (Bit 0) */ +#define DMA_CLEN_CPLEN_Msk (0xffUL) /*!< DMA CLEN: CPLEN (Bitfield-Mask: 0xff) */ +#define DMA_CLEN_CPLEN DMA_CLEN_CPLEN_Msk +/* ======================================================== AESCTL ========================================================= */ +#define DMA_AESCTL_MODE_Pos (2UL) /*!< DMA AESCTL: MODE (Bit 2) */ +#define DMA_AESCTL_MODE_Msk (0xcUL) /*!< DMA AESCTL: MODE (Bitfield-Mask: 0x03) */ +#define DMA_AESCTL_MODE DMA_AESCTL_MODE_Msk +#define DMA_AESCTL_ENC_Pos (0UL) /*!< DMA AESCTL: ENC (Bit 0) */ +#define DMA_AESCTL_ENC_Msk (0x1UL) /*!< DMA AESCTL: ENC (Bitfield-Mask: 0x01) */ +#define DMA_AESCTL_ENC DMA_AESCTL_ENC_Msk +/* ======================================================== AESKEY ========================================================= */ +#define DMA_AESKEY_KEY_Pos (0UL) /*!< DMA AESKEY: KEY (Bit 0) */ +#define DMA_AESKEY_KEY_Msk (0xffffffffUL) /*!< DMA AESKEY: KEY (Bitfield-Mask: 0xffffffff) */ +#define DMA_AESKEY_KEY DMA_AESKEY_KEY_Msk + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ICEPROT ======================================================== */ +#define FLASH_ICEPROT_ICEPROT_Pos (0UL) /*!< FLASH ICEPROT: ICEPROT (Bit 0) */ +#define FLASH_ICEPROT_ICEPROT_Msk (0xffffffffUL) /*!< FLASH ICEPROT: ICEPROT (Bitfield-Mask: 0xffffffff) */ +#define FLASH_ICEPROT_ICEPROT FLASH_ICEPROT_ICEPROT_Msk +/* ======================================================== RDPROT ========================================================= */ +#define FLASH_RDPROT_RDPORT_Pos (0UL) /*!< FLASH RDPROT: RDPORT (Bit 0) */ +#define FLASH_RDPROT_RDPORT_Msk (0xffffffffUL) /*!< FLASH RDPROT: RDPORT (Bitfield-Mask: 0xffffffff) */ +#define FLASH_RDPROT_RDPORT FLASH_RDPROT_RDPORT_Msk +/* ======================================================== WRPROT ========================================================= */ +#define FLASH_WRPROT_WRPORT_Pos (0UL) /*!< FLASH WRPROT: WRPORT (Bit 0) */ +#define FLASH_WRPROT_WRPORT_Msk (0xffffffffUL) /*!< FLASH WRPROT: WRPORT (Bitfield-Mask: 0xffffffff) */ +#define FLASH_WRPROT_WRPORT FLASH_WRPROT_WRPORT_Msk +/* ========================================================== STS ========================================================== */ +#define FLASH_STS_STS_Pos (0UL) /*!< FLASH STS: STS (Bit 0) */ +#define FLASH_STS_STS_Msk (0x1fUL) /*!< FLASH STS: STS (Bitfield-Mask: 0x1f) */ +#define FLASH_STS_STS FLASH_STS_STS_Msk +/* ======================================================== INTSTS ========================================================= */ +#define FLASH_INTSTS_CSERR_Pos (0UL) /*!< FLASH INTSTS: CSERR (Bit 0) */ +#define FLASH_INTSTS_CSERR_Msk (0x1UL) /*!< FLASH INTSTS: CSERR (Bitfield-Mask: 0x01) */ +#define FLASH_INTSTS_CSERR FLASH_INTSTS_CSERR_Msk +/* ======================================================== CSSADDR ======================================================== */ +#define FLASH_CSSADDR_CSSADDR_Pos (0UL) /*!< FLASH CSSADDR: CSSADDR (Bit 0) */ +#define FLASH_CSSADDR_CSSADDR_Msk (0x7ffffUL) /*!< FLASH CSSADDR: CSSADDR (Bitfield-Mask: 0x7ffff) */ +#define FLASH_CSSADDR_CSSADDR FLASH_CSSADDR_CSSADDR_Msk +/* ======================================================== CSEADDR ======================================================== */ +#define FLASH_CSEADDR_CSEADDR_Pos (0UL) /*!< FLASH CSEADDR: CSEADDR (Bit 0) */ +#define FLASH_CSEADDR_CSEADDR_Msk (0x7ffffUL) /*!< FLASH CSEADDR: CSEADDR (Bitfield-Mask: 0x7ffff) */ +#define FLASH_CSEADDR_CSEADDR FLASH_CSEADDR_CSEADDR_Msk +/* ======================================================== CSVALUE ======================================================== */ +#define FLASH_CSVALUE_CSVALUE_Pos (0UL) /*!< FLASH CSVALUE: CSVALUE (Bit 0) */ +#define FLASH_CSVALUE_CSVALUE_Msk (0xffffffffUL) /*!< FLASH CSVALUE: CSVALUE (Bitfield-Mask: 0xffffffff) */ +#define FLASH_CSVALUE_CSVALUE FLASH_CSVALUE_CSVALUE_Msk +/* ======================================================= CSCVALUE ======================================================== */ +#define FLASH_CSCVALUE_CSCVALUE_Pos (0UL) /*!< FLASH CSCVALUE: CSCVALUE (Bit 0) */ +#define FLASH_CSCVALUE_CSCVALUE_Msk (0xffffffffUL) /*!< FLASH CSCVALUE: CSCVALUE (Bitfield-Mask: 0xffffffff) */ +#define FLASH_CSCVALUE_CSCVALUE FLASH_CSCVALUE_CSCVALUE_Msk +/* ========================================================= PASS ========================================================== */ +#define FLASH_PASS_UNLOCK_Pos (0UL) /*!< FLASH PASS: UNLOCK (Bit 0) */ +#define FLASH_PASS_UNLOCK_Msk (0x1UL) /*!< FLASH PASS: UNLOCK (Bitfield-Mask: 0x01) */ +#define FLASH_PASS_UNLOCK FLASH_PASS_UNLOCK_Msk +/* ========================================================= CTRL ========================================================== */ +#define FLASH_CTRL_CSINTEN_Pos (2UL) /*!< FLASH CTRL: CSINTEN (Bit 2) */ +#define FLASH_CTRL_CSINTEN_Msk (0x4UL) /*!< FLASH CTRL: CSINTEN (Bitfield-Mask: 0x01) */ +#define FLASH_CTRL_CSINTEN FLASH_CTRL_CSINTEN_Msk +#define FLASH_CTRL_CSMODE_Pos (0UL) /*!< FLASH CTRL: CSMODE (Bit 0) */ +#define FLASH_CTRL_CSMODE_Msk (0x3UL) /*!< FLASH CTRL: CSMODE (Bitfield-Mask: 0x03) */ +#define FLASH_CTRL_CSMODE FLASH_CTRL_CSMODE_Msk +/* ======================================================== PGADDR ========================================================= */ +#define FLASH_PGADDR_PGADDR_Pos (0UL) /*!< FLASH PGADDR: PGADDR (Bit 0) */ +#define FLASH_PGADDR_PGADDR_Msk (0x3ffffUL) /*!< FLASH PGADDR: PGADDR (Bitfield-Mask: 0x3ffff) */ +#define FLASH_PGADDR_PGADDR FLASH_PGADDR_PGADDR_Msk +/* ======================================================== PGDATA ========================================================= */ +#define FLASH_PGDATA_PGDATA_Pos (0UL) /*!< FLASH PGDATA: PGDATA (Bit 0) */ +#define FLASH_PGDATA_PGDATA_Msk (0xffffffffUL) /*!< FLASH PGDATA: PGDATA (Bitfield-Mask: 0xffffffff) */ +#define FLASH_PGDATA_PGDATA FLASH_PGDATA_PGDATA_Msk +/* ======================================================== SERASE ========================================================= */ +#define FLASH_SERASE_SERASE_Pos (0UL) /*!< FLASH SERASE: SERASE (Bit 0) */ +#define FLASH_SERASE_SERASE_Msk (0x1UL) /*!< FLASH SERASE: SERASE (Bitfield-Mask: 0x01) */ +#define FLASH_SERASE_SERASE FLASH_SERASE_SERASE_Msk +/* ======================================================== CERASE ========================================================= */ +#define FLASH_CERASE_CERASE_Pos (0UL) /*!< FLASH CERASE: CERASE (Bit 0) */ +#define FLASH_CERASE_CERASE_Msk (0x1UL) /*!< FLASH CERASE: CERASE (Bitfield-Mask: 0x01) */ +#define FLASH_CERASE_CERASE FLASH_CERASE_CERASE_Msk +/* ========================================================= DSTB ========================================================== */ +#define FLASH_DSTB_DSTB_Pos (0UL) /*!< FLASH DSTB: DSTB (Bit 0) */ +#define FLASH_DSTB_DSTB_Msk (0x1UL) /*!< FLASH DSTB: DSTB (Bitfield-Mask: 0x01) */ +#define FLASH_DSTB_DSTB FLASH_DSTB_DSTB_Msk + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OEN ========================================================== */ +#define GPIOA_OEN_IOAOEN_Pos (0UL) /*!< GPIOA OEN: IOAOEN (Bit 0) */ +#define GPIOA_OEN_IOAOEN_Msk (0xffffUL) /*!< GPIOA OEN: IOAOEN (Bitfield-Mask: 0xffff) */ +#define GPIOA_OEN_IOAOEN GPIOA_OEN_IOAOEN_Msk +/* ========================================================== IE =========================================================== */ +#define GPIOA_IE_IOAIE_Pos (0UL) /*!< GPIOA IE: IOAIE (Bit 0) */ +#define GPIOA_IE_IOAIE_Msk (0xffffUL) /*!< GPIOA IE: IOAIE (Bitfield-Mask: 0xffff) */ +#define GPIOA_IE_IOAIE GPIOA_IE_IOAIE_Msk +/* ========================================================== DAT ========================================================== */ +#define GPIOA_DAT_IOADAT_Pos (0UL) /*!< GPIOA DAT: IOADAT (Bit 0) */ +#define GPIOA_DAT_IOADAT_Msk (0xffffUL) /*!< GPIOA DAT: IOADAT (Bitfield-Mask: 0xffff) */ +#define GPIOA_DAT_IOADAT GPIOA_DAT_IOADAT_Msk +/* ========================================================== ATT ========================================================== */ +#define GPIOA_ATT_IOAATT_Pos (0UL) /*!< GPIOA ATT: IOAATT (Bit 0) */ +#define GPIOA_ATT_IOAATT_Msk (0xffffUL) /*!< GPIOA ATT: IOAATT (Bitfield-Mask: 0xffff) */ +#define GPIOA_ATT_IOAATT GPIOA_ATT_IOAATT_Msk +/* ======================================================= IOAWKUEN ======================================================== */ +#define GPIOA_IOAWKUEN_WKUEN_Pos (0UL) /*!< GPIOA IOAWKUEN: WKUEN (Bit 0) */ +#define GPIOA_IOAWKUEN_WKUEN_Msk (0xffffffffUL) /*!< GPIOA IOAWKUEN: WKUEN (Bitfield-Mask: 0xffffffff) */ +#define GPIOA_IOAWKUEN_WKUEN GPIOA_IOAWKUEN_WKUEN_Msk +/* ========================================================== STS ========================================================== */ +#define GPIOA_STS_IOASTS_Pos (0UL) /*!< GPIOA STS: IOASTS (Bit 0) */ +#define GPIOA_STS_IOASTS_Msk (0xffffUL) /*!< GPIOA STS: IOASTS (Bitfield-Mask: 0xffff) */ +#define GPIOA_STS_IOASTS GPIOA_STS_IOASTS_Msk +/* ======================================================= IOAINTSTS ======================================================= */ +#define GPIOA_IOAINTSTS_INTSTS_Pos (0UL) /*!< GPIOA IOAINTSTS: INTSTS (Bit 0) */ +#define GPIOA_IOAINTSTS_INTSTS_Msk (0xffffUL) /*!< GPIOA IOAINTSTS: INTSTS (Bitfield-Mask: 0xffff) */ +#define GPIOA_IOAINTSTS_INTSTS GPIOA_IOAINTSTS_INTSTS_Msk +/* ========================================================== SEL ========================================================== */ +#define GPIOA_SEL_SEL7_Pos (7UL) /*!< GPIOA SEL: SEL7 (Bit 7) */ +#define GPIOA_SEL_SEL7_Msk (0x80UL) /*!< GPIOA SEL: SEL7 (Bitfield-Mask: 0x01) */ +#define GPIOA_SEL_SEL7 GPIOA_SEL_SEL7_Msk +#define GPIOA_SEL_SEL6_Pos (6UL) /*!< GPIOA SEL: SEL6 (Bit 6) */ +#define GPIOA_SEL_SEL6_Msk (0x40UL) /*!< GPIOA SEL: SEL6 (Bitfield-Mask: 0x01) */ +#define GPIOA_SEL_SEL6 GPIOA_SEL_SEL6_Msk +#define GPIOA_SEL_SEL3_Pos (3UL) /*!< GPIOA SEL: SEL3 (Bit 3) */ +#define GPIOA_SEL_SEL3_Msk (0x8UL) /*!< GPIOA SEL: SEL3 (Bitfield-Mask: 0x01) */ +#define GPIOA_SEL_SEL3 GPIOA_SEL_SEL3_Msk +/* ======================================================= IOANODEG ======================================================== */ +#define GPIOA_IOANODEG_NODEG_Pos (0UL) /*!< GPIOA IOANODEG: NODEG (Bit 0) */ +#define GPIOA_IOANODEG_NODEG_Msk (0xffffUL) /*!< GPIOA IOANODEG: NODEG (Bitfield-Mask: 0xffff) */ +#define GPIOA_IOANODEG_NODEG GPIOA_IOANODEG_NODEG_Msk + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OEN ========================================================== */ +#define GPIO_OEN_IOXOEN_Pos (0UL) /*!< GPIO OEN: IOXOEN (Bit 0) */ +#define GPIO_OEN_IOXOEN_Msk (0xffffUL) /*!< GPIO OEN: IOXOEN (Bitfield-Mask: 0xffff) */ +#define GPIO_OEN_IOXOEN GPIO_OEN_IOXOEN_Msk +/* ========================================================== IE =========================================================== */ +#define GPIO_IE_IOXIE_Pos (0UL) /*!< GPIO IE: IOXIE (Bit 0) */ +#define GPIO_IE_IOXIE_Msk (0xffffUL) /*!< GPIO IE: IOXIE (Bitfield-Mask: 0xffff) */ +#define GPIO_IE_IOXIE GPIO_IE_IOXIE_Msk +/* ========================================================== DAT ========================================================== */ +#define GPIO_DAT_IOXDAT_Pos (0UL) /*!< GPIO DAT: IOXDAT (Bit 0) */ +#define GPIO_DAT_IOXDAT_Msk (0xffffUL) /*!< GPIO DAT: IOXDAT (Bitfield-Mask: 0xffff) */ +#define GPIO_DAT_IOXDAT GPIO_DAT_IOXDAT_Msk +/* ========================================================== ATT ========================================================== */ +#define GPIO_ATT_IOXATT_Pos (0UL) /*!< GPIO ATT: IOXATT (Bit 0) */ +#define GPIO_ATT_IOXATT_Msk (0xffffUL) /*!< GPIO ATT: IOXATT (Bitfield-Mask: 0xffff) */ +#define GPIO_ATT_IOXATT GPIO_ATT_IOXATT_Msk +/* ========================================================== STS ========================================================== */ +#define GPIO_STS_IOXSTS_Pos (0UL) /*!< GPIO STS: IOXSTS (Bit 0) */ +#define GPIO_STS_IOXSTS_Msk (0xffffUL) /*!< GPIO STS: IOXSTS (Bitfield-Mask: 0xffff) */ +#define GPIO_STS_IOXSTS GPIO_STS_IOXSTS_Msk + + +/* =========================================================================================================================== */ +/* ================ GPIOAF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IOB_SEL ======================================================== */ +#define GPIOAF_IOB_SEL_SEL6_Pos (6UL) /*!< GPIOAF IOB_SEL: SEL6 (Bit 6) */ +#define GPIOAF_IOB_SEL_SEL6_Msk (0x40UL) /*!< GPIOAF IOB_SEL: SEL6 (Bitfield-Mask: 0x01) */ +#define GPIOAF_IOB_SEL_SEL6 GPIOAF_IOB_SEL_SEL6_Msk +#define GPIOAF_IOB_SEL_SEL2_Pos (2UL) /*!< GPIOAF IOB_SEL: SEL2 (Bit 2) */ +#define GPIOAF_IOB_SEL_SEL2_Msk (0x4UL) /*!< GPIOAF IOB_SEL: SEL2 (Bitfield-Mask: 0x01) */ +#define GPIOAF_IOB_SEL_SEL2 GPIOAF_IOB_SEL_SEL2_Msk +#define GPIOAF_IOB_SEL_SEL1_Pos (1UL) /*!< GPIOAF IOB_SEL: SEL1 (Bit 1) */ +#define GPIOAF_IOB_SEL_SEL1_Msk (0x2UL) /*!< GPIOAF IOB_SEL: SEL1 (Bitfield-Mask: 0x01) */ +#define GPIOAF_IOB_SEL_SEL1 GPIOAF_IOB_SEL_SEL1_Msk +/* ======================================================== IOE_SEL ======================================================== */ +#define GPIOAF_IOE_SEL_SEL7_Pos (7UL) /*!< GPIOAF IOE_SEL: SEL7 (Bit 7) */ +#define GPIOAF_IOE_SEL_SEL7_Msk (0x80UL) /*!< GPIOAF IOE_SEL: SEL7 (Bitfield-Mask: 0x01) */ +#define GPIOAF_IOE_SEL_SEL7 GPIOAF_IOE_SEL_SEL7_Msk +/* ======================================================== IO_MISC ======================================================== */ +#define GPIOAF_IO_MISC_I2CIOC_Pos (5UL) /*!< GPIOAF IO_MISC: I2CIOC (Bit 5) */ +#define GPIOAF_IO_MISC_I2CIOC_Msk (0x20UL) /*!< GPIOAF IO_MISC: I2CIOC (Bitfield-Mask: 0x01) */ +#define GPIOAF_IO_MISC_I2CIOC GPIOAF_IO_MISC_I2CIOC_Msk +#define GPIOAF_IO_MISC_PLLHDIV_Pos (0UL) /*!< GPIOAF IO_MISC: PLLHDIV (Bit 0) */ +#define GPIOAF_IO_MISC_PLLHDIV_Msk (0x7UL) /*!< GPIOAF IO_MISC: PLLHDIV (Bitfield-Mask: 0x07) */ +#define GPIOAF_IO_MISC_PLLHDIV GPIOAF_IO_MISC_PLLHDIV_Msk + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define I2C_DATA_DATA_Pos (0UL) /*!< I2C DATA: DATA (Bit 0) */ +#define I2C_DATA_DATA_Msk (0xffUL) /*!< I2C DATA: DATA (Bitfield-Mask: 0xff) */ +#define I2C_DATA_DATA I2C_DATA_DATA_Msk +/* ========================================================= ADDR ========================================================== */ +#define I2C_ADDR_SLA_Pos (1UL) /*!< I2C ADDR: SLA (Bit 1) */ +#define I2C_ADDR_SLA_Msk (0xfeUL) /*!< I2C ADDR: SLA (Bitfield-Mask: 0x7f) */ +#define I2C_ADDR_SLA I2C_ADDR_SLA_Msk +#define I2C_ADDR_GC_Pos (0UL) /*!< I2C ADDR: GC (Bit 0) */ +#define I2C_ADDR_GC_Msk (0x1UL) /*!< I2C ADDR: GC (Bitfield-Mask: 0x01) */ +#define I2C_ADDR_GC I2C_ADDR_GC_Msk +/* ========================================================= CTRL ========================================================== */ +#define I2C_CTRL_CR2_Pos (7UL) /*!< I2C CTRL: CR2 (Bit 7) */ +#define I2C_CTRL_CR2_Msk (0x80UL) /*!< I2C CTRL: CR2 (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_CR2 I2C_CTRL_CR2_Msk +#define I2C_CTRL_EN_Pos (6UL) /*!< I2C CTRL: EN (Bit 6) */ +#define I2C_CTRL_EN_Msk (0x40UL) /*!< I2C CTRL: EN (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_EN I2C_CTRL_EN_Msk +#define I2C_CTRL_STA_Pos (5UL) /*!< I2C CTRL: STA (Bit 5) */ +#define I2C_CTRL_STA_Msk (0x20UL) /*!< I2C CTRL: STA (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_STA I2C_CTRL_STA_Msk +#define I2C_CTRL_STO_Pos (4UL) /*!< I2C CTRL: STO (Bit 4) */ +#define I2C_CTRL_STO_Msk (0x10UL) /*!< I2C CTRL: STO (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_STO I2C_CTRL_STO_Msk +#define I2C_CTRL_SI_Pos (3UL) /*!< I2C CTRL: SI (Bit 3) */ +#define I2C_CTRL_SI_Msk (0x8UL) /*!< I2C CTRL: SI (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_SI I2C_CTRL_SI_Msk +#define I2C_CTRL_AA_Pos (2UL) /*!< I2C CTRL: AA (Bit 2) */ +#define I2C_CTRL_AA_Msk (0x4UL) /*!< I2C CTRL: AA (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_AA I2C_CTRL_AA_Msk +#define I2C_CTRL_CR1_Pos (1UL) /*!< I2C CTRL: CR1 (Bit 1) */ +#define I2C_CTRL_CR1_Msk (0x2UL) /*!< I2C CTRL: CR1 (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_CR1 I2C_CTRL_CR1_Msk +#define I2C_CTRL_CR0_Pos (0UL) /*!< I2C CTRL: CR0 (Bit 0) */ +#define I2C_CTRL_CR0_Msk (0x1UL) /*!< I2C CTRL: CR0 (Bitfield-Mask: 0x01) */ +#define I2C_CTRL_CR0 I2C_CTRL_CR0_Msk +/* ========================================================== STS ========================================================== */ +#define I2C_STS_STS_Pos (3UL) /*!< I2C STS: STS (Bit 3) */ +#define I2C_STS_STS_Msk (0xf8UL) /*!< I2C STS: STS (Bitfield-Mask: 0x1f) */ +#define I2C_STS_STS I2C_STS_STS_Msk +/* ========================================================= CTRL2 ========================================================= */ +#define I2C_CTRL2_INTEN_Pos (0UL) /*!< I2C CTRL2: INTEN (Bit 0) */ +#define I2C_CTRL2_INTEN_Msk (0x1UL) /*!< I2C CTRL2: INTEN (Bitfield-Mask: 0x01) */ +#define I2C_CTRL2_INTEN I2C_CTRL2_INTEN_Msk + + +/* =========================================================================================================================== */ +/* ================ ISO7816 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= BAUDDIVL ======================================================== */ +#define ISO7816_BAUDDIVL_BAUDDIVL_Pos (0UL) /*!< ISO7816 BAUDDIVL: BAUDDIVL (Bit 0) */ +#define ISO7816_BAUDDIVL_BAUDDIVL_Msk (0xffUL) /*!< ISO7816 BAUDDIVL: BAUDDIVL (Bitfield-Mask: 0xff) */ +#define ISO7816_BAUDDIVL_BAUDDIVL ISO7816_BAUDDIVL_BAUDDIVL_Msk +/* ======================================================= BAUDDIVH ======================================================== */ +#define ISO7816_BAUDDIVH_BAUDDIVH_Pos (0UL) /*!< ISO7816 BAUDDIVH: BAUDDIVH (Bit 0) */ +#define ISO7816_BAUDDIVH_BAUDDIVH_Msk (0xffUL) /*!< ISO7816 BAUDDIVH: BAUDDIVH (Bitfield-Mask: 0xff) */ +#define ISO7816_BAUDDIVH_BAUDDIVH ISO7816_BAUDDIVH_BAUDDIVH_Msk +/* ========================================================= DATA ========================================================== */ +#define ISO7816_DATA_DATA_Pos (0UL) /*!< ISO7816 DATA: DATA (Bit 0) */ +#define ISO7816_DATA_DATA_Msk (0xffUL) /*!< ISO7816 DATA: DATA (Bitfield-Mask: 0xff) */ +#define ISO7816_DATA_DATA ISO7816_DATA_DATA_Msk +/* ========================================================= INFO ========================================================== */ +#define ISO7816_INFO_DMATXDONE_Pos (9UL) /*!< ISO7816 INFO: DMATXDONE (Bit 9) */ +#define ISO7816_INFO_DMATXDONE_Msk (0x200UL) /*!< ISO7816 INFO: DMATXDONE (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_DMATXDONE ISO7816_INFO_DMATXDONE_Msk +#define ISO7816_INFO_TXRTYERRIF_Pos (8UL) /*!< ISO7816 INFO: TXRTYERRIF (Bit 8) */ +#define ISO7816_INFO_TXRTYERRIF_Msk (0x100UL) /*!< ISO7816 INFO: TXRTYERRIF (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_TXRTYERRIF ISO7816_INFO_TXRTYERRIF_Msk +#define ISO7816_INFO_RXOVIF_Pos (7UL) /*!< ISO7816 INFO: RXOVIF (Bit 7) */ +#define ISO7816_INFO_RXOVIF_Msk (0x80UL) /*!< ISO7816 INFO: RXOVIF (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_RXOVIF ISO7816_INFO_RXOVIF_Msk +#define ISO7816_INFO_TXDONEIF_Pos (6UL) /*!< ISO7816 INFO: TXDONEIF (Bit 6) */ +#define ISO7816_INFO_TXDONEIF_Msk (0x40UL) /*!< ISO7816 INFO: TXDONEIF (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_TXDONEIF ISO7816_INFO_TXDONEIF_Msk +#define ISO7816_INFO_RXIF_Pos (5UL) /*!< ISO7816 INFO: RXIF (Bit 5) */ +#define ISO7816_INFO_RXIF_Msk (0x20UL) /*!< ISO7816 INFO: RXIF (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_RXIF ISO7816_INFO_RXIF_Msk +#define ISO7816_INFO_RXERRIF_Pos (2UL) /*!< ISO7816 INFO: RXERRIF (Bit 2) */ +#define ISO7816_INFO_RXERRIF_Msk (0x4UL) /*!< ISO7816 INFO: RXERRIF (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_RXERRIF ISO7816_INFO_RXERRIF_Msk +#define ISO7816_INFO_CHKSUM_Pos (1UL) /*!< ISO7816 INFO: CHKSUM (Bit 1) */ +#define ISO7816_INFO_CHKSUM_Msk (0x2UL) /*!< ISO7816 INFO: CHKSUM (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_CHKSUM ISO7816_INFO_CHKSUM_Msk +#define ISO7816_INFO_RXACK_Pos (0UL) /*!< ISO7816 INFO: RXACK (Bit 0) */ +#define ISO7816_INFO_RXACK_Msk (0x1UL) /*!< ISO7816 INFO: RXACK (Bitfield-Mask: 0x01) */ +#define ISO7816_INFO_RXACK ISO7816_INFO_RXACK_Msk +/* ========================================================== CFG ========================================================== */ +#define ISO7816_CFG_RXACKSET_Pos (16UL) /*!< ISO7816 CFG: RXACKSET (Bit 16) */ +#define ISO7816_CFG_RXACKSET_Msk (0x10000UL) /*!< ISO7816 CFG: RXACKSET (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_RXACKSET ISO7816_CFG_RXACKSET_Msk +#define ISO7816_CFG_TXRTYCNT_Pos (12UL) /*!< ISO7816 CFG: TXRTYCNT (Bit 12) */ +#define ISO7816_CFG_TXRTYCNT_Msk (0xf000UL) /*!< ISO7816 CFG: TXRTYCNT (Bitfield-Mask: 0x0f) */ +#define ISO7816_CFG_TXRTYCNT ISO7816_CFG_TXRTYCNT_Msk +#define ISO7816_CFG_LSB_Pos (11UL) /*!< ISO7816 CFG: LSB (Bit 11) */ +#define ISO7816_CFG_LSB_Msk (0x800UL) /*!< ISO7816 CFG: LSB (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_LSB ISO7816_CFG_LSB_Msk +#define ISO7816_CFG_AUTORXACK_Pos (9UL) /*!< ISO7816 CFG: AUTORXACK (Bit 9) */ +#define ISO7816_CFG_AUTORXACK_Msk (0x200UL) /*!< ISO7816 CFG: AUTORXACK (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_AUTORXACK ISO7816_CFG_AUTORXACK_Msk +#define ISO7816_CFG_TXRTYERRIE_Pos (8UL) /*!< ISO7816 CFG: TXRTYERRIE (Bit 8) */ +#define ISO7816_CFG_TXRTYERRIE_Msk (0x100UL) /*!< ISO7816 CFG: TXRTYERRIE (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_TXRTYERRIE ISO7816_CFG_TXRTYERRIE_Msk +#define ISO7816_CFG_RXOVIE_Pos (7UL) /*!< ISO7816 CFG: RXOVIE (Bit 7) */ +#define ISO7816_CFG_RXOVIE_Msk (0x80UL) /*!< ISO7816 CFG: RXOVIE (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_RXOVIE ISO7816_CFG_RXOVIE_Msk +#define ISO7816_CFG_TXDONEIE_Pos (6UL) /*!< ISO7816 CFG: TXDONEIE (Bit 6) */ +#define ISO7816_CFG_TXDONEIE_Msk (0x40UL) /*!< ISO7816 CFG: TXDONEIE (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_TXDONEIE ISO7816_CFG_TXDONEIE_Msk +#define ISO7816_CFG_RXIE_Pos (5UL) /*!< ISO7816 CFG: RXIE (Bit 5) */ +#define ISO7816_CFG_RXIE_Msk (0x20UL) /*!< ISO7816 CFG: RXIE (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_RXIE ISO7816_CFG_RXIE_Msk +#define ISO7816_CFG_ACKLEN_Pos (4UL) /*!< ISO7816 CFG: ACKLEN (Bit 4) */ +#define ISO7816_CFG_ACKLEN_Msk (0x10UL) /*!< ISO7816 CFG: ACKLEN (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_ACKLEN ISO7816_CFG_ACKLEN_Msk +#define ISO7816_CFG_RXERRIE_Pos (2UL) /*!< ISO7816 CFG: RXERRIE (Bit 2) */ +#define ISO7816_CFG_RXERRIE_Msk (0x4UL) /*!< ISO7816 CFG: RXERRIE (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_RXERRIE ISO7816_CFG_RXERRIE_Msk +#define ISO7816_CFG_CHKP_Pos (1UL) /*!< ISO7816 CFG: CHKP (Bit 1) */ +#define ISO7816_CFG_CHKP_Msk (0x2UL) /*!< ISO7816 CFG: CHKP (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_CHKP ISO7816_CFG_CHKP_Msk +#define ISO7816_CFG_EN_Pos (0UL) /*!< ISO7816 CFG: EN (Bit 0) */ +#define ISO7816_CFG_EN_Msk (0x1UL) /*!< ISO7816 CFG: EN (Bitfield-Mask: 0x01) */ +#define ISO7816_CFG_EN ISO7816_CFG_EN_Msk +/* ========================================================== CLK ========================================================== */ +#define ISO7816_CLK_CLKEN_Pos (7UL) /*!< ISO7816 CLK: CLKEN (Bit 7) */ +#define ISO7816_CLK_CLKEN_Msk (0x80UL) /*!< ISO7816 CLK: CLKEN (Bitfield-Mask: 0x01) */ +#define ISO7816_CLK_CLKEN ISO7816_CLK_CLKEN_Msk +#define ISO7816_CLK_CLKDIV_Pos (0UL) /*!< ISO7816 CLK: CLKDIV (Bit 0) */ +#define ISO7816_CLK_CLKDIV_Msk (0x7fUL) /*!< ISO7816 CLK: CLKDIV (Bitfield-Mask: 0x7f) */ +#define ISO7816_CLK_CLKDIV ISO7816_CLK_CLKDIV_Msk + + +/* =========================================================================================================================== */ +/* ================ LCD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== FB =========================================================== */ +#define LCD_FB_DATA_Pos (0UL) /*!< LCD FB: DATA (Bit 0) */ +#define LCD_FB_DATA_Msk (0xffffffffUL) /*!< LCD FB: DATA (Bitfield-Mask: 0xffffffff) */ +#define LCD_FB_DATA LCD_FB_DATA_Msk +/* ========================================================= CTRL ========================================================== */ +#define LCD_CTRL_EN_Pos (7UL) /*!< LCD CTRL: EN (Bit 7) */ +#define LCD_CTRL_EN_Msk (0x80UL) /*!< LCD CTRL: EN (Bitfield-Mask: 0x01) */ +#define LCD_CTRL_EN LCD_CTRL_EN_Msk +#define LCD_CTRL_TYPE_Pos (4UL) /*!< LCD CTRL: TYPE (Bit 4) */ +#define LCD_CTRL_TYPE_Msk (0x30UL) /*!< LCD CTRL: TYPE (Bitfield-Mask: 0x03) */ +#define LCD_CTRL_TYPE LCD_CTRL_TYPE_Msk +#define LCD_CTRL_DRV_Pos (2UL) /*!< LCD CTRL: DRV (Bit 2) */ +#define LCD_CTRL_DRV_Msk (0xcUL) /*!< LCD CTRL: DRV (Bitfield-Mask: 0x03) */ +#define LCD_CTRL_DRV LCD_CTRL_DRV_Msk +#define LCD_CTRL_FRQ_Pos (0UL) /*!< LCD CTRL: FRQ (Bit 0) */ +#define LCD_CTRL_FRQ_Msk (0x3UL) /*!< LCD CTRL: FRQ (Bitfield-Mask: 0x03) */ +#define LCD_CTRL_FRQ LCD_CTRL_FRQ_Msk +/* ========================================================= CTRL2 ========================================================= */ +#define LCD_CTRL2_SWPR_Pos (8UL) /*!< LCD CTRL2: SWPR (Bit 8) */ +#define LCD_CTRL2_SWPR_Msk (0xff00UL) /*!< LCD CTRL2: SWPR (Bitfield-Mask: 0xff) */ +#define LCD_CTRL2_SWPR LCD_CTRL2_SWPR_Msk +#define LCD_CTRL2_FBMODE_Pos (6UL) /*!< LCD CTRL2: FBMODE (Bit 6) */ +#define LCD_CTRL2_FBMODE_Msk (0xc0UL) /*!< LCD CTRL2: FBMODE (Bitfield-Mask: 0x03) */ +#define LCD_CTRL2_FBMODE LCD_CTRL2_FBMODE_Msk +#define LCD_CTRL2_BKFILL_Pos (4UL) /*!< LCD CTRL2: BKFILL (Bit 4) */ +#define LCD_CTRL2_BKFILL_Msk (0x10UL) /*!< LCD CTRL2: BKFILL (Bitfield-Mask: 0x01) */ +#define LCD_CTRL2_BKFILL LCD_CTRL2_BKFILL_Msk +/* ======================================================= SEGCTRL0 ======================================================== */ +#define LCD_SEGCTRL0_SEGCTRL_Pos (0UL) /*!< LCD SEGCTRL0: SEGCTRL (Bit 0) */ +#define LCD_SEGCTRL0_SEGCTRL_Msk (0xffffffffUL) /*!< LCD SEGCTRL0: SEGCTRL (Bitfield-Mask: 0xffffffff) */ +#define LCD_SEGCTRL0_SEGCTRL LCD_SEGCTRL0_SEGCTRL_Msk +/* ======================================================= SEGCTRL1 ======================================================== */ +#define LCD_SEGCTRL1_SEGCTRL_Pos (0UL) /*!< LCD SEGCTRL1: SEGCTRL (Bit 0) */ +#define LCD_SEGCTRL1_SEGCTRL_Msk (0xffffffffUL) /*!< LCD SEGCTRL1: SEGCTRL (Bitfield-Mask: 0xffffffff) */ +#define LCD_SEGCTRL1_SEGCTRL LCD_SEGCTRL1_SEGCTRL_Msk +/* ======================================================= SEGCTRL2 ======================================================== */ +#define LCD_SEGCTRL2_SEGCTRL_Pos (0UL) /*!< LCD SEGCTRL2: SEGCTRL (Bit 0) */ +#define LCD_SEGCTRL2_SEGCTRL_Msk (0xffffUL) /*!< LCD SEGCTRL2: SEGCTRL (Bitfield-Mask: 0xffff) */ +#define LCD_SEGCTRL2_SEGCTRL LCD_SEGCTRL2_SEGCTRL_Msk + + +/* =========================================================================================================================== */ +/* ================ MISC1 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRAMINT ======================================================== */ +#define MISC1_SRAMINT_LOCKUP_Pos (4UL) /*!< MISC1 SRAMINT: LOCKUP (Bit 4) */ +#define MISC1_SRAMINT_LOCKUP_Msk (0x10UL) /*!< MISC1 SRAMINT: LOCKUP (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINT_LOCKUP MISC1_SRAMINT_LOCKUP_Msk +#define MISC1_SRAMINT_PIAC_Pos (3UL) /*!< MISC1 SRAMINT: PIAC (Bit 3) */ +#define MISC1_SRAMINT_PIAC_Msk (0x8UL) /*!< MISC1 SRAMINT: PIAC (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINT_PIAC MISC1_SRAMINT_PIAC_Msk +#define MISC1_SRAMINT_HIAC_Pos (2UL) /*!< MISC1 SRAMINT: HIAC (Bit 2) */ +#define MISC1_SRAMINT_HIAC_Msk (0x4UL) /*!< MISC1 SRAMINT: HIAC (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINT_HIAC MISC1_SRAMINT_HIAC_Msk +#define MISC1_SRAMINT_HIAL_Pos (1UL) /*!< MISC1 SRAMINT: HIAL (Bit 1) */ +#define MISC1_SRAMINT_HIAL_Msk (0x2UL) /*!< MISC1 SRAMINT: HIAL (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINT_HIAL MISC1_SRAMINT_HIAL_Msk +#define MISC1_SRAMINT_PERR_Pos (0UL) /*!< MISC1 SRAMINT: PERR (Bit 0) */ +#define MISC1_SRAMINT_PERR_Msk (0x1UL) /*!< MISC1 SRAMINT: PERR (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINT_PERR MISC1_SRAMINT_PERR_Msk +/* ======================================================= SRAMINIT ======================================================== */ +#define MISC1_SRAMINIT_LOCKIE_Pos (7UL) /*!< MISC1 SRAMINIT: LOCKIE (Bit 7) */ +#define MISC1_SRAMINIT_LOCKIE_Msk (0x80UL) /*!< MISC1 SRAMINIT: LOCKIE (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINIT_LOCKIE MISC1_SRAMINIT_LOCKIE_Msk +#define MISC1_SRAMINIT_PIACIE_Pos (6UL) /*!< MISC1 SRAMINIT: PIACIE (Bit 6) */ +#define MISC1_SRAMINIT_PIACIE_Msk (0x40UL) /*!< MISC1 SRAMINIT: PIACIE (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINIT_PIACIE MISC1_SRAMINIT_PIACIE_Msk +#define MISC1_SRAMINIT_HIACIE_Pos (5UL) /*!< MISC1 SRAMINIT: HIACIE (Bit 5) */ +#define MISC1_SRAMINIT_HIACIE_Msk (0x20UL) /*!< MISC1 SRAMINIT: HIACIE (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINIT_HIACIE MISC1_SRAMINIT_HIACIE_Msk +#define MISC1_SRAMINIT_INIT_Pos (2UL) /*!< MISC1 SRAMINIT: INIT (Bit 2) */ +#define MISC1_SRAMINIT_INIT_Msk (0x4UL) /*!< MISC1 SRAMINIT: INIT (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINIT_INIT MISC1_SRAMINIT_INIT_Msk +#define MISC1_SRAMINIT_PERRIE_Pos (1UL) /*!< MISC1 SRAMINIT: PERRIE (Bit 1) */ +#define MISC1_SRAMINIT_PERRIE_Msk (0x2UL) /*!< MISC1 SRAMINIT: PERRIE (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINIT_PERRIE MISC1_SRAMINIT_PERRIE_Msk +#define MISC1_SRAMINIT_PEN_Pos (0UL) /*!< MISC1 SRAMINIT: PEN (Bit 0) */ +#define MISC1_SRAMINIT_PEN_Msk (0x1UL) /*!< MISC1 SRAMINIT: PEN (Bitfield-Mask: 0x01) */ +#define MISC1_SRAMINIT_PEN MISC1_SRAMINIT_PEN_Msk +/* ======================================================== PARERR ========================================================= */ +#define MISC1_PARERR_PEADDR_Pos (0UL) /*!< MISC1 PARERR: PEADDR (Bit 0) */ +#define MISC1_PARERR_PEADDR_Msk (0x3fffUL) /*!< MISC1 PARERR: PEADDR (Bitfield-Mask: 0x3fff) */ +#define MISC1_PARERR_PEADDR MISC1_PARERR_PEADDR_Msk +/* ========================================================= IREN ========================================================== */ +#define MISC1_IREN_IREN_Pos (0UL) /*!< MISC1 IREN: IREN (Bit 0) */ +#define MISC1_IREN_IREN_Msk (0x3fUL) /*!< MISC1 IREN: IREN (Bitfield-Mask: 0x3f) */ +#define MISC1_IREN_IREN MISC1_IREN_IREN_Msk +/* ========================================================= DUTYL ========================================================= */ +#define MISC1_DUTYL_DUTYL_Pos (0UL) /*!< MISC1 DUTYL: DUTYL (Bit 0) */ +#define MISC1_DUTYL_DUTYL_Msk (0xffffUL) /*!< MISC1 DUTYL: DUTYL (Bitfield-Mask: 0xffff) */ +#define MISC1_DUTYL_DUTYL MISC1_DUTYL_DUTYL_Msk +/* ========================================================= DUTYH ========================================================= */ +#define MISC1_DUTYH_DUTYH_Pos (0UL) /*!< MISC1 DUTYH: DUTYH (Bit 0) */ +#define MISC1_DUTYH_DUTYH_Msk (0xffffUL) /*!< MISC1 DUTYH: DUTYH (Bitfield-Mask: 0xffff) */ +#define MISC1_DUTYH_DUTYH MISC1_DUTYH_DUTYH_Msk +/* ======================================================== IRQLAT ========================================================= */ +#define MISC1_IRQLAT_NOHARDFAULT_Pos (9UL) /*!< MISC1 IRQLAT: NOHARDFAULT (Bit 9) */ +#define MISC1_IRQLAT_NOHARDFAULT_Msk (0x200UL) /*!< MISC1 IRQLAT: NOHARDFAULT (Bitfield-Mask: 0x01) */ +#define MISC1_IRQLAT_NOHARDFAULT MISC1_IRQLAT_NOHARDFAULT_Msk +#define MISC1_IRQLAT_LOCKRESET_Pos (8UL) /*!< MISC1 IRQLAT: LOCKRESET (Bit 8) */ +#define MISC1_IRQLAT_LOCKRESET_Msk (0x100UL) /*!< MISC1 IRQLAT: LOCKRESET (Bitfield-Mask: 0x01) */ +#define MISC1_IRQLAT_LOCKRESET MISC1_IRQLAT_LOCKRESET_Msk +#define MISC1_IRQLAT_IRQLAT_Pos (0UL) /*!< MISC1 IRQLAT: IRQLAT (Bit 0) */ +#define MISC1_IRQLAT_IRQLAT_Msk (0xffUL) /*!< MISC1 IRQLAT: IRQLAT (Bitfield-Mask: 0xff) */ +#define MISC1_IRQLAT_IRQLAT MISC1_IRQLAT_IRQLAT_Msk +/* ======================================================== HIADDR ========================================================= */ +#define MISC1_HIADDR_HIADDR_Pos (0UL) /*!< MISC1 HIADDR: HIADDR (Bit 0) */ +#define MISC1_HIADDR_HIADDR_Msk (0xffffffffUL) /*!< MISC1 HIADDR: HIADDR (Bitfield-Mask: 0xffffffff) */ +#define MISC1_HIADDR_HIADDR MISC1_HIADDR_HIADDR_Msk +/* ======================================================== PIADDR ========================================================= */ +#define MISC1_PIADDR_PIADDR_Pos (0UL) /*!< MISC1 PIADDR: PIADDR (Bit 0) */ +#define MISC1_PIADDR_PIADDR_Msk (0xffffffffUL) /*!< MISC1 PIADDR: PIADDR (Bitfield-Mask: 0xffffffff) */ +#define MISC1_PIADDR_PIADDR MISC1_PIADDR_PIADDR_Msk + + +/* =========================================================================================================================== */ +/* ================ MISC2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FLASHWC ======================================================== */ +#define MISC2_FLASHWC_CYCLE_1US_Pos (8UL) /*!< MISC2 FLASHWC: CYCLE_1US (Bit 8) */ +#define MISC2_FLASHWC_CYCLE_1US_Msk (0x3f00UL) /*!< MISC2 FLASHWC: CYCLE_1US (Bitfield-Mask: 0x3f) */ +#define MISC2_FLASHWC_CYCLE_1US MISC2_FLASHWC_CYCLE_1US_Msk +/* ======================================================== CLKSEL ========================================================= */ +#define MISC2_CLKSEL_CLKSEL_Pos (0UL) /*!< MISC2 CLKSEL: CLKSEL (Bit 0) */ +#define MISC2_CLKSEL_CLKSEL_Msk (0x7UL) /*!< MISC2 CLKSEL: CLKSEL (Bitfield-Mask: 0x07) */ +#define MISC2_CLKSEL_CLKSEL MISC2_CLKSEL_CLKSEL_Msk +/* ======================================================== CLKDIVH ======================================================== */ +#define MISC2_CLKDIVH_CLKDIVH_Pos (0UL) /*!< MISC2 CLKDIVH: CLKDIVH (Bit 0) */ +#define MISC2_CLKDIVH_CLKDIVH_Msk (0xffUL) /*!< MISC2 CLKDIVH: CLKDIVH (Bitfield-Mask: 0xff) */ +#define MISC2_CLKDIVH_CLKDIVH MISC2_CLKDIVH_CLKDIVH_Msk +/* ======================================================== CLKDIVP ======================================================== */ +#define MISC2_CLKDIVP_CLKDIVP_Pos (0UL) /*!< MISC2 CLKDIVP: CLKDIVP (Bit 0) */ +#define MISC2_CLKDIVP_CLKDIVP_Msk (0xffUL) /*!< MISC2 CLKDIVP: CLKDIVP (Bitfield-Mask: 0xff) */ +#define MISC2_CLKDIVP_CLKDIVP MISC2_CLKDIVP_CLKDIVP_Msk +/* ======================================================== HCLKEN ========================================================= */ +#define MISC2_HCLKEN_CRYPT_Pos (8UL) /*!< MISC2 HCLKEN: CRYPT (Bit 8) */ +#define MISC2_HCLKEN_CRYPT_Msk (0x100UL) /*!< MISC2 HCLKEN: CRYPT (Bitfield-Mask: 0x01) */ +#define MISC2_HCLKEN_CRYPT MISC2_HCLKEN_CRYPT_Msk +#define MISC2_HCLKEN_LCD_Pos (6UL) /*!< MISC2 HCLKEN: LCD (Bit 6) */ +#define MISC2_HCLKEN_LCD_Msk (0x40UL) /*!< MISC2 HCLKEN: LCD (Bitfield-Mask: 0x01) */ +#define MISC2_HCLKEN_LCD MISC2_HCLKEN_LCD_Msk +#define MISC2_HCLKEN_GPIO_Pos (5UL) /*!< MISC2 HCLKEN: GPIO (Bit 5) */ +#define MISC2_HCLKEN_GPIO_Msk (0x20UL) /*!< MISC2 HCLKEN: GPIO (Bitfield-Mask: 0x01) */ +#define MISC2_HCLKEN_GPIO MISC2_HCLKEN_GPIO_Msk +#define MISC2_HCLKEN_DMA_Pos (4UL) /*!< MISC2 HCLKEN: DMA (Bit 4) */ +#define MISC2_HCLKEN_DMA_Msk (0x10UL) /*!< MISC2 HCLKEN: DMA (Bitfield-Mask: 0x01) */ +#define MISC2_HCLKEN_DMA MISC2_HCLKEN_DMA_Msk +/* ======================================================== PCLKEN ========================================================= */ +#define MISC2_PCLKEN_SPI3_Pos (22UL) /*!< MISC2 PCLKEN: SPI3 (Bit 22) */ +#define MISC2_PCLKEN_SPI3_Msk (0x400000UL) /*!< MISC2 PCLKEN: SPI3 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_SPI3 MISC2_PCLKEN_SPI3_Msk +#define MISC2_PCLKEN_SPI2_Pos (21UL) /*!< MISC2 PCLKEN: SPI2 (Bit 21) */ +#define MISC2_PCLKEN_SPI2_Msk (0x200000UL) /*!< MISC2 PCLKEN: SPI2 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_SPI2 MISC2_PCLKEN_SPI2_Msk +#define MISC2_PCLKEN_U32K1_Pos (19UL) /*!< MISC2 PCLKEN: U32K1 (Bit 19) */ +#define MISC2_PCLKEN_U32K1_Msk (0x80000UL) /*!< MISC2 PCLKEN: U32K1 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_U32K1 MISC2_PCLKEN_U32K1_Msk +#define MISC2_PCLKEN_U32K0_Pos (18UL) /*!< MISC2 PCLKEN: U32K0 (Bit 18) */ +#define MISC2_PCLKEN_U32K0_Msk (0x40000UL) /*!< MISC2 PCLKEN: U32K0 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_U32K0 MISC2_PCLKEN_U32K0_Msk +#define MISC2_PCLKEN_ANA_Pos (17UL) /*!< MISC2 PCLKEN: ANA (Bit 17) */ +#define MISC2_PCLKEN_ANA_Msk (0x20000UL) /*!< MISC2 PCLKEN: ANA (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_ANA MISC2_PCLKEN_ANA_Msk +#define MISC2_PCLKEN_RTC_Pos (16UL) /*!< MISC2 PCLKEN: RTC (Bit 16) */ +#define MISC2_PCLKEN_RTC_Msk (0x10000UL) /*!< MISC2 PCLKEN: RTC (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_RTC MISC2_PCLKEN_RTC_Msk +#define MISC2_PCLKEN_PMU_Pos (15UL) /*!< MISC2 PCLKEN: PMU (Bit 15) */ +#define MISC2_PCLKEN_PMU_Msk (0x8000UL) /*!< MISC2 PCLKEN: PMU (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_PMU MISC2_PCLKEN_PMU_Msk +#define MISC2_PCLKEN_MISC2_Pos (14UL) /*!< MISC2 PCLKEN: MISC2 (Bit 14) */ +#define MISC2_PCLKEN_MISC2_Msk (0x4000UL) /*!< MISC2 PCLKEN: MISC2 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_MISC2 MISC2_PCLKEN_MISC2_Msk +#define MISC2_PCLKEN_MISC1_Pos (13UL) /*!< MISC2 PCLKEN: MISC1 (Bit 13) */ +#define MISC2_PCLKEN_MISC1_Msk (0x2000UL) /*!< MISC2 PCLKEN: MISC1 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_MISC1 MISC2_PCLKEN_MISC1_Msk +#define MISC2_PCLKEN_TIMER_Pos (12UL) /*!< MISC2 PCLKEN: TIMER (Bit 12) */ +#define MISC2_PCLKEN_TIMER_Msk (0x1000UL) /*!< MISC2 PCLKEN: TIMER (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_TIMER MISC2_PCLKEN_TIMER_Msk +#define MISC2_PCLKEN_ISO78161_Pos (11UL) /*!< MISC2 PCLKEN: ISO78161 (Bit 11) */ +#define MISC2_PCLKEN_ISO78161_Msk (0x800UL) /*!< MISC2 PCLKEN: ISO78161 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_ISO78161 MISC2_PCLKEN_ISO78161_Msk +#define MISC2_PCLKEN_ISO78160_Pos (10UL) /*!< MISC2 PCLKEN: ISO78160 (Bit 10) */ +#define MISC2_PCLKEN_ISO78160_Msk (0x400UL) /*!< MISC2 PCLKEN: ISO78160 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_ISO78160 MISC2_PCLKEN_ISO78160_Msk +#define MISC2_PCLKEN_UART5_Pos (9UL) /*!< MISC2 PCLKEN: UART5 (Bit 9) */ +#define MISC2_PCLKEN_UART5_Msk (0x200UL) /*!< MISC2 PCLKEN: UART5 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_UART5 MISC2_PCLKEN_UART5_Msk +#define MISC2_PCLKEN_UART4_Pos (8UL) /*!< MISC2 PCLKEN: UART4 (Bit 8) */ +#define MISC2_PCLKEN_UART4_Msk (0x100UL) /*!< MISC2 PCLKEN: UART4 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_UART4 MISC2_PCLKEN_UART4_Msk +#define MISC2_PCLKEN_UART3_Pos (7UL) /*!< MISC2 PCLKEN: UART3 (Bit 7) */ +#define MISC2_PCLKEN_UART3_Msk (0x80UL) /*!< MISC2 PCLKEN: UART3 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_UART3 MISC2_PCLKEN_UART3_Msk +#define MISC2_PCLKEN_UART2_Pos (6UL) /*!< MISC2 PCLKEN: UART2 (Bit 6) */ +#define MISC2_PCLKEN_UART2_Msk (0x40UL) /*!< MISC2 PCLKEN: UART2 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_UART2 MISC2_PCLKEN_UART2_Msk +#define MISC2_PCLKEN_UART1_Pos (5UL) /*!< MISC2 PCLKEN: UART1 (Bit 5) */ +#define MISC2_PCLKEN_UART1_Msk (0x20UL) /*!< MISC2 PCLKEN: UART1 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_UART1 MISC2_PCLKEN_UART1_Msk +#define MISC2_PCLKEN_UART0_Pos (4UL) /*!< MISC2 PCLKEN: UART0 (Bit 4) */ +#define MISC2_PCLKEN_UART0_Msk (0x10UL) /*!< MISC2 PCLKEN: UART0 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_UART0 MISC2_PCLKEN_UART0_Msk +#define MISC2_PCLKEN_SPI1_Pos (3UL) /*!< MISC2 PCLKEN: SPI1 (Bit 3) */ +#define MISC2_PCLKEN_SPI1_Msk (0x8UL) /*!< MISC2 PCLKEN: SPI1 (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_SPI1 MISC2_PCLKEN_SPI1_Msk +#define MISC2_PCLKEN_I2C_Pos (2UL) /*!< MISC2 PCLKEN: I2C (Bit 2) */ +#define MISC2_PCLKEN_I2C_Msk (0x4UL) /*!< MISC2 PCLKEN: I2C (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_I2C MISC2_PCLKEN_I2C_Msk +#define MISC2_PCLKEN_DMA_Pos (1UL) /*!< MISC2 PCLKEN: DMA (Bit 1) */ +#define MISC2_PCLKEN_DMA_Msk (0x2UL) /*!< MISC2 PCLKEN: DMA (Bitfield-Mask: 0x01) */ +#define MISC2_PCLKEN_DMA MISC2_PCLKEN_DMA_Msk + + +/* =========================================================================================================================== */ +/* ================ PMU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DSLEEPEN ======================================================== */ +#define PMU_DSLEEPEN_WKU_Pos (31UL) /*!< PMU DSLEEPEN: WKU (Bit 31) */ +#define PMU_DSLEEPEN_WKU_Msk (0x80000000UL) /*!< PMU DSLEEPEN: WKU (Bitfield-Mask: 0x01) */ +#define PMU_DSLEEPEN_WKU PMU_DSLEEPEN_WKU_Msk +/* ====================================================== DSLEEPPASS ======================================================= */ +#define PMU_DSLEEPPASS_UNLOCK_Pos (0UL) /*!< PMU DSLEEPPASS: UNLOCK (Bit 0) */ +#define PMU_DSLEEPPASS_UNLOCK_Msk (0x1UL) /*!< PMU DSLEEPPASS: UNLOCK (Bitfield-Mask: 0x01) */ +#define PMU_DSLEEPPASS_UNLOCK PMU_DSLEEPPASS_UNLOCK_Msk +/* ======================================================== CONTROL ======================================================== */ +#define PMU_CONTROL_FORCE_CLKSEL_RCH_Pos (20UL) /*!< PMU CONTROL: FORCE_CLKSEL_RCH (Bit 20) */ +#define PMU_CONTROL_FORCE_CLKSEL_RCH_Msk (0x100000UL) /*!< PMU CONTROL: FORCE_CLKSEL_RCH (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_FORCE_CLKSEL_RCH PMU_CONTROL_FORCE_CLKSEL_RCH_Msk +#define PMU_CONTROL_PWUPCYC_Pos (8UL) /*!< PMU CONTROL: PWUPCYC (Bit 8) */ +#define PMU_CONTROL_PWUPCYC_Msk (0xff00UL) /*!< PMU CONTROL: PWUPCYC (Bitfield-Mask: 0xff) */ +#define PMU_CONTROL_PWUPCYC PMU_CONTROL_PWUPCYC_Msk +#define PMU_CONTROL_PLLL_SEL_Pos (5UL) /*!< PMU CONTROL: PLLL_SEL (Bit 5) */ +#define PMU_CONTROL_PLLL_SEL_Msk (0x20UL) /*!< PMU CONTROL: PLLL_SEL (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_PLLL_SEL PMU_CONTROL_PLLL_SEL_Msk +#define PMU_CONTROL_PLLH_SEL_Pos (4UL) /*!< PMU CONTROL: PLLH_SEL (Bit 4) */ +#define PMU_CONTROL_PLLH_SEL_Msk (0x10UL) /*!< PMU CONTROL: PLLH_SEL (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_PLLH_SEL PMU_CONTROL_PLLH_SEL_Msk +#define PMU_CONTROL_INT_6M_EN_Pos (3UL) /*!< PMU CONTROL: INT_6M_EN (Bit 3) */ +#define PMU_CONTROL_INT_6M_EN_Msk (0x8UL) /*!< PMU CONTROL: INT_6M_EN (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_INT_6M_EN PMU_CONTROL_INT_6M_EN_Msk +#define PMU_CONTROL_INT_32K_EN_Pos (2UL) /*!< PMU CONTROL: INT_32K_EN (Bit 2) */ +#define PMU_CONTROL_INT_32K_EN_Msk (0x4UL) /*!< PMU CONTROL: INT_32K_EN (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_INT_32K_EN PMU_CONTROL_INT_32K_EN_Msk +#define PMU_CONTROL_RTCCLK_SEL_Pos (1UL) /*!< PMU CONTROL: RTCCLK_SEL (Bit 1) */ +#define PMU_CONTROL_RTCCLK_SEL_Msk (0x2UL) /*!< PMU CONTROL: RTCCLK_SEL (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_RTCCLK_SEL PMU_CONTROL_RTCCLK_SEL_Msk +#define PMU_CONTROL_INT_IOA_EN_Pos (0UL) /*!< PMU CONTROL: INT_IOA_EN (Bit 0) */ +#define PMU_CONTROL_INT_IOA_EN_Msk (0x1UL) /*!< PMU CONTROL: INT_IOA_EN (Bitfield-Mask: 0x01) */ +#define PMU_CONTROL_INT_IOA_EN PMU_CONTROL_INT_IOA_EN_Msk +/* ========================================================== STS ========================================================== */ +#define PMU_STS_MODE_Pos (24UL) /*!< PMU STS: MODE (Bit 24) */ +#define PMU_STS_MODE_Msk (0x1000000UL) /*!< PMU STS: MODE (Bitfield-Mask: 0x01) */ +#define PMU_STS_MODE PMU_STS_MODE_Msk +#define PMU_STS_WKUMODE_Pos (22UL) /*!< PMU STS: WKUMODE (Bit 22) */ +#define PMU_STS_WKUMODE_Msk (0x400000UL) /*!< PMU STS: WKUMODE (Bitfield-Mask: 0x01) */ +#define PMU_STS_WKUMODE PMU_STS_WKUMODE_Msk +#define PMU_STS_WKUXTAL_Pos (20UL) /*!< PMU STS: WKUXTAL (Bit 20) */ +#define PMU_STS_WKUXTAL_Msk (0x100000UL) /*!< PMU STS: WKUXTAL (Bitfield-Mask: 0x01) */ +#define PMU_STS_WKUXTAL PMU_STS_WKUXTAL_Msk +#define PMU_STS_WKUU32K_Pos (19UL) /*!< PMU STS: WKUU32K (Bit 19) */ +#define PMU_STS_WKUU32K_Msk (0x80000UL) /*!< PMU STS: WKUU32K (Bitfield-Mask: 0x01) */ +#define PMU_STS_WKUU32K PMU_STS_WKUU32K_Msk +#define PMU_STS_WKUANA_Pos (18UL) /*!< PMU STS: WKUANA (Bit 18) */ +#define PMU_STS_WKUANA_Msk (0x40000UL) /*!< PMU STS: WKUANA (Bitfield-Mask: 0x01) */ +#define PMU_STS_WKUANA PMU_STS_WKUANA_Msk +#define PMU_STS_WKURTC_Pos (17UL) /*!< PMU STS: WKURTC (Bit 17) */ +#define PMU_STS_WKURTC_Msk (0x20000UL) /*!< PMU STS: WKURTC (Bitfield-Mask: 0x01) */ +#define PMU_STS_WKURTC PMU_STS_WKURTC_Msk +#define PMU_STS_WKUIOA_Pos (16UL) /*!< PMU STS: WKUIOA (Bit 16) */ +#define PMU_STS_WKUIOA_Msk (0x10000UL) /*!< PMU STS: WKUIOA (Bitfield-Mask: 0x01) */ +#define PMU_STS_WKUIOA PMU_STS_WKUIOA_Msk +#define PMU_STS_MODERST_Pos (10UL) /*!< PMU STS: MODERST (Bit 10) */ +#define PMU_STS_MODERST_Msk (0x400UL) /*!< PMU STS: MODERST (Bitfield-Mask: 0x01) */ +#define PMU_STS_MODERST PMU_STS_MODERST_Msk +#define PMU_STS_SFTRST_Pos (8UL) /*!< PMU STS: SFTRST (Bit 8) */ +#define PMU_STS_SFTRST_Msk (0x100UL) /*!< PMU STS: SFTRST (Bitfield-Mask: 0x01) */ +#define PMU_STS_SFTRST PMU_STS_SFTRST_Msk +#define PMU_STS_WDTRST_Pos (7UL) /*!< PMU STS: WDTRST (Bit 7) */ +#define PMU_STS_WDTRST_Msk (0x80UL) /*!< PMU STS: WDTRST (Bitfield-Mask: 0x01) */ +#define PMU_STS_WDTRST PMU_STS_WDTRST_Msk +#define PMU_STS_DPORST_Pos (6UL) /*!< PMU STS: DPORST (Bit 6) */ +#define PMU_STS_DPORST_Msk (0x40UL) /*!< PMU STS: DPORST (Bitfield-Mask: 0x01) */ +#define PMU_STS_DPORST PMU_STS_DPORST_Msk +#define PMU_STS_PORST_Pos (5UL) /*!< PMU STS: PORST (Bit 5) */ +#define PMU_STS_PORST_Msk (0x20UL) /*!< PMU STS: PORST (Bitfield-Mask: 0x01) */ +#define PMU_STS_PORST PMU_STS_PORST_Msk +#define PMU_STS_EXTRST_Pos (4UL) /*!< PMU STS: EXTRST (Bit 4) */ +#define PMU_STS_EXTRST_Msk (0x10UL) /*!< PMU STS: EXTRST (Bitfield-Mask: 0x01) */ +#define PMU_STS_EXTRST PMU_STS_EXTRST_Msk +#define PMU_STS_EXIST_6M_Pos (3UL) /*!< PMU STS: EXIST_6M (Bit 3) */ +#define PMU_STS_EXIST_6M_Msk (0x8UL) /*!< PMU STS: EXIST_6M (Bitfield-Mask: 0x01) */ +#define PMU_STS_EXIST_6M PMU_STS_EXIST_6M_Msk +#define PMU_STS_EXIST_32K_Pos (2UL) /*!< PMU STS: EXIST_32K (Bit 2) */ +#define PMU_STS_EXIST_32K_Msk (0x4UL) /*!< PMU STS: EXIST_32K (Bitfield-Mask: 0x01) */ +#define PMU_STS_EXIST_32K PMU_STS_EXIST_32K_Msk +#define PMU_STS_INT_6M_Pos (1UL) /*!< PMU STS: INT_6M (Bit 1) */ +#define PMU_STS_INT_6M_Msk (0x2UL) /*!< PMU STS: INT_6M (Bitfield-Mask: 0x01) */ +#define PMU_STS_INT_6M PMU_STS_INT_6M_Msk +#define PMU_STS_INT_32K_Pos (0UL) /*!< PMU STS: INT_32K (Bit 0) */ +#define PMU_STS_INT_32K_Msk (0x1UL) /*!< PMU STS: INT_32K (Bitfield-Mask: 0x01) */ +#define PMU_STS_INT_32K PMU_STS_INT_32K_Msk +/* ======================================================== WDTPASS ======================================================== */ +#define PMU_WDTPASS_UNLOCK_Pos (0UL) /*!< PMU WDTPASS: UNLOCK (Bit 0) */ +#define PMU_WDTPASS_UNLOCK_Msk (0x1UL) /*!< PMU WDTPASS: UNLOCK (Bitfield-Mask: 0x01) */ +#define PMU_WDTPASS_UNLOCK PMU_WDTPASS_UNLOCK_Msk +/* ========================================================= WDTEN ========================================================= */ +#define PMU_WDTEN_WDTSEL_Pos (2UL) /*!< PMU WDTEN: WDTSEL (Bit 2) */ +#define PMU_WDTEN_WDTSEL_Msk (0xcUL) /*!< PMU WDTEN: WDTSEL (Bitfield-Mask: 0x03) */ +#define PMU_WDTEN_WDTSEL PMU_WDTEN_WDTSEL_Msk +#define PMU_WDTEN_WDTEN_Pos (0UL) /*!< PMU WDTEN: WDTEN (Bit 0) */ +#define PMU_WDTEN_WDTEN_Msk (0x1UL) /*!< PMU WDTEN: WDTEN (Bitfield-Mask: 0x01) */ +#define PMU_WDTEN_WDTEN PMU_WDTEN_WDTEN_Msk +/* ======================================================== WDTCLR ========================================================= */ +#define PMU_WDTCLR_WDTCNT_Pos (0UL) /*!< PMU WDTCLR: WDTCNT (Bit 0) */ +#define PMU_WDTCLR_WDTCNT_Msk (0xffffUL) /*!< PMU WDTCLR: WDTCNT (Bitfield-Mask: 0xffff) */ +#define PMU_WDTCLR_WDTCNT PMU_WDTCLR_WDTCNT_Msk +/* ========================================================== RAM ========================================================== */ +#define PMU_RAM_RAM_Pos (0UL) /*!< PMU RAM: RAM (Bit 0) */ +#define PMU_RAM_RAM_Msk (0xffffffffUL) /*!< PMU RAM: RAM (Bitfield-Mask: 0xffffffff) */ +#define PMU_RAM_RAM PMU_RAM_RAM_Msk + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define PWM_CTL_ID_Pos (6UL) /*!< PWM CTL: ID (Bit 6) */ +#define PWM_CTL_ID_Msk (0xc0UL) /*!< PWM CTL: ID (Bitfield-Mask: 0x03) */ +#define PWM_CTL_ID PWM_CTL_ID_Msk +#define PWM_CTL_MC_Pos (4UL) /*!< PWM CTL: MC (Bit 4) */ +#define PWM_CTL_MC_Msk (0x30UL) /*!< PWM CTL: MC (Bitfield-Mask: 0x03) */ +#define PWM_CTL_MC PWM_CTL_MC_Msk +#define PWM_CTL_TSEL_Pos (3UL) /*!< PWM CTL: TSEL (Bit 3) */ +#define PWM_CTL_TSEL_Msk (0x8UL) /*!< PWM CTL: TSEL (Bitfield-Mask: 0x01) */ +#define PWM_CTL_TSEL PWM_CTL_TSEL_Msk +#define PWM_CTL_CLR_Pos (2UL) /*!< PWM CTL: CLR (Bit 2) */ +#define PWM_CTL_CLR_Msk (0x4UL) /*!< PWM CTL: CLR (Bitfield-Mask: 0x01) */ +#define PWM_CTL_CLR PWM_CTL_CLR_Msk +#define PWM_CTL_IE_Pos (1UL) /*!< PWM CTL: IE (Bit 1) */ +#define PWM_CTL_IE_Msk (0x2UL) /*!< PWM CTL: IE (Bitfield-Mask: 0x01) */ +#define PWM_CTL_IE PWM_CTL_IE_Msk +#define PWM_CTL_IFG_Pos (0UL) /*!< PWM CTL: IFG (Bit 0) */ +#define PWM_CTL_IFG_Msk (0x1UL) /*!< PWM CTL: IFG (Bitfield-Mask: 0x01) */ +#define PWM_CTL_IFG PWM_CTL_IFG_Msk +/* ========================================================== TAR ========================================================== */ +#define PWM_TAR_TAR_Pos (0UL) /*!< PWM TAR: TAR (Bit 0) */ +#define PWM_TAR_TAR_Msk (0xffffUL) /*!< PWM TAR: TAR (Bitfield-Mask: 0xffff) */ +#define PWM_TAR_TAR PWM_TAR_TAR_Msk +/* ========================================================= CCTL ========================================================== */ +#define PWM_CCTL_CM_Pos (14UL) /*!< PWM CCTL: CM (Bit 14) */ +#define PWM_CCTL_CM_Msk (0xc000UL) /*!< PWM CCTL: CM (Bitfield-Mask: 0x03) */ +#define PWM_CCTL_CM PWM_CCTL_CM_Msk +#define PWM_CCTL_SCCI_Pos (10UL) /*!< PWM CCTL: SCCI (Bit 10) */ +#define PWM_CCTL_SCCI_Msk (0x400UL) /*!< PWM CCTL: SCCI (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_SCCI PWM_CCTL_SCCI_Msk +#define PWM_CCTL_OUTEN_Pos (9UL) /*!< PWM CCTL: OUTEN (Bit 9) */ +#define PWM_CCTL_OUTEN_Msk (0x200UL) /*!< PWM CCTL: OUTEN (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_OUTEN PWM_CCTL_OUTEN_Msk +#define PWM_CCTL_CAP_Pos (8UL) /*!< PWM CCTL: CAP (Bit 8) */ +#define PWM_CCTL_CAP_Msk (0x100UL) /*!< PWM CCTL: CAP (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_CAP PWM_CCTL_CAP_Msk +#define PWM_CCTL_OUTMOD_Pos (5UL) /*!< PWM CCTL: OUTMOD (Bit 5) */ +#define PWM_CCTL_OUTMOD_Msk (0xe0UL) /*!< PWM CCTL: OUTMOD (Bitfield-Mask: 0x07) */ +#define PWM_CCTL_OUTMOD PWM_CCTL_OUTMOD_Msk +#define PWM_CCTL_CCIE_Pos (4UL) /*!< PWM CCTL: CCIE (Bit 4) */ +#define PWM_CCTL_CCIE_Msk (0x10UL) /*!< PWM CCTL: CCIE (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_CCIE PWM_CCTL_CCIE_Msk +#define PWM_CCTL_OUT_Pos (2UL) /*!< PWM CCTL: OUT (Bit 2) */ +#define PWM_CCTL_OUT_Msk (0x4UL) /*!< PWM CCTL: OUT (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_OUT PWM_CCTL_OUT_Msk +#define PWM_CCTL_COV_Pos (1UL) /*!< PWM CCTL: COV (Bit 1) */ +#define PWM_CCTL_COV_Msk (0x2UL) /*!< PWM CCTL: COV (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_COV PWM_CCTL_COV_Msk +#define PWM_CCTL_CCIFG_Pos (0UL) /*!< PWM CCTL: CCIFG (Bit 0) */ +#define PWM_CCTL_CCIFG_Msk (0x1UL) /*!< PWM CCTL: CCIFG (Bitfield-Mask: 0x01) */ +#define PWM_CCTL_CCIFG PWM_CCTL_CCIFG_Msk +/* ========================================================== CCR ========================================================== */ +#define PWM_CCR_CCRx_Pos (0UL) /*!< PWM CCR: CCRx (Bit 0) */ +#define PWM_CCR_CCRx_Msk (0xffffUL) /*!< PWM CCR: CCRx (Bitfield-Mask: 0xffff) */ +#define PWM_CCR_CCRx PWM_CCR_CCRx_Msk + + +/* =========================================================================================================================== */ +/* ================ PWM_SEL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= O_SEL ========================================================= */ +#define PWM_SEL_O_SEL_SEL3_Pos (12UL) /*!< PWM_SEL O_SEL: SEL3 (Bit 12) */ +#define PWM_SEL_O_SEL_SEL3_Msk (0xf000UL) /*!< PWM_SEL O_SEL: SEL3 (Bitfield-Mask: 0x0f) */ +#define PWM_SEL_O_SEL_SEL3 PWM_SEL_O_SEL_SEL3_Msk +#define PWM_SEL_O_SEL_SEL2_Pos (8UL) /*!< PWM_SEL O_SEL: SEL2 (Bit 8) */ +#define PWM_SEL_O_SEL_SEL2_Msk (0xf00UL) /*!< PWM_SEL O_SEL: SEL2 (Bitfield-Mask: 0x0f) */ +#define PWM_SEL_O_SEL_SEL2 PWM_SEL_O_SEL_SEL2_Msk +#define PWM_SEL_O_SEL_SEL1_Pos (4UL) /*!< PWM_SEL O_SEL: SEL1 (Bit 4) */ +#define PWM_SEL_O_SEL_SEL1_Msk (0xf0UL) /*!< PWM_SEL O_SEL: SEL1 (Bitfield-Mask: 0x0f) */ +#define PWM_SEL_O_SEL_SEL1 PWM_SEL_O_SEL_SEL1_Msk +#define PWM_SEL_O_SEL_SEL0_Pos (0UL) /*!< PWM_SEL O_SEL: SEL0 (Bit 0) */ +#define PWM_SEL_O_SEL_SEL0_Msk (0xfUL) /*!< PWM_SEL O_SEL: SEL0 (Bitfield-Mask: 0x0f) */ +#define PWM_SEL_O_SEL_SEL0 PWM_SEL_O_SEL_SEL0_Msk +/* ======================================================== I_SEL01 ======================================================== */ +#define PWM_SEL_I_SEL01_SEL12_Pos (20UL) /*!< PWM_SEL I_SEL01: SEL12 (Bit 20) */ +#define PWM_SEL_I_SEL01_SEL12_Msk (0x300000UL) /*!< PWM_SEL I_SEL01: SEL12 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL01_SEL12 PWM_SEL_I_SEL01_SEL12_Msk +#define PWM_SEL_I_SEL01_SEL11_Pos (18UL) /*!< PWM_SEL I_SEL01: SEL11 (Bit 18) */ +#define PWM_SEL_I_SEL01_SEL11_Msk (0xc0000UL) /*!< PWM_SEL I_SEL01: SEL11 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL01_SEL11 PWM_SEL_I_SEL01_SEL11_Msk +#define PWM_SEL_I_SEL01_SEL10_Pos (16UL) /*!< PWM_SEL I_SEL01: SEL10 (Bit 16) */ +#define PWM_SEL_I_SEL01_SEL10_Msk (0x30000UL) /*!< PWM_SEL I_SEL01: SEL10 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL01_SEL10 PWM_SEL_I_SEL01_SEL10_Msk +#define PWM_SEL_I_SEL01_SEL02_Pos (4UL) /*!< PWM_SEL I_SEL01: SEL02 (Bit 4) */ +#define PWM_SEL_I_SEL01_SEL02_Msk (0x30UL) /*!< PWM_SEL I_SEL01: SEL02 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL01_SEL02 PWM_SEL_I_SEL01_SEL02_Msk +#define PWM_SEL_I_SEL01_SEL01_Pos (2UL) /*!< PWM_SEL I_SEL01: SEL01 (Bit 2) */ +#define PWM_SEL_I_SEL01_SEL01_Msk (0xcUL) /*!< PWM_SEL I_SEL01: SEL01 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL01_SEL01 PWM_SEL_I_SEL01_SEL01_Msk +#define PWM_SEL_I_SEL01_SEL00_Pos (0UL) /*!< PWM_SEL I_SEL01: SEL00 (Bit 0) */ +#define PWM_SEL_I_SEL01_SEL00_Msk (0x3UL) /*!< PWM_SEL I_SEL01: SEL00 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL01_SEL00 PWM_SEL_I_SEL01_SEL00_Msk +/* ======================================================== I_SEL23 ======================================================== */ +#define PWM_SEL_I_SEL23_SEL32_Pos (20UL) /*!< PWM_SEL I_SEL23: SEL32 (Bit 20) */ +#define PWM_SEL_I_SEL23_SEL32_Msk (0x300000UL) /*!< PWM_SEL I_SEL23: SEL32 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL23_SEL32 PWM_SEL_I_SEL23_SEL32_Msk +#define PWM_SEL_I_SEL23_SEL31_Pos (18UL) /*!< PWM_SEL I_SEL23: SEL31 (Bit 18) */ +#define PWM_SEL_I_SEL23_SEL31_Msk (0xc0000UL) /*!< PWM_SEL I_SEL23: SEL31 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL23_SEL31 PWM_SEL_I_SEL23_SEL31_Msk +#define PWM_SEL_I_SEL23_SEL30_Pos (16UL) /*!< PWM_SEL I_SEL23: SEL30 (Bit 16) */ +#define PWM_SEL_I_SEL23_SEL30_Msk (0x30000UL) /*!< PWM_SEL I_SEL23: SEL30 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL23_SEL30 PWM_SEL_I_SEL23_SEL30_Msk +#define PWM_SEL_I_SEL23_SEL22_Pos (4UL) /*!< PWM_SEL I_SEL23: SEL22 (Bit 4) */ +#define PWM_SEL_I_SEL23_SEL22_Msk (0x30UL) /*!< PWM_SEL I_SEL23: SEL22 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL23_SEL22 PWM_SEL_I_SEL23_SEL22_Msk +#define PWM_SEL_I_SEL23_SEL21_Pos (2UL) /*!< PWM_SEL I_SEL23: SEL21 (Bit 2) */ +#define PWM_SEL_I_SEL23_SEL21_Msk (0xcUL) /*!< PWM_SEL I_SEL23: SEL21 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL23_SEL21 PWM_SEL_I_SEL23_SEL21_Msk +#define PWM_SEL_I_SEL23_SEL20_Pos (0UL) /*!< PWM_SEL I_SEL23: SEL20 (Bit 0) */ +#define PWM_SEL_I_SEL23_SEL20_Msk (0x3UL) /*!< PWM_SEL I_SEL23: SEL20 (Bitfield-Mask: 0x03) */ +#define PWM_SEL_I_SEL23_SEL20 PWM_SEL_I_SEL23_SEL20_Msk + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SEC ========================================================== */ +#define RTC_SEC_SEC_Pos (0UL) /*!< RTC SEC: SEC (Bit 0) */ +#define RTC_SEC_SEC_Msk (0x7fUL) /*!< RTC SEC: SEC (Bitfield-Mask: 0x7f) */ +#define RTC_SEC_SEC RTC_SEC_SEC_Msk +/* ========================================================== MIN ========================================================== */ +#define RTC_MIN_MIN_Pos (0UL) /*!< RTC MIN: MIN (Bit 0) */ +#define RTC_MIN_MIN_Msk (0x7fUL) /*!< RTC MIN: MIN (Bitfield-Mask: 0x7f) */ +#define RTC_MIN_MIN RTC_MIN_MIN_Msk +/* ========================================================= HOUR ========================================================== */ +#define RTC_HOUR_HOUR_Pos (0UL) /*!< RTC HOUR: HOUR (Bit 0) */ +#define RTC_HOUR_HOUR_Msk (0x3fUL) /*!< RTC HOUR: HOUR (Bitfield-Mask: 0x3f) */ +#define RTC_HOUR_HOUR RTC_HOUR_HOUR_Msk +/* ========================================================== DAY ========================================================== */ +#define RTC_DAY_DAY_Pos (0UL) /*!< RTC DAY: DAY (Bit 0) */ +#define RTC_DAY_DAY_Msk (0x3fUL) /*!< RTC DAY: DAY (Bitfield-Mask: 0x3f) */ +#define RTC_DAY_DAY RTC_DAY_DAY_Msk +/* ========================================================= WEEK ========================================================== */ +#define RTC_WEEK_WEEK_Pos (0UL) /*!< RTC WEEK: WEEK (Bit 0) */ +#define RTC_WEEK_WEEK_Msk (0x7UL) /*!< RTC WEEK: WEEK (Bitfield-Mask: 0x07) */ +#define RTC_WEEK_WEEK RTC_WEEK_WEEK_Msk +/* ========================================================== MON ========================================================== */ +#define RTC_MON_MON_Pos (0UL) /*!< RTC MON: MON (Bit 0) */ +#define RTC_MON_MON_Msk (0x1fUL) /*!< RTC MON: MON (Bitfield-Mask: 0x1f) */ +#define RTC_MON_MON RTC_MON_MON_Msk +/* ========================================================= YEAR ========================================================== */ +#define RTC_YEAR_YEAR_Pos (0UL) /*!< RTC YEAR: YEAR (Bit 0) */ +#define RTC_YEAR_YEAR_Msk (0xffUL) /*!< RTC YEAR: YEAR (Bitfield-Mask: 0xff) */ +#define RTC_YEAR_YEAR RTC_YEAR_YEAR_Msk +/* ========================================================= TIME ========================================================== */ +#define RTC_TIME_TIME_Pos (0UL) /*!< RTC TIME: TIME (Bit 0) */ +#define RTC_TIME_TIME_Msk (0x3fffffUL) /*!< RTC TIME: TIME (Bitfield-Mask: 0x3fffff) */ +#define RTC_TIME_TIME RTC_TIME_TIME_Msk +/* ======================================================== WKUSEC ========================================================= */ +#define RTC_WKUSEC_WKUSEC_Pos (0UL) /*!< RTC WKUSEC: WKUSEC (Bit 0) */ +#define RTC_WKUSEC_WKUSEC_Msk (0x3fUL) /*!< RTC WKUSEC: WKUSEC (Bitfield-Mask: 0x3f) */ +#define RTC_WKUSEC_WKUSEC RTC_WKUSEC_WKUSEC_Msk +/* ======================================================== WKUMIN ========================================================= */ +#define RTC_WKUMIN_WKUMIN_Pos (0UL) /*!< RTC WKUMIN: WKUMIN (Bit 0) */ +#define RTC_WKUMIN_WKUMIN_Msk (0x3fUL) /*!< RTC WKUMIN: WKUMIN (Bitfield-Mask: 0x3f) */ +#define RTC_WKUMIN_WKUMIN RTC_WKUMIN_WKUMIN_Msk +/* ======================================================== WKUHOUR ======================================================== */ +#define RTC_WKUHOUR_WKUHOUR_Pos (0UL) /*!< RTC WKUHOUR: WKUHOUR (Bit 0) */ +#define RTC_WKUHOUR_WKUHOUR_Msk (0x1fUL) /*!< RTC WKUHOUR: WKUHOUR (Bitfield-Mask: 0x1f) */ +#define RTC_WKUHOUR_WKUHOUR RTC_WKUHOUR_WKUHOUR_Msk +/* ======================================================== WKUCNT ========================================================= */ +#define RTC_WKUCNT_CNTSEL_Pos (24UL) /*!< RTC WKUCNT: CNTSEL (Bit 24) */ +#define RTC_WKUCNT_CNTSEL_Msk (0x3000000UL) /*!< RTC WKUCNT: CNTSEL (Bitfield-Mask: 0x03) */ +#define RTC_WKUCNT_CNTSEL RTC_WKUCNT_CNTSEL_Msk +#define RTC_WKUCNT_WKUCNT_Pos (0UL) /*!< RTC WKUCNT: WKUCNT (Bit 0) */ +#define RTC_WKUCNT_WKUCNT_Msk (0xffffffUL) /*!< RTC WKUCNT: WKUCNT (Bitfield-Mask: 0xffffff) */ +#define RTC_WKUCNT_WKUCNT RTC_WKUCNT_WKUCNT_Msk +/* ========================================================== CAL ========================================================== */ +#define RTC_CAL_CAL_Pos (0UL) /*!< RTC CAL: CAL (Bit 0) */ +#define RTC_CAL_CAL_Msk (0x3fffUL) /*!< RTC CAL: CAL (Bitfield-Mask: 0x3fff) */ +#define RTC_CAL_CAL RTC_CAL_CAL_Msk +/* ========================================================== DIV ========================================================== */ +#define RTC_DIV_RTCDIV_Pos (0UL) /*!< RTC DIV: RTCDIV (Bit 0) */ +#define RTC_DIV_RTCDIV_Msk (0x3ffffffUL) /*!< RTC DIV: RTCDIV (Bitfield-Mask: 0x3ffffff) */ +#define RTC_DIV_RTCDIV RTC_DIV_RTCDIV_Msk +/* ========================================================== CTL ========================================================== */ +#define RTC_CTL_RTCPLLCLKSEL_Pos (4UL) /*!< RTC CTL: RTCPLLCLKSEL (Bit 4) */ +#define RTC_CTL_RTCPLLCLKSEL_Msk (0x10UL) /*!< RTC CTL: RTCPLLCLKSEL (Bitfield-Mask: 0x01) */ +#define RTC_CTL_RTCPLLCLKSEL RTC_CTL_RTCPLLCLKSEL_Msk +#define RTC_CTL_RTCPLLOE_Pos (2UL) /*!< RTC CTL: RTCPLLOE (Bit 2) */ +#define RTC_CTL_RTCPLLOE_Msk (0x4UL) /*!< RTC CTL: RTCPLLOE (Bitfield-Mask: 0x01) */ +#define RTC_CTL_RTCPLLOE RTC_CTL_RTCPLLOE_Msk +/* ========================================================== ITV ========================================================== */ +#define RTC_ITV_ITV_Pos (0UL) /*!< RTC ITV: ITV (Bit 0) */ +#define RTC_ITV_ITV_Msk (0x7UL) /*!< RTC ITV: ITV (Bitfield-Mask: 0x07) */ +#define RTC_ITV_ITV RTC_ITV_ITV_Msk +/* ========================================================= SITV ========================================================== */ +#define RTC_SITV_SITVEN_Pos (6UL) /*!< RTC SITV: SITVEN (Bit 6) */ +#define RTC_SITV_SITVEN_Msk (0x40UL) /*!< RTC SITV: SITVEN (Bitfield-Mask: 0x01) */ +#define RTC_SITV_SITVEN RTC_SITV_SITVEN_Msk +#define RTC_SITV_SITV_Pos (0UL) /*!< RTC SITV: SITV (Bit 0) */ +#define RTC_SITV_SITV_Msk (0x3fUL) /*!< RTC SITV: SITV (Bitfield-Mask: 0x3f) */ +#define RTC_SITV_SITV RTC_SITV_SITV_Msk +/* ========================================================== PWD ========================================================== */ +#define RTC_PWD_PWDEN_Pos (0UL) /*!< RTC PWD: PWDEN (Bit 0) */ +#define RTC_PWD_PWDEN_Msk (0x1UL) /*!< RTC PWD: PWDEN (Bitfield-Mask: 0x01) */ +#define RTC_PWD_PWDEN RTC_PWD_PWDEN_Msk +/* ========================================================== CE =========================================================== */ +#define RTC_CE_BSY_Pos (1UL) /*!< RTC CE: BSY (Bit 1) */ +#define RTC_CE_BSY_Msk (0x2UL) /*!< RTC CE: BSY (Bitfield-Mask: 0x01) */ +#define RTC_CE_BSY RTC_CE_BSY_Msk +#define RTC_CE_CE_Pos (0UL) /*!< RTC CE: CE (Bit 0) */ +#define RTC_CE_CE_Msk (0x1UL) /*!< RTC CE: CE (Bitfield-Mask: 0x01) */ +#define RTC_CE_CE RTC_CE_CE_Msk +/* ========================================================= LOAD ========================================================== */ +#define RTC_LOAD_LOAD_Pos (0UL) /*!< RTC LOAD: LOAD (Bit 0) */ +#define RTC_LOAD_LOAD_Msk (0xffffffffUL) /*!< RTC LOAD: LOAD (Bitfield-Mask: 0xffffffff) */ +#define RTC_LOAD_LOAD RTC_LOAD_LOAD_Msk +/* ======================================================== INTSTS ========================================================= */ +#define RTC_INTSTS_INTSTS10_Pos (10UL) /*!< RTC INTSTS: INTSTS10 (Bit 10) */ +#define RTC_INTSTS_INTSTS10_Msk (0x400UL) /*!< RTC INTSTS: INTSTS10 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS10 RTC_INTSTS_INTSTS10_Msk +#define RTC_INTSTS_INTSTS8_Pos (8UL) /*!< RTC INTSTS: INTSTS8 (Bit 8) */ +#define RTC_INTSTS_INTSTS8_Msk (0x100UL) /*!< RTC INTSTS: INTSTS8 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS8 RTC_INTSTS_INTSTS8_Msk +#define RTC_INTSTS_INTSTS6_Pos (6UL) /*!< RTC INTSTS: INTSTS6 (Bit 6) */ +#define RTC_INTSTS_INTSTS6_Msk (0x40UL) /*!< RTC INTSTS: INTSTS6 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS6 RTC_INTSTS_INTSTS6_Msk +#define RTC_INTSTS_INTSTS5_Pos (5UL) /*!< RTC INTSTS: INTSTS5 (Bit 5) */ +#define RTC_INTSTS_INTSTS5_Msk (0x20UL) /*!< RTC INTSTS: INTSTS5 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS5 RTC_INTSTS_INTSTS5_Msk +#define RTC_INTSTS_INTSTS4_Pos (4UL) /*!< RTC INTSTS: INTSTS4 (Bit 4) */ +#define RTC_INTSTS_INTSTS4_Msk (0x10UL) /*!< RTC INTSTS: INTSTS4 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS4 RTC_INTSTS_INTSTS4_Msk +#define RTC_INTSTS_INTSTS3_Pos (3UL) /*!< RTC INTSTS: INTSTS3 (Bit 3) */ +#define RTC_INTSTS_INTSTS3_Msk (0x8UL) /*!< RTC INTSTS: INTSTS3 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS3 RTC_INTSTS_INTSTS3_Msk +#define RTC_INTSTS_INTSTS2_Pos (2UL) /*!< RTC INTSTS: INTSTS2 (Bit 2) */ +#define RTC_INTSTS_INTSTS2_Msk (0x4UL) /*!< RTC INTSTS: INTSTS2 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS2 RTC_INTSTS_INTSTS2_Msk +#define RTC_INTSTS_INTSTS1_Pos (1UL) /*!< RTC INTSTS: INTSTS1 (Bit 1) */ +#define RTC_INTSTS_INTSTS1_Msk (0x2UL) /*!< RTC INTSTS: INTSTS1 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS1 RTC_INTSTS_INTSTS1_Msk +#define RTC_INTSTS_INTSTS0_Pos (0UL) /*!< RTC INTSTS: INTSTS0 (Bit 0) */ +#define RTC_INTSTS_INTSTS0_Msk (0x1UL) /*!< RTC INTSTS: INTSTS0 (Bitfield-Mask: 0x01) */ +#define RTC_INTSTS_INTSTS0 RTC_INTSTS_INTSTS0_Msk +/* ========================================================= INTEN ========================================================= */ +#define RTC_INTEN_INTEN10_Pos (10UL) /*!< RTC INTEN: INTEN10 (Bit 10) */ +#define RTC_INTEN_INTEN10_Msk (0x400UL) /*!< RTC INTEN: INTEN10 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN10 RTC_INTEN_INTEN10_Msk +#define RTC_INTEN_INTEN8_Pos (8UL) /*!< RTC INTEN: INTEN8 (Bit 8) */ +#define RTC_INTEN_INTEN8_Msk (0x100UL) /*!< RTC INTEN: INTEN8 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN8 RTC_INTEN_INTEN8_Msk +#define RTC_INTEN_INTEN6_Pos (6UL) /*!< RTC INTEN: INTEN6 (Bit 6) */ +#define RTC_INTEN_INTEN6_Msk (0x40UL) /*!< RTC INTEN: INTEN6 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN6 RTC_INTEN_INTEN6_Msk +#define RTC_INTEN_INTEN5_Pos (5UL) /*!< RTC INTEN: INTEN5 (Bit 5) */ +#define RTC_INTEN_INTEN5_Msk (0x20UL) /*!< RTC INTEN: INTEN5 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN5 RTC_INTEN_INTEN5_Msk +#define RTC_INTEN_INTEN4_Pos (4UL) /*!< RTC INTEN: INTEN4 (Bit 4) */ +#define RTC_INTEN_INTEN4_Msk (0x10UL) /*!< RTC INTEN: INTEN4 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN4 RTC_INTEN_INTEN4_Msk +#define RTC_INTEN_INTRN3_Pos (3UL) /*!< RTC INTEN: INTRN3 (Bit 3) */ +#define RTC_INTEN_INTRN3_Msk (0x8UL) /*!< RTC INTEN: INTRN3 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTRN3 RTC_INTEN_INTRN3_Msk +#define RTC_INTEN_INTEN2_Pos (2UL) /*!< RTC INTEN: INTEN2 (Bit 2) */ +#define RTC_INTEN_INTEN2_Msk (0x4UL) /*!< RTC INTEN: INTEN2 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN2 RTC_INTEN_INTEN2_Msk +#define RTC_INTEN_INTEN1_Pos (1UL) /*!< RTC INTEN: INTEN1 (Bit 1) */ +#define RTC_INTEN_INTEN1_Msk (0x2UL) /*!< RTC INTEN: INTEN1 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN1 RTC_INTEN_INTEN1_Msk +#define RTC_INTEN_INTEN0_Pos (0UL) /*!< RTC INTEN: INTEN0 (Bit 0) */ +#define RTC_INTEN_INTEN0_Msk (0x1UL) /*!< RTC INTEN: INTEN0 (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_INTEN0 RTC_INTEN_INTEN0_Msk +/* ========================================================= PSCA ========================================================== */ +#define RTC_PSCA_PSCA_Pos (0UL) /*!< RTC PSCA: PSCA (Bit 0) */ +#define RTC_PSCA_PSCA_Msk (0x3UL) /*!< RTC PSCA: PSCA (Bitfield-Mask: 0x03) */ +#define RTC_PSCA_PSCA RTC_PSCA_PSCA_Msk +/* ========================================================= ACTI ========================================================== */ +#define RTC_ACTI_ACTI_Pos (0UL) /*!< RTC ACTI: ACTI (Bit 0) */ +#define RTC_ACTI_ACTI_Msk (0x3fffUL) /*!< RTC ACTI: ACTI (Bitfield-Mask: 0x3fff) */ +#define RTC_ACTI_ACTI RTC_ACTI_ACTI_Msk +/* ======================================================== ACF200 ========================================================= */ +#define RTC_ACF200_F200_Pos (0UL) /*!< RTC ACF200: F200 (Bit 0) */ +#define RTC_ACF200_F200_Msk (0x3ffffffUL) /*!< RTC ACF200: F200 (Bitfield-Mask: 0x3ffffff) */ +#define RTC_ACF200_F200 RTC_ACF200_F200_Msk +/* ========================================================= ACP0 ========================================================== */ +#define RTC_ACP0_P0_Pos (0UL) /*!< RTC ACP0: P0 (Bit 0) */ +#define RTC_ACP0_P0_Msk (0xffffUL) /*!< RTC ACP0: P0 (Bitfield-Mask: 0xffff) */ +#define RTC_ACP0_P0 RTC_ACP0_P0_Msk +/* ========================================================= ACP1 ========================================================== */ +#define RTC_ACP1_P1_Pos (0UL) /*!< RTC ACP1: P1 (Bit 0) */ +#define RTC_ACP1_P1_Msk (0xffffUL) /*!< RTC ACP1: P1 (Bitfield-Mask: 0xffff) */ +#define RTC_ACP1_P1 RTC_ACP1_P1_Msk +/* ========================================================= ACP2 ========================================================== */ +#define RTC_ACP2_P2_Pos (0UL) /*!< RTC ACP2: P2 (Bit 0) */ +#define RTC_ACP2_P2_Msk (0xffffffffUL) /*!< RTC ACP2: P2 (Bitfield-Mask: 0xffffffff) */ +#define RTC_ACP2_P2 RTC_ACP2_P2_Msk +/* ========================================================= ACP3 ========================================================== */ +#define RTC_ACP3_P3_Pos (0UL) /*!< RTC ACP3: P3 (Bit 0) */ +#define RTC_ACP3_P3_Msk (0xffffffffUL) /*!< RTC ACP3: P3 (Bitfield-Mask: 0xffffffff) */ +#define RTC_ACP3_P3 RTC_ACP3_P3_Msk +/* ========================================================= ACP4 ========================================================== */ +#define RTC_ACP4_P4_Pos (0UL) /*!< RTC ACP4: P4 (Bit 0) */ +#define RTC_ACP4_P4_Msk (0xffffUL) /*!< RTC ACP4: P4 (Bitfield-Mask: 0xffff) */ +#define RTC_ACP4_P4 RTC_ACP4_P4_Msk +/* ========================================================= ACP5 ========================================================== */ +#define RTC_ACP5_P5_Pos (0UL) /*!< RTC ACP5: P5 (Bit 0) */ +#define RTC_ACP5_P5_Msk (0xffffUL) /*!< RTC ACP5: P5 (Bitfield-Mask: 0xffff) */ +#define RTC_ACP5_P5 RTC_ACP5_P5_Msk +/* ========================================================= ACP6 ========================================================== */ +#define RTC_ACP6_P6_Pos (0UL) /*!< RTC ACP6: P6 (Bit 0) */ +#define RTC_ACP6_P6_Msk (0xffffUL) /*!< RTC ACP6: P6 (Bitfield-Mask: 0xffff) */ +#define RTC_ACP6_P6 RTC_ACP6_P6_Msk +/* ========================================================= ACP7 ========================================================== */ +#define RTC_ACP7_P7_Pos (0UL) /*!< RTC ACP7: P7 (Bit 0) */ +#define RTC_ACP7_P7_Msk (0xffffUL) /*!< RTC ACP7: P7 (Bitfield-Mask: 0xffff) */ +#define RTC_ACP7_P7 RTC_ACP7_P7_Msk +/* ========================================================== ACK ========================================================== */ +#define RTC_ACK_K_Pos (0UL) /*!< RTC ACK: K (Bit 0) */ +#define RTC_ACK_K_Msk (0xffffUL) /*!< RTC ACK: K (Bitfield-Mask: 0xffff) */ +#define RTC_ACK_K RTC_ACK_K_Msk +/* ======================================================== WKUCNTR ======================================================== */ +#define RTC_WKUCNTR_WKUCNTR_Pos (0UL) /*!< RTC WKUCNTR: WKUCNTR (Bit 0) */ +#define RTC_WKUCNTR_WKUCNTR_Msk (0xffffffUL) /*!< RTC WKUCNTR: WKUCNTR (Bitfield-Mask: 0xffffff) */ +#define RTC_WKUCNTR_WKUCNTR RTC_WKUCNTR_WKUCNTR_Msk +/* ======================================================== ACKTEMP ======================================================== */ +#define RTC_ACKTEMP_KTEMP4_Pos (24UL) /*!< RTC ACKTEMP: KTEMP4 (Bit 24) */ +#define RTC_ACKTEMP_KTEMP4_Msk (0xff000000UL) /*!< RTC ACKTEMP: KTEMP4 (Bitfield-Mask: 0xff) */ +#define RTC_ACKTEMP_KTEMP4 RTC_ACKTEMP_KTEMP4_Msk +#define RTC_ACKTEMP_KTEMP3_Pos (16UL) /*!< RTC ACKTEMP: KTEMP3 (Bit 16) */ +#define RTC_ACKTEMP_KTEMP3_Msk (0xff0000UL) /*!< RTC ACKTEMP: KTEMP3 (Bitfield-Mask: 0xff) */ +#define RTC_ACKTEMP_KTEMP3 RTC_ACKTEMP_KTEMP3_Msk +#define RTC_ACKTEMP_KTEMP2_Pos (8UL) /*!< RTC ACKTEMP: KTEMP2 (Bit 8) */ +#define RTC_ACKTEMP_KTEMP2_Msk (0xff00UL) /*!< RTC ACKTEMP: KTEMP2 (Bitfield-Mask: 0xff) */ +#define RTC_ACKTEMP_KTEMP2 RTC_ACKTEMP_KTEMP2_Msk +#define RTC_ACKTEMP_KTEMP1_Pos (0UL) /*!< RTC ACKTEMP: KTEMP1 (Bit 0) */ +#define RTC_ACKTEMP_KTEMP1_Msk (0xffUL) /*!< RTC ACKTEMP: KTEMP1 (Bitfield-Mask: 0xff) */ +#define RTC_ACKTEMP_KTEMP1 RTC_ACKTEMP_KTEMP1_Msk +/* ======================================================= ALARMTIME ======================================================= */ +#define RTC_ALARMTIME_ALARMTIME_Pos (0UL) /*!< RTC ALARMTIME: ALARMTIME (Bit 0) */ +#define RTC_ALARMTIME_ALARMTIME_Msk (0x3fffffUL) /*!< RTC ALARMTIME: ALARMTIME (Bitfield-Mask: 0x3fffff) */ +#define RTC_ALARMTIME_ALARMTIME RTC_ALARMTIME_ALARMTIME_Msk +/* ======================================================= ALARMSEC ======================================================== */ +#define RTC_ALARMSEC_ALARMSEC_Pos (0UL) /*!< RTC ALARMSEC: ALARMSEC (Bit 0) */ +#define RTC_ALARMSEC_ALARMSEC_Msk (0x7fUL) /*!< RTC ALARMSEC: ALARMSEC (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMSEC_ALARMSEC RTC_ALARMSEC_ALARMSEC_Msk +/* ======================================================= ALARMMIN ======================================================== */ +#define RTC_ALARMMIN_ALARMMIN_Pos (0UL) /*!< RTC ALARMMIN: ALARMMIN (Bit 0) */ +#define RTC_ALARMMIN_ALARMMIN_Msk (0x7fUL) /*!< RTC ALARMMIN: ALARMMIN (Bitfield-Mask: 0x7f) */ +#define RTC_ALARMMIN_ALARMMIN RTC_ALARMMIN_ALARMMIN_Msk +/* ======================================================= ALARMHOUR ======================================================= */ +#define RTC_ALARMHOUR_ALARMHOUR_Pos (0UL) /*!< RTC ALARMHOUR: ALARMHOUR (Bit 0) */ +#define RTC_ALARMHOUR_ALARMHOUR_Msk (0x3fUL) /*!< RTC ALARMHOUR: ALARMHOUR (Bitfield-Mask: 0x3f) */ +#define RTC_ALARMHOUR_ALARMHOUR RTC_ALARMHOUR_ALARMHOUR_Msk +/* ======================================================= ALARMCTL ======================================================== */ +#define RTC_ALARMCTL_TIME_CNT_EN_Pos (2UL) /*!< RTC ALARMCTL: TIME_CNT_EN (Bit 2) */ +#define RTC_ALARMCTL_TIME_CNT_EN_Msk (0x4UL) /*!< RTC ALARMCTL: TIME_CNT_EN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMCTL_TIME_CNT_EN RTC_ALARMCTL_TIME_CNT_EN_Msk +#define RTC_ALARMCTL_ALARM_INACCURATE_Pos (1UL) /*!< RTC ALARMCTL: ALARM_INACCURATE (Bit 1) */ +#define RTC_ALARMCTL_ALARM_INACCURATE_Msk (0x2UL) /*!< RTC ALARMCTL: ALARM_INACCURATE (Bitfield-Mask: 0x01) */ +#define RTC_ALARMCTL_ALARM_INACCURATE RTC_ALARMCTL_ALARM_INACCURATE_Msk +#define RTC_ALARMCTL_ALARM_EN_Pos (0UL) /*!< RTC ALARMCTL: ALARM_EN (Bit 0) */ +#define RTC_ALARMCTL_ALARM_EN_Msk (0x1UL) /*!< RTC ALARMCTL: ALARM_EN (Bitfield-Mask: 0x01) */ +#define RTC_ALARMCTL_ALARM_EN RTC_ALARMCTL_ALARM_EN_Msk +/* ======================================================= ADCUCALK ======================================================== */ +#define RTC_ADCUCALK_UCAL_K3_Pos (16UL) /*!< RTC ADCUCALK: UCAL_K3 (Bit 16) */ +#define RTC_ADCUCALK_UCAL_K3_Msk (0xffff0000UL) /*!< RTC ADCUCALK: UCAL_K3 (Bitfield-Mask: 0xffff) */ +#define RTC_ADCUCALK_UCAL_K3 RTC_ADCUCALK_UCAL_K3_Msk +#define RTC_ADCUCALK_UCAL_K1_Pos (0UL) /*!< RTC ADCUCALK: UCAL_K1 (Bit 0) */ +#define RTC_ADCUCALK_UCAL_K1_Msk (0xffffUL) /*!< RTC ADCUCALK: UCAL_K1 (Bitfield-Mask: 0xffff) */ +#define RTC_ADCUCALK_UCAL_K1 RTC_ADCUCALK_UCAL_K1_Msk +/* ======================================================= ADCMACTL ======================================================== */ +#define RTC_ADCMACTL_ADCSREF_CAL_Pos (24UL) /*!< RTC ADCMACTL: ADCSREF_CAL (Bit 24) */ +#define RTC_ADCMACTL_ADCSREF_CAL_Msk (0x7000000UL) /*!< RTC ADCMACTL: ADCSREF_CAL (Bitfield-Mask: 0x07) */ +#define RTC_ADCMACTL_ADCSREF_CAL RTC_ADCMACTL_ADCSREF_CAL_Msk +#define RTC_ADCMACTL_SKIP_SAMPLE_Pos (20UL) /*!< RTC ADCMACTL: SKIP_SAMPLE (Bit 20) */ +#define RTC_ADCMACTL_SKIP_SAMPLE_Msk (0xf00000UL) /*!< RTC ADCMACTL: SKIP_SAMPLE (Bitfield-Mask: 0x0f) */ +#define RTC_ADCMACTL_SKIP_SAMPLE RTC_ADCMACTL_SKIP_SAMPLE_Msk +#define RTC_ADCMACTL_AVERAGE_SAMPLE_Pos (16UL) /*!< RTC ADCMACTL: AVERAGE_SAMPLE (Bit 16) */ +#define RTC_ADCMACTL_AVERAGE_SAMPLE_Msk (0x70000UL) /*!< RTC ADCMACTL: AVERAGE_SAMPLE (Bitfield-Mask: 0x07) */ +#define RTC_ADCMACTL_AVERAGE_SAMPLE RTC_ADCMACTL_AVERAGE_SAMPLE_Msk +#define RTC_ADCMACTL_AVERAGE_CHx_Pos (0UL) /*!< RTC ADCMACTL: AVERAGE_CHx (Bit 0) */ +#define RTC_ADCMACTL_AVERAGE_CHx_Msk (0xffffUL) /*!< RTC ADCMACTL: AVERAGE_CHx (Bitfield-Mask: 0xffff) */ +#define RTC_ADCMACTL_AVERAGE_CHx RTC_ADCMACTL_AVERAGE_CHx_Msk +/* ======================================================= ADCDTCTL ======================================================== */ +#define RTC_ADCDTCTL_ENDED_IN2ADC_CONVERT_Pos (30UL) /*!< RTC ADCDTCTL: ENDED_IN2ADC_CONVERT (Bit 30) */ +#define RTC_ADCDTCTL_ENDED_IN2ADC_CONVERT_Msk (0xc0000000UL) /*!< RTC ADCDTCTL: ENDED_IN2ADC_CONVERT (Bitfield-Mask: 0x03) */ +#define RTC_ADCDTCTL_ENDED_IN2ADC_CONVERT RTC_ADCDTCTL_ENDED_IN2ADC_CONVERT_Msk + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define SPI_CTRL_EN_Pos (15UL) /*!< SPI CTRL: EN (Bit 15) */ +#define SPI_CTRL_EN_Msk (0x8000UL) /*!< SPI CTRL: EN (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_EN SPI_CTRL_EN_Msk +#define SPI_CTRL_LSBF_Pos (12UL) /*!< SPI CTRL: LSBF (Bit 12) */ +#define SPI_CTRL_LSBF_Msk (0x1000UL) /*!< SPI CTRL: LSBF (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_LSBF SPI_CTRL_LSBF_Msk +#define SPI_CTRL_RST_Pos (11UL) /*!< SPI CTRL: RST (Bit 11) */ +#define SPI_CTRL_RST_Msk (0x800UL) /*!< SPI CTRL: RST (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_RST SPI_CTRL_RST_Msk +#define SPI_CTRL_CSGPIO_Pos (10UL) /*!< SPI CTRL: CSGPIO (Bit 10) */ +#define SPI_CTRL_CSGPIO_Msk (0x400UL) /*!< SPI CTRL: CSGPIO (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_CSGPIO SPI_CTRL_CSGPIO_Msk +#define SPI_CTRL_SWAP_Pos (9UL) /*!< SPI CTRL: SWAP (Bit 9) */ +#define SPI_CTRL_SWAP_Msk (0x200UL) /*!< SPI CTRL: SWAP (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_SWAP SPI_CTRL_SWAP_Msk +#define SPI_CTRL_MOD_Pos (8UL) /*!< SPI CTRL: MOD (Bit 8) */ +#define SPI_CTRL_MOD_Msk (0x100UL) /*!< SPI CTRL: MOD (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_MOD SPI_CTRL_MOD_Msk +#define SPI_CTRL_SCKPHA_Pos (5UL) /*!< SPI CTRL: SCKPHA (Bit 5) */ +#define SPI_CTRL_SCKPHA_Msk (0x20UL) /*!< SPI CTRL: SCKPHA (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_SCKPHA SPI_CTRL_SCKPHA_Msk +#define SPI_CTRL_SCKPOL_Pos (4UL) /*!< SPI CTRL: SCKPOL (Bit 4) */ +#define SPI_CTRL_SCKPOL_Msk (0x10UL) /*!< SPI CTRL: SCKPOL (Bitfield-Mask: 0x01) */ +#define SPI_CTRL_SCKPOL SPI_CTRL_SCKPOL_Msk +#define SPI_CTRL_SCKSEL_Pos (0UL) /*!< SPI CTRL: SCKSEL (Bit 0) */ +#define SPI_CTRL_SCKSEL_Msk (0x7UL) /*!< SPI CTRL: SCKSEL (Bitfield-Mask: 0x07) */ +#define SPI_CTRL_SCKSEL SPI_CTRL_SCKSEL_Msk +/* ========================================================= TXSTS ========================================================= */ +#define SPI_TXSTS_TXIF_Pos (15UL) /*!< SPI TXSTS: TXIF (Bit 15) */ +#define SPI_TXSTS_TXIF_Msk (0x8000UL) /*!< SPI TXSTS: TXIF (Bitfield-Mask: 0x01) */ +#define SPI_TXSTS_TXIF SPI_TXSTS_TXIF_Msk +#define SPI_TXSTS_TXIEN_Pos (14UL) /*!< SPI TXSTS: TXIEN (Bit 14) */ +#define SPI_TXSTS_TXIEN_Msk (0x4000UL) /*!< SPI TXSTS: TXIEN (Bitfield-Mask: 0x01) */ +#define SPI_TXSTS_TXIEN SPI_TXSTS_TXIEN_Msk +#define SPI_TXSTS_TXEMPTY_Pos (9UL) /*!< SPI TXSTS: TXEMPTY (Bit 9) */ +#define SPI_TXSTS_TXEMPTY_Msk (0x200UL) /*!< SPI TXSTS: TXEMPTY (Bitfield-Mask: 0x01) */ +#define SPI_TXSTS_TXEMPTY SPI_TXSTS_TXEMPTY_Msk +#define SPI_TXSTS_TXFUR_Pos (8UL) /*!< SPI TXSTS: TXFUR (Bit 8) */ +#define SPI_TXSTS_TXFUR_Msk (0x100UL) /*!< SPI TXSTS: TXFUR (Bitfield-Mask: 0x01) */ +#define SPI_TXSTS_TXFUR SPI_TXSTS_TXFUR_Msk +#define SPI_TXSTS_TXFLEV_Pos (4UL) /*!< SPI TXSTS: TXFLEV (Bit 4) */ +#define SPI_TXSTS_TXFLEV_Msk (0x70UL) /*!< SPI TXSTS: TXFLEV (Bitfield-Mask: 0x07) */ +#define SPI_TXSTS_TXFLEV SPI_TXSTS_TXFLEV_Msk +#define SPI_TXSTS_DMATXDONE_Pos (3UL) /*!< SPI TXSTS: DMATXDONE (Bit 3) */ +#define SPI_TXSTS_DMATXDONE_Msk (0x8UL) /*!< SPI TXSTS: DMATXDONE (Bitfield-Mask: 0x01) */ +#define SPI_TXSTS_DMATXDONE SPI_TXSTS_DMATXDONE_Msk +#define SPI_TXSTS_TXFFLAG_Pos (0UL) /*!< SPI TXSTS: TXFFLAG (Bit 0) */ +#define SPI_TXSTS_TXFFLAG_Msk (0x7UL) /*!< SPI TXSTS: TXFFLAG (Bitfield-Mask: 0x07) */ +#define SPI_TXSTS_TXFFLAG SPI_TXSTS_TXFFLAG_Msk +/* ========================================================= TXDAT ========================================================= */ +#define SPI_TXDAT_TXD_Pos (0UL) /*!< SPI TXDAT: TXD (Bit 0) */ +#define SPI_TXDAT_TXD_Msk (0xffUL) /*!< SPI TXDAT: TXD (Bitfield-Mask: 0xff) */ +#define SPI_TXDAT_TXD SPI_TXDAT_TXD_Msk +/* ========================================================= RXSTS ========================================================= */ +#define SPI_RXSTS_RXIF_Pos (15UL) /*!< SPI RXSTS: RXIF (Bit 15) */ +#define SPI_RXSTS_RXIF_Msk (0x8000UL) /*!< SPI RXSTS: RXIF (Bitfield-Mask: 0x01) */ +#define SPI_RXSTS_RXIF SPI_RXSTS_RXIF_Msk +#define SPI_RXSTS_RXIEN_Pos (14UL) /*!< SPI RXSTS: RXIEN (Bit 14) */ +#define SPI_RXSTS_RXIEN_Msk (0x4000UL) /*!< SPI RXSTS: RXIEN (Bitfield-Mask: 0x01) */ +#define SPI_RXSTS_RXIEN SPI_RXSTS_RXIEN_Msk +#define SPI_RXSTS_RXFULL_Pos (9UL) /*!< SPI RXSTS: RXFULL (Bit 9) */ +#define SPI_RXSTS_RXFULL_Msk (0x200UL) /*!< SPI RXSTS: RXFULL (Bitfield-Mask: 0x01) */ +#define SPI_RXSTS_RXFULL SPI_RXSTS_RXFULL_Msk +#define SPI_RXSTS_RXFOV_Pos (8UL) /*!< SPI RXSTS: RXFOV (Bit 8) */ +#define SPI_RXSTS_RXFOV_Msk (0x100UL) /*!< SPI RXSTS: RXFOV (Bitfield-Mask: 0x01) */ +#define SPI_RXSTS_RXFOV SPI_RXSTS_RXFOV_Msk +#define SPI_RXSTS_RXFLEV_Pos (4UL) /*!< SPI RXSTS: RXFLEV (Bit 4) */ +#define SPI_RXSTS_RXFLEV_Msk (0x70UL) /*!< SPI RXSTS: RXFLEV (Bitfield-Mask: 0x07) */ +#define SPI_RXSTS_RXFLEV SPI_RXSTS_RXFLEV_Msk +#define SPI_RXSTS_RXFFLAG_Pos (0UL) /*!< SPI RXSTS: RXFFLAG (Bit 0) */ +#define SPI_RXSTS_RXFFLAG_Msk (0x7UL) /*!< SPI RXSTS: RXFFLAG (Bitfield-Mask: 0x07) */ +#define SPI_RXSTS_RXFFLAG SPI_RXSTS_RXFFLAG_Msk +/* ========================================================= RXDAT ========================================================= */ +#define SPI_RXDAT_RXD_Pos (0UL) /*!< SPI RXDAT: RXD (Bit 0) */ +#define SPI_RXDAT_RXD_Msk (0xffUL) /*!< SPI RXDAT: RXD (Bitfield-Mask: 0xff) */ +#define SPI_RXDAT_RXD SPI_RXDAT_RXD_Msk +/* ========================================================= MISC ========================================================== */ +#define SPI_MISC_OVER_Pos (9UL) /*!< SPI MISC: OVER (Bit 9) */ +#define SPI_MISC_OVER_Msk (0x200UL) /*!< SPI MISC: OVER (Bitfield-Mask: 0x01) */ +#define SPI_MISC_OVER SPI_MISC_OVER_Msk +#define SPI_MISC_SMART_Pos (8UL) /*!< SPI MISC: SMART (Bit 8) */ +#define SPI_MISC_SMART_Msk (0x100UL) /*!< SPI MISC: SMART (Bitfield-Mask: 0x01) */ +#define SPI_MISC_SMART SPI_MISC_SMART_Msk +#define SPI_MISC_BSY_Pos (4UL) /*!< SPI MISC: BSY (Bit 4) */ +#define SPI_MISC_BSY_Msk (0x10UL) /*!< SPI MISC: BSY (Bitfield-Mask: 0x01) */ +#define SPI_MISC_BSY SPI_MISC_BSY_Msk +#define SPI_MISC_RFF_Pos (3UL) /*!< SPI MISC: RFF (Bit 3) */ +#define SPI_MISC_RFF_Msk (0x8UL) /*!< SPI MISC: RFF (Bitfield-Mask: 0x01) */ +#define SPI_MISC_RFF SPI_MISC_RFF_Msk +#define SPI_MISC_RNE_Pos (2UL) /*!< SPI MISC: RNE (Bit 2) */ +#define SPI_MISC_RNE_Msk (0x4UL) /*!< SPI MISC: RNE (Bitfield-Mask: 0x01) */ +#define SPI_MISC_RNE SPI_MISC_RNE_Msk +#define SPI_MISC_TNF_Pos (1UL) /*!< SPI MISC: TNF (Bit 1) */ +#define SPI_MISC_TNF_Msk (0x2UL) /*!< SPI MISC: TNF (Bitfield-Mask: 0x01) */ +#define SPI_MISC_TNF SPI_MISC_TNF_Msk +#define SPI_MISC_TFE_Pos (0UL) /*!< SPI MISC: TFE (Bit 0) */ +#define SPI_MISC_TFE_Msk (0x1UL) /*!< SPI MISC: TFE (Bitfield-Mask: 0x01) */ +#define SPI_MISC_TFE SPI_MISC_TFE_Msk + + +/* =========================================================================================================================== */ +/* ================ TMR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define TMR_CTRL_INTEN_Pos (3UL) /*!< TMR CTRL: INTEN (Bit 3) */ +#define TMR_CTRL_INTEN_Msk (0x8UL) /*!< TMR CTRL: INTEN (Bitfield-Mask: 0x01) */ +#define TMR_CTRL_INTEN TMR_CTRL_INTEN_Msk +#define TMR_CTRL_EXTCLK_Pos (2UL) /*!< TMR CTRL: EXTCLK (Bit 2) */ +#define TMR_CTRL_EXTCLK_Msk (0x4UL) /*!< TMR CTRL: EXTCLK (Bitfield-Mask: 0x01) */ +#define TMR_CTRL_EXTCLK TMR_CTRL_EXTCLK_Msk +#define TMR_CTRL_EXTEN_Pos (1UL) /*!< TMR CTRL: EXTEN (Bit 1) */ +#define TMR_CTRL_EXTEN_Msk (0x2UL) /*!< TMR CTRL: EXTEN (Bitfield-Mask: 0x01) */ +#define TMR_CTRL_EXTEN TMR_CTRL_EXTEN_Msk +#define TMR_CTRL_EN_Pos (0UL) /*!< TMR CTRL: EN (Bit 0) */ +#define TMR_CTRL_EN_Msk (0x1UL) /*!< TMR CTRL: EN (Bitfield-Mask: 0x01) */ +#define TMR_CTRL_EN TMR_CTRL_EN_Msk +/* ========================================================= VALUE ========================================================= */ +#define TMR_VALUE_VALUE_Pos (0UL) /*!< TMR VALUE: VALUE (Bit 0) */ +#define TMR_VALUE_VALUE_Msk (0xffffffffUL) /*!< TMR VALUE: VALUE (Bitfield-Mask: 0xffffffff) */ +#define TMR_VALUE_VALUE TMR_VALUE_VALUE_Msk +/* ======================================================== RELOAD ========================================================= */ +#define TMR_RELOAD_RELOAD_Pos (0UL) /*!< TMR RELOAD: RELOAD (Bit 0) */ +#define TMR_RELOAD_RELOAD_Msk (0xffffffffUL) /*!< TMR RELOAD: RELOAD (Bitfield-Mask: 0xffffffff) */ +#define TMR_RELOAD_RELOAD TMR_RELOAD_RELOAD_Msk +/* ======================================================== INTSTS ========================================================= */ +#define TMR_INTSTS_INTSTS_Pos (0UL) /*!< TMR INTSTS: INTSTS (Bit 0) */ +#define TMR_INTSTS_INTSTS_Msk (0x1UL) /*!< TMR INTSTS: INTSTS (Bitfield-Mask: 0x01) */ +#define TMR_INTSTS_INTSTS TMR_INTSTS_INTSTS_Msk + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define UART_DATA_DATA_Pos (0UL) /*!< UART DATA: DATA (Bit 0) */ +#define UART_DATA_DATA_Msk (0xffUL) /*!< UART DATA: DATA (Bitfield-Mask: 0xff) */ +#define UART_DATA_DATA UART_DATA_DATA_Msk +/* ========================================================= STATE ========================================================= */ +#define UART_STATE_DMATXDONE_Pos (7UL) /*!< UART STATE: DMATXDONE (Bit 7) */ +#define UART_STATE_DMATXDONE_Msk (0x80UL) /*!< UART STATE: DMATXDONE (Bitfield-Mask: 0x01) */ +#define UART_STATE_DMATXDONE UART_STATE_DMATXDONE_Msk +#define UART_STATE_RXPSTS_Pos (6UL) /*!< UART STATE: RXPSTS (Bit 6) */ +#define UART_STATE_RXPSTS_Msk (0x40UL) /*!< UART STATE: RXPSTS (Bitfield-Mask: 0x01) */ +#define UART_STATE_RXPSTS UART_STATE_RXPSTS_Msk +#define UART_STATE_TXDONE_Pos (5UL) /*!< UART STATE: TXDONE (Bit 5) */ +#define UART_STATE_TXDONE_Msk (0x20UL) /*!< UART STATE: TXDONE (Bitfield-Mask: 0x01) */ +#define UART_STATE_TXDONE UART_STATE_TXDONE_Msk +#define UART_STATE_RXPE_Pos (4UL) /*!< UART STATE: RXPE (Bit 4) */ +#define UART_STATE_RXPE_Msk (0x10UL) /*!< UART STATE: RXPE (Bitfield-Mask: 0x01) */ +#define UART_STATE_RXPE UART_STATE_RXPE_Msk +#define UART_STATE_RXOV_Pos (3UL) /*!< UART STATE: RXOV (Bit 3) */ +#define UART_STATE_RXOV_Msk (0x8UL) /*!< UART STATE: RXOV (Bitfield-Mask: 0x01) */ +#define UART_STATE_RXOV UART_STATE_RXOV_Msk +#define UART_STATE_TXOV_Pos (2UL) /*!< UART STATE: TXOV (Bit 2) */ +#define UART_STATE_TXOV_Msk (0x4UL) /*!< UART STATE: TXOV (Bitfield-Mask: 0x01) */ +#define UART_STATE_TXOV UART_STATE_TXOV_Msk +#define UART_STATE_RXFULL_Pos (1UL) /*!< UART STATE: RXFULL (Bit 1) */ +#define UART_STATE_RXFULL_Msk (0x2UL) /*!< UART STATE: RXFULL (Bitfield-Mask: 0x01) */ +#define UART_STATE_RXFULL UART_STATE_RXFULL_Msk +/* ========================================================= CTRL ========================================================== */ +#define UART_CTRL_TXDONEIE_Pos (8UL) /*!< UART CTRL: TXDONEIE (Bit 8) */ +#define UART_CTRL_TXDONEIE_Msk (0x100UL) /*!< UART CTRL: TXDONEIE (Bitfield-Mask: 0x01) */ +#define UART_CTRL_TXDONEIE UART_CTRL_TXDONEIE_Msk +#define UART_CTRL_RXPEIE_Pos (7UL) /*!< UART CTRL: RXPEIE (Bit 7) */ +#define UART_CTRL_RXPEIE_Msk (0x80UL) /*!< UART CTRL: RXPEIE (Bitfield-Mask: 0x01) */ +#define UART_CTRL_RXPEIE UART_CTRL_RXPEIE_Msk +#define UART_CTRL_RXOVIE_Pos (5UL) /*!< UART CTRL: RXOVIE (Bit 5) */ +#define UART_CTRL_RXOVIE_Msk (0x20UL) /*!< UART CTRL: RXOVIE (Bitfield-Mask: 0x01) */ +#define UART_CTRL_RXOVIE UART_CTRL_RXOVIE_Msk +#define UART_CTRL_TXOVIE_Pos (4UL) /*!< UART CTRL: TXOVIE (Bit 4) */ +#define UART_CTRL_TXOVIE_Msk (0x10UL) /*!< UART CTRL: TXOVIE (Bitfield-Mask: 0x01) */ +#define UART_CTRL_TXOVIE UART_CTRL_TXOVIE_Msk +#define UART_CTRL_RXIE_Pos (3UL) /*!< UART CTRL: RXIE (Bit 3) */ +#define UART_CTRL_RXIE_Msk (0x8UL) /*!< UART CTRL: RXIE (Bitfield-Mask: 0x01) */ +#define UART_CTRL_RXIE UART_CTRL_RXIE_Msk +#define UART_CTRL_RXEN_Pos (1UL) /*!< UART CTRL: RXEN (Bit 1) */ +#define UART_CTRL_RXEN_Msk (0x2UL) /*!< UART CTRL: RXEN (Bitfield-Mask: 0x01) */ +#define UART_CTRL_RXEN UART_CTRL_RXEN_Msk +#define UART_CTRL_TXEN_Pos (0UL) /*!< UART CTRL: TXEN (Bit 0) */ +#define UART_CTRL_TXEN_Msk (0x1UL) /*!< UART CTRL: TXEN (Bitfield-Mask: 0x01) */ +#define UART_CTRL_TXEN UART_CTRL_TXEN_Msk +/* ======================================================== INTSTS ========================================================= */ +#define UART_INTSTS_TXDONEIF_Pos (5UL) /*!< UART INTSTS: TXDONEIF (Bit 5) */ +#define UART_INTSTS_TXDONEIF_Msk (0x20UL) /*!< UART INTSTS: TXDONEIF (Bitfield-Mask: 0x01) */ +#define UART_INTSTS_TXDONEIF UART_INTSTS_TXDONEIF_Msk +#define UART_INTSTS_RXPEIF_Pos (4UL) /*!< UART INTSTS: RXPEIF (Bit 4) */ +#define UART_INTSTS_RXPEIF_Msk (0x10UL) /*!< UART INTSTS: RXPEIF (Bitfield-Mask: 0x01) */ +#define UART_INTSTS_RXPEIF UART_INTSTS_RXPEIF_Msk +#define UART_INTSTS_RXOVIF_Pos (3UL) /*!< UART INTSTS: RXOVIF (Bit 3) */ +#define UART_INTSTS_RXOVIF_Msk (0x8UL) /*!< UART INTSTS: RXOVIF (Bitfield-Mask: 0x01) */ +#define UART_INTSTS_RXOVIF UART_INTSTS_RXOVIF_Msk +#define UART_INTSTS_TXOVIF_Pos (2UL) /*!< UART INTSTS: TXOVIF (Bit 2) */ +#define UART_INTSTS_TXOVIF_Msk (0x4UL) /*!< UART INTSTS: TXOVIF (Bitfield-Mask: 0x01) */ +#define UART_INTSTS_TXOVIF UART_INTSTS_TXOVIF_Msk +#define UART_INTSTS_RXIF_Pos (1UL) /*!< UART INTSTS: RXIF (Bit 1) */ +#define UART_INTSTS_RXIF_Msk (0x2UL) /*!< UART INTSTS: RXIF (Bitfield-Mask: 0x01) */ +#define UART_INTSTS_RXIF UART_INTSTS_RXIF_Msk +/* ======================================================== BAUDDIV ======================================================== */ +#define UART_BAUDDIV_BAUDDIV_Pos (0UL) /*!< UART BAUDDIV: BAUDDIV (Bit 0) */ +#define UART_BAUDDIV_BAUDDIV_Msk (0xfffffUL) /*!< UART BAUDDIV: BAUDDIV (Bitfield-Mask: 0xfffff) */ +#define UART_BAUDDIV_BAUDDIV UART_BAUDDIV_BAUDDIV_Msk +/* ========================================================= CTRL2 ========================================================= */ +#define UART_CTRL2_PMODE_Pos (1UL) /*!< UART CTRL2: PMODE (Bit 1) */ +#define UART_CTRL2_PMODE_Msk (0xeUL) /*!< UART CTRL2: PMODE (Bitfield-Mask: 0x07) */ +#define UART_CTRL2_PMODE UART_CTRL2_PMODE_Msk +#define UART_CTRL2_MSB_Pos (0UL) /*!< UART CTRL2: MSB (Bit 0) */ +#define UART_CTRL2_MSB_Msk (0x1UL) /*!< UART CTRL2: MSB (Bitfield-Mask: 0x01) */ +#define UART_CTRL2_MSB UART_CTRL2_MSB_Msk + + +/* =========================================================================================================================== */ +/* ================ U32K ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL0 ========================================================= */ +#define U32K_CTRL0_WKUMODE_Pos (8UL) /*!< U32K CTRL0: WKUMODE (Bit 8) */ +#define U32K_CTRL0_WKUMODE_Msk (0x100UL) /*!< U32K CTRL0: WKUMODE (Bitfield-Mask: 0x01) */ +#define U32K_CTRL0_WKUMODE U32K_CTRL0_WKUMODE_Msk +#define U32K_CTRL0_DEBSEL_Pos (6UL) /*!< U32K CTRL0: DEBSEL (Bit 6) */ +#define U32K_CTRL0_DEBSEL_Msk (0xc0UL) /*!< U32K CTRL0: DEBSEL (Bitfield-Mask: 0x03) */ +#define U32K_CTRL0_DEBSEL U32K_CTRL0_DEBSEL_Msk +#define U32K_CTRL0_PMODE_Pos (3UL) /*!< U32K CTRL0: PMODE (Bit 3) */ +#define U32K_CTRL0_PMODE_Msk (0x38UL) /*!< U32K CTRL0: PMODE (Bitfield-Mask: 0x07) */ +#define U32K_CTRL0_PMODE U32K_CTRL0_PMODE_Msk +#define U32K_CTRL0_MSB_Pos (2UL) /*!< U32K CTRL0: MSB (Bit 2) */ +#define U32K_CTRL0_MSB_Msk (0x4UL) /*!< U32K CTRL0: MSB (Bitfield-Mask: 0x01) */ +#define U32K_CTRL0_MSB U32K_CTRL0_MSB_Msk +#define U32K_CTRL0_ACOFF_Pos (1UL) /*!< U32K CTRL0: ACOFF (Bit 1) */ +#define U32K_CTRL0_ACOFF_Msk (0x2UL) /*!< U32K CTRL0: ACOFF (Bitfield-Mask: 0x01) */ +#define U32K_CTRL0_ACOFF U32K_CTRL0_ACOFF_Msk +#define U32K_CTRL0_EN_Pos (0UL) /*!< U32K CTRL0: EN (Bit 0) */ +#define U32K_CTRL0_EN_Msk (0x1UL) /*!< U32K CTRL0: EN (Bitfield-Mask: 0x01) */ +#define U32K_CTRL0_EN U32K_CTRL0_EN_Msk +/* ========================================================= CTRL1 ========================================================= */ +#define U32K_CTRL1_RXSEL_Pos (4UL) /*!< U32K CTRL1: RXSEL (Bit 4) */ +#define U32K_CTRL1_RXSEL_Msk (0x30UL) /*!< U32K CTRL1: RXSEL (Bitfield-Mask: 0x03) */ +#define U32K_CTRL1_RXSEL U32K_CTRL1_RXSEL_Msk +#define U32K_CTRL1_RXOVIE_Pos (2UL) /*!< U32K CTRL1: RXOVIE (Bit 2) */ +#define U32K_CTRL1_RXOVIE_Msk (0x4UL) /*!< U32K CTRL1: RXOVIE (Bitfield-Mask: 0x01) */ +#define U32K_CTRL1_RXOVIE U32K_CTRL1_RXOVIE_Msk +#define U32K_CTRL1_RXPEIE_Pos (1UL) /*!< U32K CTRL1: RXPEIE (Bit 1) */ +#define U32K_CTRL1_RXPEIE_Msk (0x2UL) /*!< U32K CTRL1: RXPEIE (Bitfield-Mask: 0x01) */ +#define U32K_CTRL1_RXPEIE U32K_CTRL1_RXPEIE_Msk +#define U32K_CTRL1_RXIE_Pos (0UL) /*!< U32K CTRL1: RXIE (Bit 0) */ +#define U32K_CTRL1_RXIE_Msk (0x1UL) /*!< U32K CTRL1: RXIE (Bitfield-Mask: 0x01) */ +#define U32K_CTRL1_RXIE U32K_CTRL1_RXIE_Msk +/* ======================================================== BAUDDIV ======================================================== */ +#define U32K_BAUDDIV_BAUDDIV_Pos (0UL) /*!< U32K BAUDDIV: BAUDDIV (Bit 0) */ +#define U32K_BAUDDIV_BAUDDIV_Msk (0xffffUL) /*!< U32K BAUDDIV: BAUDDIV (Bitfield-Mask: 0xffff) */ +#define U32K_BAUDDIV_BAUDDIV U32K_BAUDDIV_BAUDDIV_Msk +/* ========================================================= DATA ========================================================== */ +#define U32K_DATA_DATA_Pos (0UL) /*!< U32K DATA: DATA (Bit 0) */ +#define U32K_DATA_DATA_Msk (0xffUL) /*!< U32K DATA: DATA (Bitfield-Mask: 0xff) */ +#define U32K_DATA_DATA U32K_DATA_DATA_Msk +/* ========================================================== STS ========================================================== */ +#define U32K_STS_RXOV_Pos (2UL) /*!< U32K STS: RXOV (Bit 2) */ +#define U32K_STS_RXOV_Msk (0x4UL) /*!< U32K STS: RXOV (Bitfield-Mask: 0x01) */ +#define U32K_STS_RXOV U32K_STS_RXOV_Msk +#define U32K_STS_RXPE_Pos (1UL) /*!< U32K STS: RXPE (Bit 1) */ +#define U32K_STS_RXPE_Msk (0x2UL) /*!< U32K STS: RXPE (Bitfield-Mask: 0x01) */ +#define U32K_STS_RXPE U32K_STS_RXPE_Msk +#define U32K_STS_RXIF_Pos (0UL) /*!< U32K STS: RXIF (Bit 0) */ +#define U32K_STS_RXIF_Msk (0x1UL) /*!< U32K STS: RXIF (Bitfield-Mask: 0x01) */ +#define U32K_STS_RXIF U32K_STS_RXIF_Msk + +/** @} */ /* End of group PosMask_peripherals */ +#include "system_target.h" /*!< target System */ + + +#ifdef __cplusplus +} +#endif + +#endif /* TARGET_H */ + + +/** @} */ /* End of group target */ + +/** @} */ /* End of group Vango */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/type_def.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/type_def.h new file mode 100644 index 0000000000..eea44ff4e6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/CMSIS/include/type_def.h @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file type_def.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Typedef file + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __TYPE_DEF_H +#define __TYPE_DEF_H + +#define ENABLE 1 +#define DISABLE 0 +#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE)) + +#define BIT_BAND(addr, bitnum) *((volatile unsigned long *)((((uint32_t)addr) & 0xF0000000) + \ + 0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2))) + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/*---------- EWARM ----------*/ +#ifdef __ICCARM__ + #define __RAM_FUNC __ramfunc + #define __IN_RAMSECTION + + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ + + #define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +/*---------- MDK-ARM ----------*/ +#ifdef __CC_ARM + #define __RAM_FUNC __attribute__((used)) + #define __IN_RAMSECTION + + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __align(4) + #endif /* __ALIGN_BEGIN */ + + #define __NOINLINE __attribute__ ( (noinline) ) + +#endif + +/*---------- GCC ----------*/ +#ifdef __GNUC__ + #define __RAM_FUNC + #define __IN_RAMSECTION __attribute__((section(".ram_exec"))) + + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ + + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ + + #define __NOINLINE __attribute__ ( (noinline) ) + +#endif + + + + + +#endif /* __TYPE_DEF_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/startup_target_noload.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/startup_target_noload.S new file mode 100644 index 0000000000..8907a4889b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/ECLIPSE/startup_target_noload.S @@ -0,0 +1,477 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.0.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 0 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/startup_target.s new file mode 100644 index 0000000000..9591a3eb22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 1 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/startup_target_noload.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/startup_target_noload.s new file mode 100644 index 0000000000..cc2b6afbae --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/startup_target_noload.s @@ -0,0 +1,499 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 0 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARM/startup_target_noload.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARM/startup_target_noload.s new file mode 100644 index 0000000000..c0dfe70792 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARM/startup_target_noload.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 0 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARMv4/startup_target_noload.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARMv4/startup_target_noload.s new file mode 100644 index 0000000000..7f30d1f481 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Config/MDK-ARMv4/startup_target_noload.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 0 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_adc.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_adc.h new file mode 100644 index 0000000000..ed2aea1469 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_adc.h @@ -0,0 +1,313 @@ +/** + ****************************************************************************** + * @file lib_adc.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief ADC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ADC_H +#define __LIB_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Mode; + uint32_t ClockSource; + uint32_t ClockFrq; + uint32_t SkipSample; + uint32_t AverageSample; + uint32_t TriggerSource; + uint32_t Channel; + uint32_t ResDivEnable; + uint32_t AverageEnable; +} ADC_InitType; + +typedef struct +{ + uint32_t THDChannel; + uint8_t UpperTHD; + uint8_t LowerTHD; + uint32_t TriggerSel; + uint32_t THDSource; +} ADCTHD_InitType; + +/* Exported constants --------------------------------------------------------*/ + + +//Mode +#define ADC_MODE_DC (0UL) +#define ADC_MODE_AC (1UL) +#define ADC_MODE_TEMP (2UL) +#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_DC) ||\ + ((__MODE__) == ADC_MODE_AC) ||\ + ((__MODE__) == ADC_MODE_TEMP)) +//ClockSource +#define ADC_CLKSRC_RCH (0) +#define ADC_CLKSRC_PLLL ANA_ADCCTRL0_CLKSRCSEL +#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\ + ((__CLKSRC__) == ADC_CLKSRC_PLLL)) +//ClockFrq +#define ADC_CLKFRQ_HIGH (0UL) +#define ADC_CLKFRQ_LOW (1UL) +#define IS_ADC_CLKFRQ(__CLKFRQ__) (((__CLKFRQ__) == ADC_CLKFRQ_HIGH) ||\ + ((__CLKFRQ__) == ADC_CLKFRQ_LOW)) +//SkipSample +#define ADC_SKIP_0 (0x0UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) +#define ADC_SKIP_4 (0x4UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) +#define ADC_SKIP_8 (0x8UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) +#define ADC_SKIP_12 (0xCUL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) +#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_0) ||\ + ((__SKIP__) == ADC_SKIP_4) ||\ + ((__SKIP__) == ADC_SKIP_8) ||\ + ((__SKIP__) == ADC_SKIP_12)) +//AverageSample +#define ADC_AVERAGE_2 (0x0UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) +#define ADC_AVERAGE_4 (0x1UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) +#define ADC_AVERAGE_8 (0x2UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) +#define ADC_AVERAGE_16 (0x3UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) +#define ADC_AVERAGE_32 (0x4UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) +#define ADC_AVERAGE_64 (0x5UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) +#define IS_ADC_AVERAG(__AVERAG__) (((__AVERAG__) == ADC_AVERAGE_2) ||\ + ((__AVERAG__) == ADC_AVERAGE_4) ||\ + ((__AVERAG__) == ADC_AVERAGE_8) ||\ + ((__AVERAG__) == ADC_AVERAGE_16) ||\ + ((__AVERAG__) == ADC_AVERAGE_32) ||\ + ((__AVERAG__) == ADC_AVERAGE_64)) +//TriggerSource +#define ADC_TRIGSOURCE_OFF (0x0UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_ITVSITV (0x1UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_WKUSEC (0x2UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_ALARM (0x3UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_TMR0 (0x4UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_TMR1 (0x5UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_TMR2 (0x6UL << ANA_ADCCTRL0_AEN_Pos) +#define ADC_TRIGSOURCE_TMR3 (0x7UL << ANA_ADCCTRL0_AEN_Pos) +#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_ITVSITV) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_WKUSEC) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_ALARM) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR0) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR1) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR2) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR3)) +//Channel +#define ADC_CHANNEL_NONE (0 << 0UL) +#define ADC_CHANNEL_GND0 (1 << 0UL) +#define ADC_CHANNEL_BAT1 (1 << 1UL) +#define ADC_CHANNEL_BATRTC (1 << 2UL) +#define ADC_CHANNEL_CH3 (1 << 3UL) +#define ADC_CHANNEL_CH4 (1 << 4UL) +#define ADC_CHANNEL_CH5 (1 << 5UL) +#define ADC_CHANNEL_CH6 (1 << 6UL) +#define ADC_CHANNEL_CH7 (1 << 7UL) +#define ADC_CHANNEL_CH8 (1 << 8UL) +#define ADC_CHANNEL_CH9 (1 << 9UL) +#define ADC_CHANNEL_TEMP (1 << 10UL) +#define ADC_CHANNEL_CH11 (1 << 11UL) +#define ADC_CHANNEL_DVCC (1 << 12UL) +#define ADC_CHANNEL_GND13 (1 << 13UL) +#define ADC_CHANNEL_GND14 (1 << 14UL) +#define ADC_CHANNEL_GND15 (1 << 15UL) +#define ADC_CHANNEL_DC_Msk (0xFBFFUL) +#define ADC_CHANNEL_DC_ALL ADC_CHANNEL_DC_Msk +#define ADC_CHANNEL_AC_Msk (0x0BF8UL) +#define ADC_CHANNEL_AC_ALL ADC_CHANNEL_AC_Msk +#define IS_ADC_CHANNEL_GETDATA(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_GND0) ||\ + ((__CHANNEL__) == ADC_CHANNEL_BAT1) ||\ + ((__CHANNEL__) == ADC_CHANNEL_BATRTC) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH3) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH4) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH5) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH6) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH7) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH8) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH9) ||\ + ((__CHANNEL__) == ADC_CHANNEL_TEMP) ||\ + ((__CHANNEL__) == ADC_CHANNEL_CH11) ||\ + ((__CHANNEL__) == ADC_CHANNEL_DVCC) ||\ + ((__CHANNEL__) == ADC_CHANNEL_GND13) ||\ + ((__CHANNEL__) == ADC_CHANNEL_GND14) ||\ + ((__CHANNEL__) == ADC_CHANNEL_GND15)) +#define IS_ADC_CHANNEL_AC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) &&\ + (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL)) +#define IS_ADC_CHANNEL_DC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) &&\ + (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL)) +#define IS_ADC_CHANNEL_TEMP(__CHANNEL__) ((__CHANNEL__) == ADC_CHANNEL_TEMP) +#define IS_ADC_CHANNEL_EN_DC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL)) ||\ + ((__CHANNEL__) == ADC_CHANNEL_NONE)) +#define IS_ADC_CHANNEL_EN_AC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL)) ||\ + ((__CHANNEL__) == ADC_CHANNEL_NONE)) + +#define ADC_CHANNEL_Pos (0UL) +#define ADC_CHANNEL_SHIFT (ANA_ADCCTRL2_SCAN_CHx_Pos - ADC_CHANNEL_Pos) +#define ADC_AVERAGECH_SHIFT (RTC_ADCMACTL_AVERAGE_CHx_Pos - ADC_CHANNEL_Pos) +#define ADC_RESDIVCH_SHIFT (ANA_ADCCTRL1_RESDIV_CHx_Pos - ADC_CHANNEL_Pos) + +//THDChannel +#define ADC_THDCHANNEL0 (0UL) +#define ADC_THDCHANNEL1 (1UL) +#define ADC_THDCHANNEL2 (2UL) +#define ADC_THDCHANNEL3 (3UL) +#define IS_ADC_THDCHANNEL(THDCHANNEL) (((THDCHANNEL) == ADC_THDCHANNEL0) ||\ + ((THDCHANNEL) == ADC_THDCHANNEL1) ||\ + ((THDCHANNEL) == ADC_THDCHANNEL2) ||\ + ((THDCHANNEL) == ADC_THDCHANNEL3)) + +//TriggerSel +#define ADC_THDSEL_HIGH (0UL) +#define ADC_THDSEL_RISING (1UL) +#define ADC_THDSEL_FALLING (2UL) +#define ADC_THDSEL_BOTH (3UL) +#define IS_ADC_THDSEL(__THDSEL__) (((__THDSEL__) == ADC_THDSEL_HIGH) ||\ + ((__THDSEL__) == ADC_THDSEL_RISING) ||\ + ((__THDSEL__) == ADC_THDSEL_FALLING) ||\ + ((__THDSEL__) == ADC_THDSEL_BOTH)) + +//INTMask +#define ADC_INT_UPPER_TH3 ANA_INTEN_INTEN21 +#define ADC_INT_LOWER_TH3 ANA_INTEN_INTEN20 +#define ADC_INT_UPPER_TH2 ANA_INTEN_INTEN19 +#define ADC_INT_LOWER_TH2 ANA_INTEN_INTEN18 +#define ADC_INT_UPPER_TH1 ANA_INTEN_INTEN17 +#define ADC_INT_LOWER_TH1 ANA_INTEN_INTEN16 +#define ADC_INT_UPPER_TH0 ANA_INTEN_INTEN15 +#define ADC_INT_LOWER_TH0 ANA_INTEN_INTEN14 +#define ADC_INT_AUTODONE ANA_INTEN_INTEN1 +#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0 +#define ADC_INT_Msk (0x3FC003UL) +#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0UL) &&\ + (((__INT__) & ~ADC_INT_Msk) == 0UL)) + +//INTSTS +#define ADC_INTSTS_UPPER_TH3 ANA_INTSTS_INTSTS21 +#define ADC_INTSTS_LOWER_TH3 ANA_INTSTS_INTSTS20 +#define ADC_INTSTS_UPPER_TH2 ANA_INTSTS_INTSTS19 +#define ADC_INTSTS_LOWER_TH2 ANA_INTSTS_INTSTS18 +#define ADC_INTSTS_UPPER_TH1 ANA_INTSTS_INTSTS17 +#define ADC_INTSTS_LOWER_TH1 ANA_INTSTS_INTSTS16 +#define ADC_INTSTS_UPPER_TH0 ANA_INTSTS_INTSTS15 +#define ADC_INTSTS_LOWER_TH0 ANA_INTSTS_INTSTS14 +#define ADC_INTSTS_AUTODONE ANA_INTSTS_INTSTS1 +#define ADC_INTSTS_MANUALDONE ANA_INTSTS_INTSTS0 +#define ADC_INTSTS_Msk (0x3FC003UL) +#define IS_ADC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & ADC_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~ADC_INTSTS_Msk) == 0U)) + +#define IS_ADC_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == ADC_INTSTS_UPPER_TH3) ||\ + ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH3) ||\ + ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH2) ||\ + ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH2) ||\ + ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH1) ||\ + ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH1) ||\ + ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH0) ||\ + ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH0) ||\ + ((__INTFLAGR__) == ADC_INTSTS_AUTODONE) ||\ + ((__INTFLAGR__) == ADC_INTSTS_MANUALDONE)) + +#define ADC_FLAG_CONV_ERR (0x1U << ANA_ADCCTRL2_CONV_ERR_Pos) +#define ADC_FLAG_CAL_ERR (0x1U << ANA_ADCCTRL2_CAL_ERR_Pos) +#define ADC_FLAG_CAL_DONE (0x1U << ANA_ADCCTRL2_ADC_CAL_DONE_Pos) +#define ADC_FLAG_BUSY (0x1U << ANA_ADCCTRL2_BUSY_Pos) +#define IS_ADC_ADCFLAG(__ADCFLAG__) (((__ADCFLAG__) == ADC_FLAG_CONV_ERR) ||\ + ((__ADCFLAG__) == ADC_FLAG_CAL_ERR) ||\ + ((__ADCFLAG__) == ADC_FLAG_CAL_DONE) ||\ + ((__ADCFLAG__) == ADC_FLAG_BUSY)) + +#define ADC_FLAG_RCMsk (ADC_FLAG_CONV_ERR|ADC_FLAG_CAL_ERR) +#define IS_ADC_ADCFLAGC(__ADCFLAG__) ((((__ADCFLAG__) & ADC_FLAG_RCMsk) != 0U) &&\ + (((__ADCFLAG__) & ~ADC_FLAG_RCMsk) == 0U)) + +//THDFlag +#define ADC_THDFLAG_UPPER3 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Pos) +#define ADC_THDFLAG_LOWER3 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Pos) +#define ADC_THDFLAG_UPPER2 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Pos) +#define ADC_THDFLAG_LOWER2 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Pos) +#define ADC_THDFLAG_UPPER1 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Pos) +#define ADC_THDFLAG_LOWER1 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Pos) +#define ADC_THDFLAG_UPPER0 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Pos) +#define ADC_THDFLAG_LOWER0 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Pos) +#define IS_ADC_THDFLAG(__THDFLAG__) (((__THDFLAG__) == ADC_THDFLAG_UPPER3) ||\ + ((__THDFLAG__) == ADC_THDFLAG_LOWER3) ||\ + ((__THDFLAG__) == ADC_THDFLAG_UPPER2) ||\ + ((__THDFLAG__) == ADC_THDFLAG_LOWER2) ||\ + ((__THDFLAG__) == ADC_THDFLAG_UPPER1) ||\ + ((__THDFLAG__) == ADC_THDFLAG_LOWER1) ||\ + ((__THDFLAG__) == ADC_THDFLAG_UPPER0) ||\ + ((__THDFLAG__) == ADC_THDFLAG_LOWER0)) + +#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\ + ((__BATDIV__) == ADC_BAT_RESDIV)) + +/* ADC_GetVoltage */ +//Mode +#define ADC_3V_ADCCHx_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None +#define ADC_3V_ADCCHx_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive +#define ADC_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive +#define ADC_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive +#define ADC_5V_ADCCHx_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None +#define ADC_5V_ADCCHx_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive +#define ADC_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive +#define ADC_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive +#define ADC_TEMP (0x1000UL) // Temperature ; Channel: ADC_CHANNEL_TEMP +#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_ADCCHx_NODIV) ||\ + ((__MODE__) == ADC_3V_ADCCHx_RESDIV) ||\ + ((__MODE__) == ADC_3V_BAT1_RESDIV) ||\ + ((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\ + ((__MODE__) == ADC_5V_ADCCHx_NODIV) ||\ + ((__MODE__) == ADC_5V_ADCCHx_RESDIV) ||\ + ((__MODE__) == ADC_5V_BAT1_RESDIV) ||\ + ((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\ + ((__MODE__) == ADC_TEMP)) + +/* Exported Functions ------------------------------------------------------- */ +/* ADC Exported Functions Group1: + (De)Initialization -------------------------*/ +uint32_t ADC_DeInit(void); +void ADC_StructInit(ADC_InitType* ADC_InitStruct); +void ADC_Init(ADC_InitType* ADC_InitStruct); +/* ADC Exported Functions Group2: + ADC Configuration --------------*/ +void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct); +void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct); +void ADC_Calibration(void); +/* ADC Exported Functions Group3: + Get NVR Info, Calculate datas --------------*/ +uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value); +/* ADC Exported Functions Group4: + Interrupt (flag) ---------------------------*/ +int16_t ADC_GetADCConversionValue(uint32_t Channel); +void ADC_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t ADC_GetFlag(uint32_t FlagMask); +void ADC_ClearFlag(uint32_t FlagMask); +uint8_t ADC_GetINTStatus(uint32_t INTMask); +void ADC_ClearINTStatus(uint32_t INTMask); +uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask); + +/* ADC Exported Functions Group5: + MISC Configuration -------------------------*/ +void ADC_Cmd(uint32_t NewState); +void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState); +void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState); +void ADC_StartManual(void); +uint8_t ADC_WaitForManual(uint32_t Timeout); +uint8_t ADC_WaitForAuto(uint32_t Timeout); + +uint8_t ADC_SoftReset(ADC_InitType* ADC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ADC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_adc_tiny.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_adc_tiny.h new file mode 100644 index 0000000000..7988ffb96f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_adc_tiny.h @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file lib_adc_tiny.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief ADC_TINY library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ADC_TINY_H +#define __LIB_ADC_TINY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t SignalSel; + uint32_t ADTREF1; + uint32_t ADTREF2; + uint32_t ADTREF3; +} TADCInitType; + +//SelADT +#define ADCTINY_SIGNALSEL_IOE6 0 +#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_ADTSEL +#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\ + ((__SELADT__) == ADCTINY_SIGNALSEL_IOE7)) + +//ADTREF1 +#define ADCTINY_REF1_0_9 0 +#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL +#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\ + ((__ADTREF1__) == ADCTINY_REF1_0_7)) + +//ADTREF2 +#define ADCTINY_REF2_1_8 0 +#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL +#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\ + ((__ADTREF2__) == ADCTINY_REF2_1_6)) + +//ADTREF3 +#define ADCTINY_REF3_2_7 0 +#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL +#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\ + ((__ADTREF3__) == ADCTINY_REF3_2_5)) + +//THSel +#define ADCTINY_THSEL_0 (0x00UL << ANA_MISC_TADCTH_Pos) +#define ADCTINY_THSEL_1 (0x01UL << ANA_MISC_TADCTH_Pos) +#define ADCTINY_THSEL_2 (0x02UL << ANA_MISC_TADCTH_Pos) +#define ADCTINY_THSEL_3 (0x03UL << ANA_MISC_TADCTH_Pos) +#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\ + ((__THSEL__) == ADCTINY_THSEL_1) ||\ + ((__THSEL__) == ADCTINY_THSEL_2) ||\ + ((__THSEL__) == ADCTINY_THSEL_3)) + +/* Exported Functions ------------------------------------------------------- */ +void TADC_DeInit(void); +void TADC_StructInit(TADCInitType* TADC_InitStruct); +void TADC_Init(TADCInitType* TADC_InitStruct); +void TADC_Cmd(uint32_t NewState); +uint8_t TADC_GetOutput(void); +void TADC_IntTHConfig(uint32_t THSel); +void TADC_INTConfig(uint32_t NewState); +uint8_t TADC_GetINTStatus(void); +void TADC_ClearINTStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ADC_TINY_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_ana.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_ana.h new file mode 100644 index 0000000000..e7ebfac706 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_ana.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file lib_ana.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Analog library. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ +#ifndef __LIB_ANA_H +#define __LIB_ANA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/***** StatusMask (ANA_GetStatus) *****/ +#define ANA_STATUS_AVCCLV ANA_CMPOUT_AVCCLV +#define ANA_STATUS_VDCINDROP ANA_CMPOUT_VDCINDROP +#define ANA_STATUS_VDDALARM ANA_CMPOUT_VDDALARM +#define ANA_STATUS_CMP2 ANA_CMPOUT_CMP2 +#define ANA_STATUS_CMP1 ANA_CMPOUT_CMP1 +#define ANA_STATUS_LOCKL ANA_CMPOUT_LOCKL +#define ANA_STATUS_LOCKH ANA_CMPOUT_LOCKH + +/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/ +#define ANA_INT_UPPER_TH3 ANA_INTEN_INTEN21 +#define ANA_INT_LOWER_TH3 ANA_INTEN_INTEN20 +#define ANA_INT_UPPER_TH2 ANA_INTEN_INTEN19 +#define ANA_INT_LOWER_TH2 ANA_INTEN_INTEN18 +#define ANA_INT_UPPER_TH1 ANA_INTEN_INTEN17 +#define ANA_INT_LOWER_TH1 ANA_INTEN_INTEN16 +#define ANA_INT_UPPER_TH0 ANA_INTEN_INTEN15 +#define ANA_INT_LOWER_TH0 ANA_INTEN_INTEN14 +#define ANA_INT_TADC_OVER ANA_INTEN_INTEN13 +#define ANA_INT_REGERR ANA_INTEN_INTEN12 +#define ANA_INT_SLPFAIL_VDCIN ANA_INTEN_INTEN11 +#define ANA_INT_AVCCLV ANA_INTEN_INTEN10 +#define ANA_INT_VDCINDROP ANA_INTEN_INTEN8 +#define ANA_INT_VDDALARM ANA_INTEN_INTEN7 +#define ANA_INT_CMP2 ANA_INTEN_INTEN3 +#define ANA_INT_CMP1 ANA_INTEN_INTEN2 +#define ANA_INT_ADCA ANA_INTEN_INTEN1 +#define ANA_INT_ADCM ANA_INTEN_INTEN0 +#define ANA_INT_Msk (ANA_INTSTS_INTSTS21 \ + |ANA_INTSTS_INTSTS20 \ + |ANA_INTSTS_INTSTS19 \ + |ANA_INTSTS_INTSTS18 \ + |ANA_INTSTS_INTSTS17 \ + |ANA_INTSTS_INTSTS16 \ + |ANA_INTSTS_INTSTS15 \ + |ANA_INTSTS_INTSTS14 \ + |ANA_INTSTS_INTSTS13 \ + |ANA_INTSTS_INTSTS12 \ + |ANA_INTSTS_INTSTS11 \ + |ANA_INTSTS_INTSTS10 \ + |ANA_INTSTS_INTSTS8 \ + |ANA_INTSTS_INTSTS7 \ + |ANA_INTSTS_INTSTS3 \ + |ANA_INTSTS_INTSTS2 \ + |ANA_INTSTS_INTSTS1 \ + |ANA_INTSTS_INTSTS0) + +/****************************** ANA Instances *********************************/ +#define IS_ANA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ANA) + +/* Private macros ------------------------------------------------------------*/ +#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\ + ((__STATUS__) == ANA_STATUS_VDCINDROP) ||\ + ((__STATUS__) == ANA_STATUS_VDDALARM) ||\ + ((__STATUS__) == ANA_STATUS_CMP2) ||\ + ((__STATUS__) == ANA_STATUS_CMP1) ||\ + ((__STATUS__) == ANA_STATUS_LOCKL) ||\ + ((__STATUS__) == ANA_STATUS_LOCKH)) + +#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_UPPER_TH3) ||\ + ((__INTSTSR__) == ANA_INT_LOWER_TH3) ||\ + ((__INTSTSR__) == ANA_INT_UPPER_TH2) ||\ + ((__INTSTSR__) == ANA_INT_LOWER_TH2) ||\ + ((__INTSTSR__) == ANA_INT_UPPER_TH1) ||\ + ((__INTSTSR__) == ANA_INT_LOWER_TH1) ||\ + ((__INTSTSR__) == ANA_INT_UPPER_TH0) ||\ + ((__INTSTSR__) == ANA_INT_LOWER_TH0) ||\ + ((__INTSTSR__) == ANA_INT_TADC_OVER) ||\ + ((__INTSTSR__) == ANA_INT_REGERR) ||\ + ((__INTSTSR__) == ANA_INT_SLPFAIL_VDCIN) ||\ + ((__INTSTSR__) == ANA_INT_AVCCLV) ||\ + ((__INTSTSR__) == ANA_INT_VDCINDROP) ||\ + ((__INTSTSR__) == ANA_INT_VDDALARM) ||\ + ((__INTSTSR__) == ANA_INT_CMP2) ||\ + ((__INTSTSR__) == ANA_INT_CMP1) ||\ + ((__INTSTSR__) == ANA_INT_ADCA) ||\ + ((__INTSTSR__) == ANA_INT_ADCM)) + +#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\ + (((__INTSTSC__) & ~ANA_INT_Msk) == 0U)) + +#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__) + +/* Exported Functions ------------------------------------------------------- */ +uint8_t ANA_GetStatus(uint32_t StatusMask); +uint8_t ANA_GetINTStatus(uint32_t IntMask); +void ANA_ClearINTStatus(uint32_t IntMask); +void ANA_INTConfig(uint32_t IntMask, uint32_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ANA_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_clk.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_clk.h new file mode 100644 index 0000000000..b820761595 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_clk.h @@ -0,0 +1,339 @@ +/** + ****************************************************************************** + * @file lib_clk.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Clock library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CLK_H +#define __LIB_CLK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* PLLL Configure */ +typedef struct +{ + uint32_t Source; + uint32_t State; + uint32_t Frequency; +} PLLL_ConfTypeDef; + +/* PLLH Configure */ +typedef struct +{ + uint32_t Source; + uint32_t State; + uint32_t Frequency; +} PLLH_ConfTypeDef; + +/* RCH Configure */ +typedef struct +{ + uint32_t State; +} RCH_ConfTypeDef; + +/* XTALH Configure */ +typedef struct +{ + uint32_t State; +} XTALH_ConfTypeDef; + +/* RTCCLK Configure */ +typedef struct +{ + uint32_t Source; + uint32_t Divider; +} RTCCLK_ConfTypeDef; + +/* HCLK Configure */ +typedef struct +{ + uint32_t Divider; /* 1 ~ 256 */ +} HCLK_ConfTypeDef; + +/* PCLK Configure */ +typedef struct +{ + uint32_t Divider; /* 1 ~ 256 */ +} PCLK_ConfTypeDef; + +/* Clock Configure */ +typedef struct +{ + uint32_t ClockType; /* The clock to be configured */ + + uint32_t AHBSource; + + PLLL_ConfTypeDef PLLL; + + PLLH_ConfTypeDef PLLH; + + XTALH_ConfTypeDef XTALH; + + RTCCLK_ConfTypeDef RTCCLK; + + HCLK_ConfTypeDef HCLK; + + PCLK_ConfTypeDef PCLK; + +} CLK_InitTypeDef; + +/************** Bits definition for ANA_REG9 register ******************/ +#define ANA_REG9_PLLLSEL_26M (0x0U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_13M (0x1U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_6_5M (0x2U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_3_2M (0x3U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_800K (0x5U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_400K (0x6U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_200K (0x7U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLHSEL_X2 (0xCU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X2_5 (0xDU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X3 (0xEU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X3_5 (0xFU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X4 (0x0U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X4_5 (0x1U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X5 (0x2U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X6 (0x4U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X6_5 (0x5U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X7 (0x6U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X7_5 (0x7U << ANA_REG9_PLLHSEL_Pos) + +/************** Bits definition for MISC2_CLKSEL register ******************/ +#define MISC2_CLKSEL_CLKSEL_RCOH (0x0U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000000 */ +#define MISC2_CLKSEL_CLKSEL_XOH (0x1U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000001 */ +#define MISC2_CLKSEL_CLKSEL_PLLH (0x2U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000002 */ +#define MISC2_CLKSEL_CLKSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000003 */ +#define MISC2_CLKSEL_CLKSEL_PLLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000004 */ + +/***** ClockType *****/ +#define CLK_TYPE_MSk (0xFFUL) +#define CLK_TYPE_ALL CLK_TYPE_MSk +#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */ +#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */ +#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */ +#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */ +#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */ +#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */ +#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */ + +/***** AHBSource *****/ +#define CLK_AHBSEL_6_5MRC (0x0U << MISC2_CLKSEL_CLKSEL_Pos) +#define CLK_AHBSEL_6_5MXTAL (0x1U << MISC2_CLKSEL_CLKSEL_Pos) +#define CLK_AHBSEL_HSPLL (0x2U << MISC2_CLKSEL_CLKSEL_Pos) +#define CLK_AHBSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) +#define CLK_AHBSEL_LSPLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) + +/***** PLLL_ConfTypeDef PLLL *****/ +/* PLLL.Source */ +#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL +#define CLK_PLLLSRC_XTALL (0) +/* PLLL.State */ +#define CLK_PLLL_ON ANA_REG3_PLLLPDN +#define CLK_PLLL_OFF (0) +/* PLLL.Frequency */ +#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M +#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M +#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M +#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M +#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M +#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K +#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K +#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K + +/***** PLLH_ConfTypeDef PLLH *****/ +/* PLLH.Source */ +#define CLK_PLLHSRC_RCH (0) +#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL +/* PLLH.State */ +#define CLK_PLLH_ON ANA_REG3_PLLHPDN +#define CLK_PLLH_OFF (0) +/* PLLH.Frequency */ +#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2 +#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5 +#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3 +#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5 +#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4 +#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5 +#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5 +#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5 +#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6 +#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5 +#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7 +#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5 + +/* XTALH_ConfTypeDef XTALH */ +/* XTALH.State */ +#define CLK_XTALH_ON ANA_REG3_XOHPDN +#define CLK_XTALH_OFF (0) + +/* RTCCLK Configure */ +/* RTCCLK.Source */ +#define CLK_RTCCLKSRC_XTALL (0) +#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCCLK_SEL) +/* RTCCLK.Divider */ +#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0) +#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1) + +//AHB Periphral +#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA +#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO +#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD +#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT +#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \ + |MISC2_HCLKEN_GPIO \ + |MISC2_HCLKEN_LCD \ + |MISC2_HCLKEN_CRYPT) + +//APB Periphral +#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA +#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C +#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1 +#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0 +#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1 +#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2 +#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3 +#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4 +#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5 +#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160 +#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161 +#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER +#define CLK_APBPERIPHRAL_MISC1 MISC2_PCLKEN_MISC1 +#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2 +#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU +#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC +#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA +#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0 +#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1 +#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2 +#define CLK_APBPERIPHRAL_SPI3 MISC2_PCLKEN_SPI3 +#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \ + |MISC2_PCLKEN_I2C \ + |MISC2_PCLKEN_SPI1 \ + |MISC2_PCLKEN_UART0 \ + |MISC2_PCLKEN_UART1 \ + |MISC2_PCLKEN_UART2 \ + |MISC2_PCLKEN_UART3 \ + |MISC2_PCLKEN_UART4 \ + |MISC2_PCLKEN_UART5 \ + |MISC2_PCLKEN_ISO78160 \ + |MISC2_PCLKEN_ISO78161 \ + |MISC2_PCLKEN_TIMER \ + |MISC2_PCLKEN_MISC1 \ + |MISC2_PCLKEN_MISC2 \ + |MISC2_PCLKEN_PMU \ + |MISC2_PCLKEN_RTC \ + |MISC2_PCLKEN_ANA \ + |MISC2_PCLKEN_U32K0 \ + |MISC2_PCLKEN_U32K1 \ + |MISC2_PCLKEN_SPI2 \ + |MISC2_PCLKEN_SPI3) + +/***** PLLStatus (CLK_GetPLLLockStatus) *****/ +#define CLK_STATUS_LOCKL ANA_CMPOUT_LOCKL +#define CLK_STATUS_LOCKH ANA_CMPOUT_LOCKH + + +/* Private macros ------------------------------------------------------------*/ +#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_MSk) != 0UL) &&\ + (((__TYPE__) & ~CLK_TYPE_MSk) == 0UL)) + +#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\ + ((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\ + ((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\ + ((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\ + ((__AHBSRC__) == CLK_AHBSEL_LSPLL)) + +#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\ + ((__PLLLSRC__) == CLK_PLLLSRC_XTALL)) + +#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\ + ((__PLLLSTA__) == CLK_PLLL_OFF)) + +#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_2048MHz)) + +#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\ + ((__PLLHSRC__) == CLK_PLLHSRC_XTALH)) + +#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\ + ((__PLLHSTA__) == CLK_PLLH_OFF)) + +#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_49_152MHz)) + +#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\ + ((__XTALHSTA__) == CLK_XTALH_OFF)) + +#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\ + ((__RTCSRC__) == CLK_RTCCLKSRC_RCL)) + +#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\ + ((__RTCDIV__) == CLK_RTCCLKDIV_4)) + +#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\ + ((__HCLKDIV__) < 257UL)) + +#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\ + ((__PCLKDIV__) < 257UL)) + +#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\ + (((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL)) + +#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\ + (((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL)) + +#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_CMPOUT_LOCKL) ||\ + ((__PLLLOCK__) == ANA_CMPOUT_LOCKH)) +/* Exported Functions ------------------------------------------------------- */ +/* CLK Exported Functions Group1: + Initialization and functions ---------------*/ +void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); + +/* CLK Exported Functions Group2: + Peripheral Control -------------------------*/ +void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState); +void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState); +/* CLK Exported Functions Group3: + Get clock/configuration information --------*/ +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLKFreq(void); +uint32_t CLK_GetPLLLFreq(void); +void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); +uint8_t CLK_GetXTALHStatus(void); +uint8_t CLK_GetXTALLStatus(void); +uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CLK_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_cmp.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_cmp.h new file mode 100644 index 0000000000..252aa2ef66 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_cmp.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file lib_cmp.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief CMP library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CMP_H +#define __LIB_CMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* CMP Time struct */ +typedef struct +{ + uint32_t DebSel; + uint32_t SignalSourceSel; + uint32_t BiasSel; +} CMP_TypeDef; + +typedef struct +{ + uint32_t ModeSel; + uint32_t CheckPeriod; + uint32_t CheckNum; +} CMP_CountTypeDef; + +typedef struct +{ + uint32_t DebSel; + uint32_t OutputSel; +} CMP_OutputTypeDef; + +typedef struct +{ + uint32_t INTNumSel; + uint32_t SubSel; + uint32_t THRNum; +} CMP_INTTypeDef; + +/* Macros --------------------------------------------------------------------*/ + +/***** CMP_DEBConfig *****/ +//CMPx +#define CMP_1 (0x00U) +#define CMP_2 (0x02U) +#define IS_CMP(__CMP__) (((__CMP__) == CMP_1) || ((__CMP__) == CMP_2)) +/************** Bits definition for ANA_REG2 register ******************/ +#define ANA_REG2_CMP1SEL_0 (0x0U << ANA_REG2_CMP1SEL_Pos) +#define ANA_REG2_CMP1SEL_1 (0x1U << ANA_REG2_CMP1SEL_Pos) +#define ANA_REG2_CMP1SEL_2 (0x2U << ANA_REG2_CMP1SEL_Pos) +#define ANA_REG2_CMP1SEL_3 (0x3U << ANA_REG2_CMP1SEL_Pos) +#define ANA_REG2_CMP2SEL_0 (0x0U << ANA_REG2_CMP2SEL_Pos) +#define ANA_REG2_CMP2SEL_1 (0x1U << ANA_REG2_CMP2SEL_Pos) +#define ANA_REG2_CMP2SEL_2 (0x2U << ANA_REG2_CMP2SEL_Pos) +#define ANA_REG2_CMP2SEL_3 (0x3U << ANA_REG2_CMP2SEL_Pos) +/************** Bits definition for ANA_REG5 register ******************/ +#define ANA_REG5_CMP1IT_0 (0x0U << ANA_REG5_CMP1IT_Pos) +#define ANA_REG5_CMP1IT_1 (0x1U << ANA_REG5_CMP1IT_Pos) +#define ANA_REG5_CMP1IT_2 (0x2U << ANA_REG5_CMP1IT_Pos) +#define ANA_REG5_CMP1IT_3 (0x3U << ANA_REG5_CMP1IT_Pos) +#define ANA_REG5_CMP2IT_0 (0x0U << ANA_REG5_CMP2IT_Pos) +#define ANA_REG5_CMP2IT_1 (0x1U << ANA_REG5_CMP2IT_Pos) +#define ANA_REG5_CMP2IT_2 (0x2U << ANA_REG5_CMP2IT_Pos) +#define ANA_REG5_CMP2IT_3 (0x3U << ANA_REG5_CMP2IT_Pos) +/************** Bits definition for ANA_CTRL register ******************/ +//Debounce +#define CMP_DEB_NONE (0x0U) +#define CMP_DEB_RTCCLK_2 (0x1U) +#define CMP_DEB_RTCCLK_3 (0x2U) +#define CMP_DEB_RTCCLK_4 (0x3U) +#define IS_CMP_DEB(__DEB__) (((__DEB__) == CMP_DEB_NONE) ||\ + ((__DEB__) == CMP_DEB_RTCCLK_2) ||\ + ((__DEB__) == CMP_DEB_RTCCLK_3) ||\ + ((__DEB__) == CMP_DEB_RTCCLK_4)) + +/***** SourceSelect (CMP_ConfigSignalSource) *****/ +#define CMP_SIGNALSRC_PPIN_TO_VREF 0x00 +#define CMP_SIGNALSRC_PPIN_TO_BGPREF 0x01 +#define CMP_SIGNALSRC_PBAT_TO_VREF 0x80 +#define CMP_SIGNALSRC_PBAT_TO_BGPREF 0x81 +#define CMP_SIGNALSRC_NPIN_TO_VREF 0x10 +#define CMP_SIGNALSRC_NPIN_TO_BGPREF 0x11 +#define CMP_SIGNALSRC_PPIN_TO_NPIN 0x20 +#define CMP_SIGNALSRC_PBAT_TO_NPIN 0xA0 + +#define IS_CMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_VREF) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_BGPREF) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_NPIN) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_NPIN) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_VREF) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_BGPREF) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_VREF) ||\ + ((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_BGPREF)) + +/***** BiasSel (CMP_BiasConfig) *****/ +#define CMP_BIAS_20nA (0x0U) +#define CMP_BIAS_100nA (0x1U) +#define CMP_BIAS_500nA (0x2U) +#define IS_CMP_BIAS(__BIAS__) (((__BIAS__) == CMP_BIAS_20nA) ||\ + ((__BIAS__) == CMP_BIAS_100nA) ||\ + ((__BIAS__) == CMP_BIAS_500nA)) + +/***** CheckPeriod (CMP_CheckFrequecnyConfig) *****/ +#define CMP_PERIOD_30US 0 +#define CMP_PERIOD_7_8125MS 1 +#define CMP_PERIOD_125MS 2 +#define CMP_PERIOD_250MS 3 +#define CMP_PERIOD_500MS 4 +#define IS_CMP_CHECKPERIOD(__CHECKPERIOD__) (((__CHECKPERIOD__) == CMP_PERIOD_30US) ||\ + ((__CHECKPERIOD__) == CMP_PERIOD_7_8125MS)||\ + ((__CHECKPERIOD__) == CMP_PERIOD_125MS) ||\ + ((__CHECKPERIOD__) == CMP_PERIOD_250MS) ||\ + ((__CHECKPERIOD__) == CMP_PERIOD_500MS)) + +/***** Mode (CMP_ModeConfig) *****/ +#define CMP_MODE_OFF (0x0U) +#define CMP_MODE_RISING (0x1U) +#define CMP_MODE_FALLING (0x2U) +#define CMP_MODE_BOTH (0x3U) +#define IS_CMP_MODE(__MODE__) (((__MODE__) == CMP_MODE_OFF) ||\ + ((__MODE__) == CMP_MODE_RISING) ||\ + ((__MODE__) == CMP_MODE_FALLING) ||\ + ((__MODE__) == CMP_MODE_BOTH)) + +//CountSel +#define CMP_COUNT_NOSUB 0 +#define CMP_COUNT_SUB 1 +#define IS_CMP_COUNT(__COUNT__) (((__COUNT__) == CMP_COUNT_NOSUB) ||\ + ((__COUNT__) == CMP_COUNT_SUB)) + +//SubSel +#define CMP_INTNUM_EVERY 0 +#define CMP_INTNUM_1 1 +#define IS_CMP_INTNUM(__INTNUM__) (((__INTNUM__) == CMP_INTNUM_EVERY) ||\ + ((__INTNUM__) == CMP_INTNUM_1)) + +//THRNum +#define IS_CMP_THRNUM(__THRNUM__) ((__THRNUM__) < 65536UL) + +#define CMP_CHKNUM_1 0 +#define CMP_CHKNUM_2 1 +#define CMP_CHKNUM_3 2 +#define CMP_CHKNUM_4 3 +#define CMP_CHKNUM_5 4 +#define CMP_CHKNUM_6 5 +#define CMP_CHKNUM_7 6 +#define CMP_CHKNUM_8 7 +#define CMP_CHKNUM_9 8 +#define CMP_CHKNUM_10 9 +#define CMP_CHKNUM_11 10 +#define CMP_CHKNUM_12 11 +#define CMP_CHKNUM_13 12 +#define CMP_CHKNUM_14 13 +#define CMP_CHKNUM_15 14 +#define CMP_CHKNUM_16 15 +#define IS_CMP_CHKNUM(__CHKNUM__) (__CHKNUM__ < 16) + +//DebSel +//SubSel +#define CMP_OUTPUT_DEB 0 +#define CMP_OUTPUT_NODEB 1 +#define IS_CMP_OUTPUTDEB(__OUTPUTDEB__) (((__OUTPUTDEB__) == CMP_OUTPUT_DEB) ||\ + ((__OUTPUTDEB__) == CMP_OUTPUT_NODEB)) + +/* Exported Functions ------------------------------------------------------- */ +/* CMP Exported Functions Group1: + (De)Initialization ------------------------*/ +void CMP_DeInit(uint32_t CMPx); +void CMP_Init(uint32_t CMPx, CMP_TypeDef *InitStruct); +void CMP_StructInit(CMP_TypeDef *InitStruct); +void CMP_CountStructInit(CMP_CountTypeDef *InitStruct); +void CMP_CountInit(uint32_t CMPx, CMP_CountTypeDef *InitStruct); +void CMP_INTStructInit(CMP_INTTypeDef *InitStruct); +void CMP_INTInit(uint32_t CMPx, CMP_INTTypeDef *InitStruct); +void CMP_OutputStructInit(CMP_OutputTypeDef *InitStruct); +void CMP_OutputInit(uint32_t CMPx, CMP_OutputTypeDef *InitStruct); +/* CMP Exported Functions Group2: + Interrupt (flag) --------------------------*/ +void CMP_INTConfig(uint32_t CMPx, uint32_t NewState); +uint8_t CMP_GetINTStatus(uint32_t CMPx); +void CMP_ClearINTStatus(uint32_t CMPx); +/* CMP Exported Functions Group3: + MISC Configuration ------------------------*/ +void CMP_Cmd(uint32_t CMPx, uint32_t NewState); +uint32_t CMP_GetCNTValue(uint32_t CMPx); +void CMP_ClearCNTValue(uint32_t CMPx); +uint8_t CMP_GetOutputValue(uint32_t CMPx); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CMP_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_crypt.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_crypt.h new file mode 100644 index 0000000000..295fe3c2db --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_crypt.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file lib_crypt.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief CRYPT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CRYPT_H +#define __LIB_CRYPT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" +/************** Bits definition for CRYPT_CTRL register ******************/ +#define CRYPT_CTRL_MODE_MULTIPLY (0x0U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_ADD (0x1U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_SUB (0x2U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_RSHIFT1 (0x3U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_LENGTH_32 (0x0U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_64 (0x1U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_96 (0x2U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_128 (0x3U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_160 (0x4U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_192 (0x5U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_224 (0x6U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_256 (0x7U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_288 (0x8U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_320 (0x9U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_352 (0xAU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_384 (0xBU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_416 (0xCU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_448 (0xDU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_480 (0xEU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_512 (0xFU << CRYPT_CTRL_LENGTH_Pos) +//Length +#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32 +#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64 +#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96 +#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128 +#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160 +#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192 +#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224 +#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256 +#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288 +#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320 +#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352 +#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384 +#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416 +#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448 +#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480 +#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512 +//Nostop +#define CRYPT_STOPCPU (0) +#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP + +/* Private macros ------------------------------------------------------------*/ +#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) & 0x3U) == 0U) + +#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\ + ((__LENGTH__) == CRYPT_LENGTH_64) ||\ + ((__LENGTH__) == CRYPT_LENGTH_32) ||\ + ((__LENGTH__) == CRYPT_LENGTH_96) ||\ + ((__LENGTH__) == CRYPT_LENGTH_128) ||\ + ((__LENGTH__) == CRYPT_LENGTH_160) ||\ + ((__LENGTH__) == CRYPT_LENGTH_192) ||\ + ((__LENGTH__) == CRYPT_LENGTH_224) ||\ + ((__LENGTH__) == CRYPT_LENGTH_256) ||\ + ((__LENGTH__) == CRYPT_LENGTH_288) ||\ + ((__LENGTH__) == CRYPT_LENGTH_320) ||\ + ((__LENGTH__) == CRYPT_LENGTH_352) ||\ + ((__LENGTH__) == CRYPT_LENGTH_384) ||\ + ((__LENGTH__) == CRYPT_LENGTH_416) ||\ + ((__LENGTH__) == CRYPT_LENGTH_448) ||\ + ((__LENGTH__) == CRYPT_LENGTH_480) ||\ + ((__LENGTH__) == CRYPT_LENGTH_512)) + +#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU)) + +/****************************** CRYPT Instances *******************************/ +#define IS_CRYPT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRYPT) + +/* Exported Functions ------------------------------------------------------- */ +void CRYPT_AddressAConfig(uint16_t AddrA); +void CRYPT_AddressBConfig(uint16_t AddrB); +void CRYPT_AddressOConfig(uint16_t AddrO); +uint8_t CRYPT_GetCarryBorrowBit(void); +void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop); +void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop); +void CRYPT_StartSub(uint32_t Length, uint32_t Nostop); +void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop); +void CRYPT_WaitForLastOperation(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CRYPT_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_dma.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_dma.h new file mode 100644 index 0000000000..d746c333d8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_dma.h @@ -0,0 +1,267 @@ +/** + ****************************************************************************** + * @file lib_dma.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief DMA library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_DMA_H +#define __LIB_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//Channel +#define DMA_CHANNEL_0 (0) +#define DMA_CHANNEL_1 (1) +#define DMA_CHANNEL_2 (2) +#define DMA_CHANNEL_3 (3) + +typedef struct +{ + uint32_t DestAddr; /* destination address */ + uint32_t SrcAddr; /* source address */ + uint8_t FrameLen; /* Frame length */ + uint8_t PackLen; /* Package length */ + uint32_t ContMode; /* Continuous mode */ + uint32_t TransMode; /* Transfer mode */ + uint32_t ReqSrc; /* DMA request source */ + uint32_t DestAddrMode; /* Destination address mode */ + uint32_t SrcAddrMode; /* Source address mode */ + uint32_t TransSize; /* Transfer size mode */ +} DMA_InitType; + +/************** Bits definition for DMA_CxCTL register ******************/ + + + +/************** Bits definition for DMA_AESCTL register ******************/ +/****************************** DMA Instances *********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA) + +//ContMode +#define DMA_CONTMODE_ENABLE DMA_CCTL_CONT +#define DMA_CONTMODE_DISABLE 0 +#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\ + ((__CONTMOD__) == DMA_CONTMODE_DISABLE)) + +//TransMode +#define DMA_TRANSMODE_SINGLE 0 +#define DMA_TRANSMODE_PACK DMA_CCTL_TMODE +#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\ + ((__TRANSMOD__) == DMA_TRANSMODE_PACK)) + +//ReqSrc +#define DMA_REQSRC_SOFT (0x0U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000000 */ +#define DMA_REQSRC_ADC (0x1U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000080 */ +#define DMA_REQSRC_UART0TX (0x2U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000100 */ +#define DMA_REQSRC_UART0RX (0x3U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000180 */ +#define DMA_REQSRC_UART1TX (0x4U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000200 */ +#define DMA_REQSRC_UART1RX (0x5U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000280 */ +#define DMA_REQSRC_UART2TX (0x6U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000300 */ +#define DMA_REQSRC_UART2RX (0x7U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000380 */ +#define DMA_REQSRC_UART3TX (0x8U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000400 */ +#define DMA_REQSRC_UART3RX (0x9U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000480 */ +#define DMA_REQSRC_UART4TX (0xAU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000500 */ +#define DMA_REQSRC_UART4RX (0xBU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000580 */ +#define DMA_REQSRC_UART5TX (0xCU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000600 */ +#define DMA_REQSRC_UART5RX (0xDU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000680 */ +#define DMA_REQSRC_ISO78160TX (0xEU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000700 */ +#define DMA_REQSRC_ISO78160RX (0xFU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000780 */ +#define DMA_REQSRC_ISO78161TX (0x10U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000800 */ +#define DMA_REQSRC_ISO78161RX (0x11U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000880 */ +#define DMA_REQSRC_TIMER0 (0x12U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000900 */ +#define DMA_REQSRC_TIMER1 (0x13U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000980 */ +#define DMA_REQSRC_TIMER2 (0x14U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A00 */ +#define DMA_REQSRC_TIMER3 (0x15U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A80 */ +#define DMA_REQSRC_SPI1TX (0x16U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B00 */ +#define DMA_REQSRC_SPI1RX (0x17U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B80 */ +#define DMA_REQSRC_U32K0 (0x18U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C00 */ +#define DMA_REQSRC_U32K1 (0x19U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C80 */ +#define DMA_REQSRC_CMP1 (0x1AU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D00 */ +#define DMA_REQSRC_CMP2 (0x1BU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D80 */ +#define DMA_REQSRC_SPI3TX (0x1CU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E00 */ +#define DMA_REQSRC_SPI3RX (0x1DU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E80 */ +#define DMA_REQSRC_SPI2TX (0x1EU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F00 */ +#define DMA_REQSRC_SPI2RX (0x1FU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F80 */ + +#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\ + ((__REQSRC__) == DMA_REQSRC_ADC) ||\ + ((__REQSRC__) == DMA_REQSRC_UART0TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART0RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART1TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART1RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART2TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART2RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART3TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART3RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART4TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART4RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART5TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART5RX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER0) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER1) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER2) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER3) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\ + ((__REQSRC__) == DMA_REQSRC_U32K0) ||\ + ((__REQSRC__) == DMA_REQSRC_U32K1) ||\ + ((__REQSRC__) == DMA_REQSRC_CMP1) ||\ + ((__REQSRC__) == DMA_REQSRC_CMP2) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI3TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI3RX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI2RX)) + + +//DestAddrMode +#define DMA_DESTADDRMODE_FIX (0x0U << DMA_CCTL_DMODE_Pos) /*!< 0x00000000 */ +#define DMA_DESTADDRMODE_PEND (0x1U << DMA_CCTL_DMODE_Pos) /*!< 0x00000020 */ +#define DMA_DESTADDRMODE_FEND (0x2U << DMA_CCTL_DMODE_Pos) /*!< 0x00000040 */ +#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\ + ((__DAM__) == DMA_DESTADDRMODE_PEND) ||\ + ((__DAM__) == DMA_DESTADDRMODE_FEND)) + +//SrcAddrMode +#define DMA_SRCADDRMODE_FIX (0x0U << DMA_CCTL_SMODE_Pos) /*!< 0x00000000 */ +#define DMA_SRCADDRMODE_PEND (0x1U << DMA_CCTL_SMODE_Pos) /*!< 0x00000008 */ +#define DMA_SRCADDRMODE_FEND (0x2U << DMA_CCTL_SMODE_Pos) /*!< 0x00000010 */ +#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\ + ((__SAM__) == DMA_SRCADDRMODE_PEND) ||\ + ((__SAM__) == DMA_SRCADDRMODE_FEND)) + +//TransSize +#define DMA_TRANSSIZE_BYTE (0x0U << DMA_CCTL_SIZE_Pos) +#define DMA_TRANSSIZE_HWORD (0x1U << DMA_CCTL_SIZE_Pos) +#define DMA_TRANSSIZE_WORD (0x2U << DMA_CCTL_SIZE_Pos) +#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\ + ((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\ + ((__TSIZE__) == DMA_TRANSSIZE_WORD)) + +#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U) +#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U) + +typedef struct +{ + uint32_t Mode; /* AES mode */ + uint32_t Direction; /* Direction */ + uint32_t *KeyStr; /* AES key */ +} DMA_AESInitType; + +//AES MODE +#define DMA_AESMODE_128 (0x0U << DMA_AESCTL_MODE_Pos) /*!< 0x00000000 */ +#define DMA_AESMODE_192 (0x1U << DMA_AESCTL_MODE_Pos) /*!< 0x00000004 */ +#define DMA_AESMODE_256 (0x2U << DMA_AESCTL_MODE_Pos) /*!< 0x00000008 */ +#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\ + ((__AESMOD__) == DMA_AESMODE_192) ||\ + ((__AESMOD__) == DMA_AESMODE_256)) + +//AES Direction +#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC +#define DMA_AESDIRECTION_DECODE 0 +#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\ + ((__AESDIR__) == DMA_AESDIRECTION_DECODE)) + +//INT +#define DMA_INT_C3DA DMA_IE_C3DAIE +#define DMA_INT_C2DA DMA_IE_C2DAIE +#define DMA_INT_C1DA DMA_IE_C1DAIE +#define DMA_INT_C0DA DMA_IE_C0DAIE +#define DMA_INT_C3FE DMA_IE_C3FEIE +#define DMA_INT_C2FE DMA_IE_C2FEIE +#define DMA_INT_C1FE DMA_IE_C1FEIE +#define DMA_INT_C0FE DMA_IE_C0FEIE +#define DMA_INT_C3PE DMA_IE_C3PEIE +#define DMA_INT_C2PE DMA_IE_C2PEIE +#define DMA_INT_C1PE DMA_IE_C1PEIE +#define DMA_INT_C0PE DMA_IE_C0PEIE +#define DMA_INT_Msk (0xFFFUL) +#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\ + (((__INT__) & ~DMA_INT_Msk) == 0U)) + +//INTSTS +#define DMA_INTSTS_C3DA DMA_STS_C3DA +#define DMA_INTSTS_C2DA DMA_STS_C2DA +#define DMA_INTSTS_C1DA DMA_STS_C1DA +#define DMA_INTSTS_C0DA DMA_STS_C0DA +#define DMA_INTSTS_C3FE DMA_STS_C3FE +#define DMA_INTSTS_C2FE DMA_STS_C2FE +#define DMA_INTSTS_C1FE DMA_STS_C1FE +#define DMA_INTSTS_C0FE DMA_STS_C0FE +#define DMA_INTSTS_C3PE DMA_STS_C3PE +#define DMA_INTSTS_C2PE DMA_STS_C2PE +#define DMA_INTSTS_C1PE DMA_STS_C1PE +#define DMA_INTSTS_C0PE DMA_STS_C0PE +#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY +#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY +#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY +#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY +#define DMA_INTSTS_Msk (0xFFF0UL) + +#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0BUSY)) + +#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U)) + +#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\ + ((__CH__) == DMA_CHANNEL_1) ||\ + ((__CH__) == DMA_CHANNEL_2) ||\ + ((__CH__) == DMA_CHANNEL_3)) + +/* Exported Functions ------------------------------------------------------- */ +/* DMA Exported Functions Group1: + (De)Initialization ------------------------*/ +void DMA_DeInit(uint32_t Channel); +void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel); +void DMA_StructInit(DMA_InitType *InitStruct); +void DMA_AESDeInit(void); +void DMA_AESInit(DMA_AESInitType *InitStruct); +/* DMA Exported Functions Group2: + Interrupt (flag) --------------------------*/ +void DMA_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t DMA_GetINTStatus(uint32_t INTMask); +void DMA_ClearINTStatus(uint32_t INTMask); +/* DMA Exported Functions Group3: + MISC Configuration ------------------------*/ +void DMA_Cmd(uint32_t Channel, uint32_t NewState); +void DMA_AESCmd(uint32_t NewState); +void DMA_StopTransmit(uint32_t Channel, uint32_t NewState); +uint8_t DMA_GetFrameLenTransferred(uint32_t Channel); +uint8_t DMA_GetPackLenTransferred(uint32_t Channel); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_DMA_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_flash.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_flash.h new file mode 100644 index 0000000000..f871a2e383 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_flash.h @@ -0,0 +1,159 @@ +/** + ****************************************************************************** + * @file lib_flash.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief FLASH library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_FLASH_H +#define __LIB_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define FLASH_BLOCK_0 (0x00000001UL) +#define FLASH_BLOCK_1 (0x00000002UL) +#define FLASH_BLOCK_2 (0x00000004UL) +#define FLASH_BLOCK_3 (0x00000008UL) +#define FLASH_BLOCK_4 (0x00000010UL) +#define FLASH_BLOCK_5 (0x00000020UL) +#define FLASH_BLOCK_6 (0x00000040UL) +#define FLASH_BLOCK_7 (0x00000080UL) +#define FLASH_BLOCK_8 (0x00000100UL) +#define FLASH_BLOCK_9 (0x00000200UL) +#define FLASH_BLOCK_10 (0x00000400UL) +#define FLASH_BLOCK_11 (0x00000800UL) +#define FLASH_BLOCK_12 (0x00001000UL) +#define FLASH_BLOCK_13 (0x00002000UL) +#define FLASH_BLOCK_14 (0x00004000UL) +#define FLASH_BLOCK_15 (0x00008000UL) +#define FLASH_BLOCK_16 (0x00010000UL) +#define FLASH_BLOCK_17 (0x00020000UL) +#define FLASH_BLOCK_18 (0x00040000UL) +#define FLASH_BLOCK_19 (0x00080000UL) +#define FLASH_BLOCK_20 (0x00100000UL) +#define FLASH_BLOCK_21 (0x00200000UL) +#define FLASH_BLOCK_22 (0x00400000UL) +#define FLASH_BLOCK_23 (0x00800000UL) +#define FLASH_BLOCK_24 (0x01000000UL) +#define FLASH_BLOCK_25 (0x02000000UL) +#define FLASH_BLOCK_26 (0x04000000UL) +#define FLASH_BLOCK_27 (0x08000000UL) +#define FLASH_BLOCK_28 (0x10000000UL) +#define FLASH_BLOCK_29 (0x20000000UL) +#define FLASH_BLOCK_30 (0x40000000UL) +#define FLASH_BLOCK_31 (0x80000000UL) +#define FLASH_BLOCK_Msk (0xFFFFFFFFUL) +#define FLASH_BLOCK_ALL FLASH_BLOCK_Msk +#define IS_FLASH_RWBLOCK(__BLOCK__) ((((__BLOCK__) & FLASH_BLOCK_Msk) != 0UL) &&\ + (((__BLOCK__) & ~FLASH_BLOCK_Msk) == 0UL)) + +#define IS_FLASH_BLOCK(__BLOCK__) (((__BLOCK__) == FLASH_BLOCK_0) ||\ + ((__BLOCK__) == FLASH_BLOCK_1) ||\ + ((__BLOCK__) == FLASH_BLOCK_2) ||\ + ((__BLOCK__) == FLASH_BLOCK_3) ||\ + ((__BLOCK__) == FLASH_BLOCK_4) ||\ + ((__BLOCK__) == FLASH_BLOCK_5) ||\ + ((__BLOCK__) == FLASH_BLOCK_6) ||\ + ((__BLOCK__) == FLASH_BLOCK_7) ||\ + ((__BLOCK__) == FLASH_BLOCK_8) ||\ + ((__BLOCK__) == FLASH_BLOCK_9) ||\ + ((__BLOCK__) == FLASH_BLOCK_10) ||\ + ((__BLOCK__) == FLASH_BLOCK_11) ||\ + ((__BLOCK__) == FLASH_BLOCK_12) ||\ + ((__BLOCK__) == FLASH_BLOCK_13) ||\ + ((__BLOCK__) == FLASH_BLOCK_14) ||\ + ((__BLOCK__) == FLASH_BLOCK_15) ||\ + ((__BLOCK__) == FLASH_BLOCK_16) ||\ + ((__BLOCK__) == FLASH_BLOCK_17) ||\ + ((__BLOCK__) == FLASH_BLOCK_18) ||\ + ((__BLOCK__) == FLASH_BLOCK_19) ||\ + ((__BLOCK__) == FLASH_BLOCK_20) ||\ + ((__BLOCK__) == FLASH_BLOCK_21) ||\ + ((__BLOCK__) == FLASH_BLOCK_22) ||\ + ((__BLOCK__) == FLASH_BLOCK_23) ||\ + ((__BLOCK__) == FLASH_BLOCK_24) ||\ + ((__BLOCK__) == FLASH_BLOCK_25) ||\ + ((__BLOCK__) == FLASH_BLOCK_26) ||\ + ((__BLOCK__) == FLASH_BLOCK_27) ||\ + ((__BLOCK__) == FLASH_BLOCK_28) ||\ + ((__BLOCK__) == FLASH_BLOCK_29) ||\ + ((__BLOCK__) == FLASH_BLOCK_30) ||\ + ((__BLOCK__) == FLASH_BLOCK_31)) + +#define FLASH_READ (0) +#define FLASH_WRITE (1) +#define IS_FLASH_OPERATION(__OPERATION__) (((__OPERATION__) == FLASH_READ) ||\ + ((__OPERATION__) == FLASH_WRITE)) + +/************** Bits definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_CSMODE_DISABLE (0x0U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000000 */ +#define FLASH_CTRL_CSMODE_ALWAYSON (0x1U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_CSMODE_TIM2OV (0x2U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_CSMODE_RTC (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */ + +//CSMode +#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE +#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON +#define FLASH_CSMODE_TMR2OV FLASH_CTRL_CSMODE_TIM2OV +#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC +#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\ + ((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\ + ((__CSMODE__) == FLASH_CSMODE_TMR2OV) ||\ + ((__CSMODE__) == FLASH_CSMODE_RTC)) + +//INT +#define FLASH_INT_CS FLASH_CTRL_CSINTEN +#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS) + +//WriteStatus +#define FLASH_WSTA_BUSY 0 +#define FLASH_WRITE_FINISH 1 +#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH + +#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x80000UL) + +#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x80000UL) &&\ + (((__ADDRW__) & 0x3U) == 0U)) + +#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x80000UL) &&\ + (((__ADDRHW__) & 0x1U) == 0U)) + +#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x80000) && ((__ADDRESS2__) < 0x80000) && ((__ADDRESS1__) < (__ADDRESS2__))) + +/* Exported Functions ------------------------------------------------------- */ + +void FLASH_Init(uint32_t CSMode); +void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState); +void FLASH_CycleInit(void); +void FLASH_SectorErase(uint32_t SectorAddr); +void FLASH_ChipErase(void); +void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length); +void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length); +void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length); +void FLASH_SetReadProtection(uint32_t Block); +void FLASH_WriteProtection(uint32_t Block, uint32_t NewState); +void FLASH_ICEProtection(uint32_t NewState); +uint8_t FLASH_GetProtectionStatus(uint32_t Block, uint32_t Operation); +uint32_t FLASH_GetAllProtectionStatus(uint32_t Operation); +void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd); +void FLASH_SetCheckSumCompValue(uint32_t Checksum); +uint32_t FLASH_GetCheckSum(void); +uint8_t FLASH_GetINTStatus(uint32_t IntMask); +void FLASH_ClearINTStatus(uint32_t IntMask); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_FLASH_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_gpio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_gpio.h new file mode 100644 index 0000000000..5e49c5abdf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_gpio.h @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file lib_gpio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief GPIO library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_GPIO_H +#define __LIB_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define GET_BITBAND_ADDR(addr, bitnum) ((((uint32_t)addr) & 0xF0000000) + \ + 0x2000000 + ((((uint32_t)addr) & 0xFFFFF) << 5) + (bitnum << 2)) + +typedef struct +{ + uint32_t GPIO_Pin; + uint32_t GPIO_Mode; +} GPIO_InitType; + +typedef struct +{ + __IO uint32_t DATBitBand[16]; +} GPIO_DATInitType; + +#define GPIO_A ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40014018,0))) +#define GPIO_B ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000028,0))) +#define GPIO_C ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000048,0))) +#define GPIO_D ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000068,0))) +#define GPIO_E ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x40000088,0))) +#define GPIO_F ((GPIO_DATInitType*) (uint32_t)(GET_BITBAND_ADDR(0x400000A8,0))) +#define IS_GPIO_DAT(__GPIODAT__) (((__GPIODAT__) == GPIO_A) ||\ + ((__GPIODAT__) == GPIO_B) ||\ + ((__GPIODAT__) == GPIO_C) ||\ + ((__GPIODAT__) == GPIO_D) ||\ + ((__GPIODAT__) == GPIO_E) ||\ + ((__GPIODAT__) == GPIO_F)) + +#define IS_GPIO_PINNUM(__PINNUM__) ((__PINNUM__) < 16U) + +#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U)) + +//GPIO_Pin +#define GPIO_Pin_0 ((uint16_t)0x0001) +#define GPIO_Pin_1 ((uint16_t)0x0002) +#define GPIO_Pin_2 ((uint16_t)0x0004) +#define GPIO_Pin_3 ((uint16_t)0x0008) +#define GPIO_Pin_4 ((uint16_t)0x0010) +#define GPIO_Pin_5 ((uint16_t)0x0020) +#define GPIO_Pin_6 ((uint16_t)0x0040) +#define GPIO_Pin_7 ((uint16_t)0x0080) +#define GPIO_Pin_8 ((uint16_t)0x0100) +#define GPIO_Pin_9 ((uint16_t)0x0200) +#define GPIO_Pin_10 ((uint16_t)0x0400) +#define GPIO_Pin_11 ((uint16_t)0x0800) +#define GPIO_Pin_12 ((uint16_t)0x1000) +#define GPIO_Pin_13 ((uint16_t)0x2000) +#define GPIO_Pin_14 ((uint16_t)0x4000) +#define GPIO_Pin_15 ((uint16_t)0x8000) +#define GPIO_Pin_All ((uint16_t)0xFFFF) +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\ + (((__PIN__) & ~GPIO_Pin_All) == 0UL)) +#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\ + ((__PINR__) == GPIO_Pin_1) ||\ + ((__PINR__) == GPIO_Pin_2) ||\ + ((__PINR__) == GPIO_Pin_3) ||\ + ((__PINR__) == GPIO_Pin_4) ||\ + ((__PINR__) == GPIO_Pin_5) ||\ + ((__PINR__) == GPIO_Pin_6) ||\ + ((__PINR__) == GPIO_Pin_7) ||\ + ((__PINR__) == GPIO_Pin_8) ||\ + ((__PINR__) == GPIO_Pin_9) ||\ + ((__PINR__) == GPIO_Pin_10) ||\ + ((__PINR__) == GPIO_Pin_11) ||\ + ((__PINR__) == GPIO_Pin_12) ||\ + ((__PINR__) == GPIO_Pin_13) ||\ + ((__PINR__) == GPIO_Pin_14) ||\ + ((__PINR__) == GPIO_Pin_15)) + +//GPIO_Mode +#define GPIO_MODE_INPUT (0xCU) +#define GPIO_MODE_OUTPUT_CMOS (0x2U) +#define GPIO_MODE_OUTPUT_OD (0x3U) +#define GPIO_MODE_INOUT_OD (0xBU) +#define GPIO_MODE_INOUT_CMOS (0xAU) +#define GPIO_MODE_FORBIDDEN (0x4U) +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_CMOS) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_INOUT_OD) ||\ + ((__MODE__) == GPIO_MODE_INOUT_CMOS) ||\ + ((__MODE__) == GPIO_MODE_FORBIDDEN)) + +/************** Bits definition for IO_MISC register ******************/ +#define IO_MISC_PLLHDIV_1 (0x0U << GPIOAF_IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_2 (0x1U << GPIOAF_IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_4 (0x2U << GPIOAF_IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_8 (0x3U << GPIOAF_IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_16 (0x4U << GPIOAF_IO_MISC_PLLHDIV_Pos) + +//GPIO AF +#define GPIOB_AF_PLLHDIV GPIOAF_IOB_SEL_SEL1 +#define GPIOB_AF_PLLLOUT GPIOAF_IOB_SEL_SEL2 +#define GPIOB_AF_OSC GPIOAF_IOB_SEL_SEL6 +#define GPIOE_AF_CMP1O GPIOAF_IOE_SEL_SEL7 +#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\ + ((__GPIOAF__) == GPIOB_AF_PLLLOUT) ||\ + ((__GPIOAF__) == GPIOB_AF_OSC) ||\ + ((__GPIOAF__) == GPIOE_AF_CMP1O)) + +#define IS_GPIOB_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\ + ((__GPIOAF__) == GPIOB_AF_PLLLOUT) ||\ + ((__GPIOAF__) == GPIOB_AF_OSC)) + +#define IS_GPIOE_GPIOAF(__GPIOAF__) ((__GPIOAF__) == GPIOE_AF_CMP1O) + + +//PMUIO AF +#define PMUIO7_AF_PLLDIV GPIOA_SEL_SEL7 +#define PMUIO6_AF_CMP2O GPIOA_SEL_SEL6 +#define PMUIO3_AF_PLLDIV GPIOA_SEL_SEL3 +#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO6_AF_CMP2O | PMUIO3_AF_PLLDIV) + +//GPIO pin remap +#define GPIO_REMAP_I2C GPIOAF_IO_MISC_I2CIOC +#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C) + +//PLLDIV +#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1 +#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2 +#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4 +#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8 +#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16 +#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_2) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_4) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_8) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_16)) + + +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOE) || \ + ((INSTANCE) == GPIOF)) + +#define IS_PMUIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPIOA) + +#define IS_GPIOAF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOE)) + +#define IS_GPIOE_GPIOAF(__GPIOAF__) ((__GPIOAF__) == GPIOE_AF_CMP1O) + +#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\ + (((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U)) + +#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C) + +#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_2) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_4) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_8) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_16)) + +/* Exported Functions ------------------------------------------------------- */ +/* GPIO Exported Functions Group1: + Initialization and functions --------------*/ +void GPIOBToF_Init(GPIO_Type *GPIOx, GPIO_InitType *InitStruct); +void GPIOA_Init(GPIOA_Type *GPIOx, GPIO_InitType *InitStruct); +/* GPIO Exported Functions Group2: + Read input data ---------------------------*/ +uint8_t GPIOBToF_ReadInputDataBit(GPIO_Type *GPIOx, uint16_t GPIO_Pin); +uint8_t GPIOA_ReadInputDataBit(GPIOA_Type *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIOBToF_ReadInputData(GPIO_Type* GPIOx); +uint16_t GPIOA_ReadInputData(GPIOA_Type* GPIOx); +/* GPIO Exported Functions Group3: + Read output data --------------------------*/ +uint8_t GPIOBToF_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin); +uint8_t GPIOA_ReadOutputDataBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIOBToF_ReadOutputData(GPIO_Type* GPIOx); +uint16_t GPIOA_ReadOutputData(GPIOA_Type* GPIOx); +/* GPIO Exported Functions Group4: + Write output data -------------------------*/ +void GPIO_WriteBit(GPIO_DATInitType* DATx, uint8_t PinNum, uint8_t val); +void GPIOBToF_Write(GPIO_Type* GPIOx, uint16_t val); +void GPIOA_Write(GPIOA_Type* GPIOx, uint16_t val); +/* GPIO Exported Functions Group5: + IO AF configure ---------------------------*/ +void GPIOBToF_AFConfig(GPIO_Type* GPIOx, uint32_t GPIO_AFx, uint8_t NewState); +void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState); +/* GPIO Exported Functions Group6: + IO Remap configure ------------------------*/ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState); +/* GPIO Exported Functions Group7: + Others ------------------------------------*/ +void GPIO_PLLDIVConfig(uint32_t Divider); +void GPIOA_DeGlitchCmd( uint16_t GPIO_Pin, uint8_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_GPIO_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_i2c.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_i2c.h new file mode 100644 index 0000000000..280e36ba96 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_i2c.h @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file lib_i2c.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief IIC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_I2C_H +#define __LIB_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t SlaveAddr; + uint32_t GeneralCallAck; + uint32_t AssertAcknowledge; + uint32_t ClockSource; +} I2C_InitType; + +/************** Bits definition for I2C_CTRL register ******************/ +#define I2C_CTRL_CR_0 (0x0U << I2C_CTRL_CR0_Pos) /*!< 0x0000000 */ +#define I2C_CTRL_CR_1 (0x1U << I2C_CTRL_CR0_Pos) /*!< 0x0000001 */ +#define I2C_CTRL_CR_2 (0x2U << I2C_CTRL_CR0_Pos) /*!< 0x0000002 */ +#define I2C_CTRL_CR_3 (0x3U << I2C_CTRL_CR0_Pos) /*!< 0x0000003 */ +#define I2C_CTRL_CR_4 (0x80U << I2C_CTRL_CR0_Pos) /*!< 0x0000080 */ +#define I2C_CTRL_CR_5 (0x81U << I2C_CTRL_CR0_Pos) /*!< 0x0000081 */ +#define I2C_CTRL_CR_6 (0x82U << I2C_CTRL_CR0_Pos) /*!< 0x0000082 */ +#define I2C_CTRL_CR_7 (0x83U << I2C_CTRL_CR0_Pos) /*!< 0x0000083 */ + +/************** Bits definition for I2C_STS register ******************/ +#define I2C_STS_STS_0x00 (0x0U << I2C_STS_STS_Pos) /*!< 0x0000000 */ +#define I2C_STS_STS_0x08 (0x1U << I2C_STS_STS_Pos) /*!< 0x0000008 */ +#define I2C_STS_STS_0x10 (0x2U << I2C_STS_STS_Pos) /*!< 0x0000010 */ +#define I2C_STS_STS_0x18 (0x3U << I2C_STS_STS_Pos) /*!< 0x0000018 */ +#define I2C_STS_STS_0x20 (0x4U << I2C_STS_STS_Pos) /*!< 0x0000020 */ +#define I2C_STS_STS_0x28 (0x5U << I2C_STS_STS_Pos) /*!< 0x0000028 */ +#define I2C_STS_STS_0x30 (0x6U << I2C_STS_STS_Pos) /*!< 0x0000030 */ +#define I2C_STS_STS_0x38 (0x7U << I2C_STS_STS_Pos) /*!< 0x0000038 */ +#define I2C_STS_STS_0x40 (0x8U << I2C_STS_STS_Pos) /*!< 0x0000040 */ +#define I2C_STS_STS_0x48 (0x9U << I2C_STS_STS_Pos) /*!< 0x0000048 */ +#define I2C_STS_STS_0x50 (0xAU << I2C_STS_STS_Pos) /*!< 0x0000050 */ +#define I2C_STS_STS_0x58 (0xBU << I2C_STS_STS_Pos) /*!< 0x0000058 */ +#define I2C_STS_STS_0x60 (0xCU << I2C_STS_STS_Pos) /*!< 0x0000060 */ +#define I2C_STS_STS_0x68 (0xDU << I2C_STS_STS_Pos) /*!< 0x0000068 */ +#define I2C_STS_STS_0x70 (0xEU << I2C_STS_STS_Pos) /*!< 0x0000070 */ +#define I2C_STS_STS_0x78 (0xFU << I2C_STS_STS_Pos) /*!< 0x0000078 */ +#define I2C_STS_STS_0x80 (0x10U << I2C_STS_STS_Pos) /*!< 0x0000080 */ +#define I2C_STS_STS_0x88 (0x11U << I2C_STS_STS_Pos) /*!< 0x0000088 */ +#define I2C_STS_STS_0x90 (0x12U << I2C_STS_STS_Pos) /*!< 0x0000090 */ +#define I2C_STS_STS_0x98 (0x13U << I2C_STS_STS_Pos) /*!< 0x0000098 */ +#define I2C_STS_STS_0xA0 (0x14U << I2C_STS_STS_Pos) /*!< 0x00000A0 */ +#define I2C_STS_STS_0xA8 (0x15U << I2C_STS_STS_Pos) /*!< 0x00000A8 */ +#define I2C_STS_STS_0xB0 (0x16U << I2C_STS_STS_Pos) /*!< 0x00000B0 */ +#define I2C_STS_STS_0xB8 (0x17U << I2C_STS_STS_Pos) /*!< 0x00000B8 */ +#define I2C_STS_STS_0xC0 (0x18U << I2C_STS_STS_Pos) /*!< 0x00000C0 */ +#define I2C_STS_STS_0xC8 (0x19U << I2C_STS_STS_Pos) /*!< 0x00000C8 */ +#define I2C_STS_STS_0xF8 (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */ + +//GeneralCallAck +#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC +#define I2C_GENERALCALLACK_DISABLE 0 +//AssertAcknowledge +#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA +#define I2C_ASSERTACKNOWLEDGE_DISABLE 0 +//ClockSource +#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0 +#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1 +#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2 +#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3 +#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4 +#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5 +#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6 +#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7 + +#define I2C_CTRL_CR (0x83) +typedef struct +{ + uint16_t SlaveAddr; + uint8_t SubAddrType; + uint32_t PageRange; + uint32_t SubAddress; + uint8_t *pBuffer; + uint32_t Length; +} I2C_WRType; +//SubAddrType +#define I2C_SUBADDR_1BYTE (1) +#define I2C_SUBADDR_2BYTE (2) +#define I2C_SUBADDR_OTHER (3) + +//remap +#define I2C_REMAP_ENABLE (1) +#define I2C_REMAP_DISABLE (0) + +/* Private macros ------------------------------------------------------------*/ + +#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\ + ((__GC__) == I2C_GENERALCALLACK_DISABLE)) + +#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\ + ((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE)) + +#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8)) + +#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\ + ((__TYPE__) == I2C_SUBADDR_2BYTE) ||\ + ((__TYPE__) == I2C_SUBADDR_OTHER)) + +/****************************** I2C Instances *********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C) + + +/* Exported Functions ------------------------------------------------------- */ +/* I2C Exported Functions Group1: + (De)Initialization ------------------------*/ +void I2C_DeInit(uint32_t remap); +void I2C_StructInit(I2C_InitType *InitStruct); +void I2C_Init(I2C_InitType *InitStruct); +/* I2C Exported Functions Group2: + Interrupt ---------------------------------*/ +void I2C_INTConfig(uint32_t NewState); +uint8_t I2C_GetINTStatus(void); +void I2C_ClearINTStatus(void); +/* I2C Exported Functions Group3: + Transfer datas ----------------------------*/ +uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct); +uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct); +/* I2C Exported Functions Group4: + MISC Configuration ------------------------*/ +void I2C_Cmd(uint32_t NewState); + +/* I2C Exported Functions Group5: + Others ------------------------------------*/ +void I2C_AssertAcknowledgeConfig(uint32_t NewState); +uint8_t I2C_ReceiveData(void); +void I2C_SendData(uint8_t Dat); +void I2C_GenerateSTART(uint32_t NewState); +void I2C_GenerateSTOP(uint32_t NewState); +uint8_t I2C_GetStatusCode(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_I2C_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_iso7816.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_iso7816.h new file mode 100644 index 0000000000..2c2cf10ba0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_iso7816.h @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file lib_iso7816.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief ISO7816 library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ISO7816_H +#define __LIB_ISO7816_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t FirstBit; + uint32_t Parity; + uint32_t Baudrate; + uint32_t TXRetry; + uint32_t RXACKLength; + uint32_t TXNACKLength; +} ISO7816_InitType; +//FirstBit +#define ISO7816_FIRSTBIT_MSB (0UL) +#define ISO7816_FIRSTBIT_LSB ISO7816_CFG_LSB +#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB) ||\ + ((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB)) +//Parity +#define ISO7816_PARITY_EVEN (0UL) +#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP +#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) ||\ + ((__PARITY__) == ISO7816_PARITY_ODD)) +//Baudrate +#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((200UL <= (__BAUDRATE__)) &&\ + ((__BAUDRATE__) <= 2625000UL)) +//TXRetry +#define ISO7816_TXRTY_0 ((0x00U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_1 ((0x01U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_2 ((0x02U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_3 ((0x03U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_4 ((0x04U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_5 ((0x05U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_6 ((0x06U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_7 ((0x07U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_8 ((0x08U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_9 ((0x09U << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_10 ((0x0AU << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_11 ((0x0BU << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_12 ((0x0CU << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_13 ((0x0DU << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_14 ((0x0EU << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define ISO7816_TXRTY_15 ((0x0FU << ISO7816_CFG_TXRTYCNT_Pos) \ + | (1U << 10)) +#define IS_ISO7816_TXRTY(__TXRTY__) (((__TXRTY__) == ISO7816_TXRTY_0) || \ + ((__TXRTY__) == ISO7816_TXRTY_1) || \ + ((__TXRTY__) == ISO7816_TXRTY_2) || \ + ((__TXRTY__) == ISO7816_TXRTY_3) || \ + ((__TXRTY__) == ISO7816_TXRTY_4) || \ + ((__TXRTY__) == ISO7816_TXRTY_5) || \ + ((__TXRTY__) == ISO7816_TXRTY_6) || \ + ((__TXRTY__) == ISO7816_TXRTY_7) || \ + ((__TXRTY__) == ISO7816_TXRTY_8) || \ + ((__TXRTY__) == ISO7816_TXRTY_9) || \ + ((__TXRTY__) == ISO7816_TXRTY_10) || \ + ((__TXRTY__) == ISO7816_TXRTY_11) || \ + ((__TXRTY__) == ISO7816_TXRTY_12) || \ + ((__TXRTY__) == ISO7816_TXRTY_13) || \ + ((__TXRTY__) == ISO7816_TXRTY_14) || \ + ((__TXRTY__) == ISO7816_TXRTY_15)) +//RXACKLength +#define ISO7816_RXACKLEN_2 (0UL) +#define ISO7816_RXACKLEN_1 (ISO7816_CFG_RXACKSET) +#define IS_ISO7816_RXACKLEN(__RXACKLEN__) (((__RXACKLEN__) == ISO7816_RXACKLEN_2) ||\ + ((__RXACKLEN__) == ISO7816_RXACKLEN_1)) +//TXNACKLength +#define ISO7816_TXNACKLEN_0 (0UL) +#define ISO7816_TXNACKLEN_1 (ISO7816_CFG_AUTORXACK) +#define ISO7816_TXNACKLEN_2 (ISO7816_CFG_AUTORXACK | ISO7816_CFG_ACKLEN) +#define IS_ISO7816_TXNACKLEN(__TXNACKLEN__) (((__TXNACKLEN__) == ISO7816_TXNACKLEN_0) ||\ + ((__TXNACKLEN__) == ISO7816_TXNACKLEN_1) ||\ + ((__TXNACKLEN__) == ISO7816_TXNACKLEN_2)) + +#define IS_ISO7816_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x80) + +//interrupt +#define ISO7816_INT_TXRTYERR ISO7816_CFG_TXRTYERRIE +#define ISO7816_INT_RXOV ISO7816_CFG_RXOVIE +#define ISO7816_INT_TXDONE ISO7816_CFG_TXDONEIE +#define ISO7816_INT_RX ISO7816_CFG_RXIE +#define ISO7816_INT_RXERR ISO7816_CFG_RXERRIE +#define ISO7816_INT_Msk (ISO7816_INT_TXRTYERR \ + |ISO7816_INT_RXOV \ + |ISO7816_INT_TXDONE \ + |ISO7816_INT_RX \ + |ISO7816_INT_RXERR) +#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\ + (((__INT__) & ~ISO7816_INT_Msk) == 0U)) + +//INTStatus +#define ISO7816_INTSTS_TXRTYERR ISO7816_INFO_TXRTYERRIF +#define ISO7816_INTSTS_RXOV ISO7816_INFO_RXOVIF +#define ISO7816_INTSTS_TXDONE ISO7816_INFO_TXDONEIF +#define ISO7816_INTSTS_RX ISO7816_INFO_RXIF +#define ISO7816_INTSTS_RXERR ISO7816_INFO_RXERRIF +#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_TXRTYERR \ + |ISO7816_INTSTS_RXOV \ + |ISO7816_INTSTS_TXDONE \ + |ISO7816_INTSTS_RX \ + |ISO7816_INTSTS_RXERR) +#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_TXRTYERR) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_TXDONE) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_RX) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_RXERR)) + +#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\ + (((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U)) +//status +#define ISO7816_FLAG_DMATXDONE ISO7816_INFO_DMATXDONE +#define IS_ISO7816_FLAGR(__FLAG__) ((__FLAG__) == ISO7816_FLAG_DMATXDONE) +#define IS_ISO7816_FLAGC(__FLAG__) ((__FLAG__) == ISO7816_FLAG_DMATXDONE) + +/****************************** ISO7816 Instances *****************************/ +#define IS_ISO7816_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ISO78160) || \ + ((INSTANCE) == ISO78161)) + +/* Exported Functions ------------------------------------------------------- */ +void ISO7816_DeInit(ISO7816_Type *ISO7816x); +void ISO7816_StructInit(ISO7816_InitType *InitStruct); +void ISO7816_Init(ISO7816_Type *ISO7816x, ISO7816_InitType *Init_Struct); +void ISO7816_Cmd(ISO7816_Type *ISO7816x, uint32_t NewState); +void ISO7816_BaudrateConfig(ISO7816_Type *ISO7816x, uint32_t BaudRate); +void ISO7816_CLKDIVConfig(ISO7816_Type *ISO7816x, uint32_t Prescaler); +void ISO7816_CLKOutputCmd(ISO7816_Type *ISO7816x, uint32_t NewState); +void ISO7816_SendData(ISO7816_Type *ISO7816x, uint8_t ch); +uint8_t ISO7816_ReceiveData(ISO7816_Type *ISO7816x); +void ISO7816_INTConfig(ISO7816_Type *ISO7816x, uint32_t INTMask, uint8_t NewState); +uint8_t ISO7816_GetINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask); +void ISO7816_ClearINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask); +uint8_t ISO7816_GetFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask); +void ISO7816_ClearFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask); +uint8_t ISO7816_GetLastTransmitACK(ISO7816_Type *ISO7816x); +uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_Type *ISO7816x); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ISO7816_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_lcd.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_lcd.h new file mode 100644 index 0000000000..836806a6a3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_lcd.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file lib_lcd.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief LCD library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_LCD_H +#define __LIB_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* LCD COMx IO typedef */ +typedef struct +{ + __IO uint32_t *GPIO; + uint16_t Pin; +}LCD_COMIO; + +typedef struct +{ + uint32_t Type; + uint32_t Drv; + uint32_t FRQ; + uint32_t SWPR; + uint32_t FBMODE; + uint32_t BKFILL; +} LCD_InitType; + +typedef struct +{ + uint32_t SegCtrl0; + uint32_t SegCtrl1; + uint16_t SegCtrl2; + uint32_t COMMode; +} LCD_IOInitType; + +/************** Bits definition for ANA_REG6 register ******************/ +#define ANA_REG6_VLCD_0 (0x0U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_1 (0x1U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_2 (0x2U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_3 (0x3U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_4 (0x4U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_5 (0x5U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_6 (0x6U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_7 (0x7U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_8 (0x8U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_9 (0x9U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_A (0xAU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_B (0xBU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_C (0xCU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_D (0xDU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_E (0xEU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_F (0xFU << ANA_REG6_VLCD_Pos) + +/************** Bits definition for LCD_CTRL register ******************/ + +/************** Bits definition for LCD_CTRL2 register ******************/ + +//Type +#define LCD_TYPE_4COM (0x0U << LCD_CTRL_TYPE_Pos) /*!< 0x00000000 */ +#define LCD_TYPE_6COM (0x1U << LCD_CTRL_TYPE_Pos) /*!< 0x00000010 */ +#define LCD_TYPE_8COM (0x2U << LCD_CTRL_TYPE_Pos) /*!< 0x00000020 */ +#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\ + ((__TYPE__) == LCD_TYPE_6COM) ||\ + ((__TYPE__) == LCD_TYPE_8COM)) + +//DrivingRes +#define LCD_DRV_300 (0x0U << LCD_CTRL_DRV_Pos) /*!< 0x00000000 */ +#define LCD_DRV_600 (0x1U << LCD_CTRL_DRV_Pos) /*!< 0x00000004 */ +#define LCD_DRV_150 (0x2U << LCD_CTRL_DRV_Pos) /*!< 0x00000008 */ +#define LCD_DRV_200 (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */ +#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\ + ((__DRV__) == LCD_DRV_600) ||\ + ((__DRV__) == LCD_DRV_150) ||\ + ((__DRV__) == LCD_DRV_200)) + +//ScanFRQ +#define LCD_FRQ_64H (0x0U << LCD_CTRL_FRQ_Pos) /*!< 0x00000000 */ +#define LCD_FRQ_128H (0x1U << LCD_CTRL_FRQ_Pos) /*!< 0x00000001 */ +#define LCD_FRQ_256H (0x2U << LCD_CTRL_FRQ_Pos) /*!< 0x00000002 */ +#define LCD_FRQ_512H (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */ +#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\ + ((__FRQ__) == LCD_FRQ_128H) ||\ + ((__FRQ__) == LCD_FRQ_256H) ||\ + ((__FRQ__) == LCD_FRQ_512H)) + +#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL) + +//SwitchMode +#define LCD_FBMODE_BUFA (0x0U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000000 */ +#define LCD_FBMODE_BUFAB (0x1U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000040 */ +#define LCD_FBMODE_BUFABLANK (0x2U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000080 */ +#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\ + ((__FBMODE__) == LCD_FBMODE_BUFAB) ||\ + ((__FBMODE__) == LCD_FBMODE_BUFABLANK)) + +//BlankFill +#define LCD_BKFILL_1 LCD_CTRL2_BKFILL +#define LCD_BKFILL_0 0 +#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0)) + +//BiasSelection +#define LCD_BMODE_DIV3 0 +#define LCD_BMODE_DIV4 ANA_REG6_LCDBMODE +#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\ + ((__BMODE__) == LCD_BMODE_DIV4)) + +/****************************** LCD Instances *********************************/ +#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) + +/* Exported Functions ------------------------------------------------------- */ +/* LCD Exported Functions Group1: + (De)Initialization -------------------------*/ +void LCD_DeInit(void); +void LCD_StructInit(LCD_InitType *LCD_InitStruct); +void LCD_Init(LCD_InitType *InitStruct); +/* LCD Exported Functions Group1: + MISC Configuration -------------------------*/ +void LCD_Cmd(LCD_IOInitType *IOInitType, uint32_t NewState); +void LCD_BiasModeConfig(uint32_t BiasSelection); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_LCD_H */ + +/*********************************** END OF FILE ******************************/ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_misc.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_misc.h new file mode 100644 index 0000000000..10169c4371 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_misc.h @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file lib_misc.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief MISC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_MISC_H +#define __LIB_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//FlagMask +#define MISC_FLAG_LOCKUP MISC1_SRAMINT_LOCKUP +#define MISC_FLAG_PIAC MISC1_SRAMINT_PIAC +#define MISC_FLAG_HIAC MISC1_SRAMINT_HIAC +#define MISC_FLAG_PERR MISC1_SRAMINT_PERR +#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR) + +//MISC interrupt +#define MISC_INT_LOCK MISC1_SRAMINIT_LOCKIE +#define MISC_INT_PIAC MISC1_SRAMINIT_PIACIE +#define MISC_INT_HIAC MISC1_SRAMINIT_HIACIE +#define MISC_INT_PERR MISC1_SRAMINIT_PERRIE +#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR) + +//IR +#define MISC_IREN_TX0 (0x01U << MISC1_IREN_IREN_Pos) +#define MISC_IREN_TX1 (0x02U << MISC1_IREN_IREN_Pos) +#define MISC_IREN_TX2 (0x04U << MISC1_IREN_IREN_Pos) +#define MISC_IREN_TX3 (0x08U << MISC1_IREN_IREN_Pos) +#define MISC_IREN_TX4 (0x10U << MISC1_IREN_IREN_Pos) +#define MISC_IREN_TX5 (0x20U << MISC1_IREN_IREN_Pos) +#define MISC_IREN_Msk (0x3FUL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\ + ((__FLAGR__) == MISC_FLAG_PIAC) ||\ + ((__FLAGR__) == MISC_FLAG_HIAC) ||\ + ((__FLAGR__) == MISC_FLAG_PERR)) + +#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\ + (((__FLAGC__) & ~MISC_FLAG_Msk) == 0U)) + +#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\ + (((__INT__) &~MISC_INT_Msk) == 0U)) + +#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\ + (((__IREN__) & ~MISC_IREN_Msk) == 0U)) + +/****************************** MISC Instances ********************************/ +#define IS_MISC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC1) + +#define IS_MISC2_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC2) + +/* Exported Functions ------------------------------------------------------- */ +uint8_t MISC_GetFlag(uint32_t FlagMask); +void MISC_ClearFlag(uint32_t FlagMask); +void MISC_INTConfig(uint32_t INTMask, uint32_t NewState); +void MISC_SRAMParityCmd(uint32_t NewState); +uint32_t MISC_GetSRAMPEAddr(void); +uint32_t MISC_GetAPBErrAddr(void); +uint32_t MISC_GetAHBErrAddr(void); +void MISC_IRCmd(uint32_t IRx, uint32_t NewState); +void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow); +void MISC_HardFaultCmd(uint32_t NewState); +void MISC_LockResetCmd(uint32_t NewState); +void MISC_IRQLATConfig(uint8_t Latency); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_MISC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_pmu.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_pmu.h new file mode 100644 index 0000000000..041eec5210 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_pmu.h @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file lib_pmu.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief PMU library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_PMU_H +#define __LIB_PMU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/** + * Deep-sleep low-power configuration +*/ +typedef struct +{ + uint32_t CMP1Power; /* Comparator 1 power control */ + uint32_t CMP2Power; /* Comparator 2 power control */ + uint32_t TADCPower; /* Tiny ADC power control */ + uint32_t BGPPower; /* BGP power control */ + uint32_t AVCCPower; /* AVCC power control */ +// uint32_t LCDPower; /* LCD controller power control */ + uint32_t VDCINDetector; /* VDCIN detector control */ + uint32_t VDDDetector; /* VDD detector control */ + uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */ + uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */ +} PMU_LowPWRTypeDef; + +/************** Bits definition for ANA_REG8 register ******************/ +#define ANA_REG8_VDDPVDSEL_0 (0x0UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_1 (0x1UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_2 (0x2UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_3 (0x3UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_4 (0x4UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_5 (0x5UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_6 (0x6UL << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_7 (0x7UL << ANA_REG8_VDDPVDSEL_Pos) + +/****************************** PMU Instances *********************************/ +#define IS_PMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU) + +/****************************** PMU_RETRAM Instances **************************/ +#define IS_PMU_RETRAM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU_RETRAM) + +/* CMP1Power */ +#define PMU_CMP1PWR_ON (ANA_REG3_CMP1PDN) +#define PMU_CMP1PWR_OFF (0UL) +#define IS_PMU_COMP1PWR(__CMP1PWR__) (((__CMP1PWR__) == PMU_CMP1PWR_ON) ||\ + ((__CMP1PWR__) == PMU_CMP1PWR_OFF)) +/* CMP2Power */ +#define PMU_CMP2PWR_ON (ANA_REG3_CMP2PDN) +#define PMU_CMP2PWR_OFF (0UL) +#define IS_PMU_COMP2PWR(__CMP2PWR__) (((__CMP2PWR__) == PMU_CMP2PWR_ON) ||\ + ((__CMP2PWR__) == PMU_CMP2PWR_OFF)) +/* TADCPower */ +#define PMU_TADCPWR_ON (ANA_REGF_ADTPDN) +#define PMU_TADCPWR_OFF (0UL) +#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\ + ((__TADCPWR__) == PMU_TADCPWR_OFF)) +/* BGPPower */ +#define PMU_BGPPWR_ON (0UL) +#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD) +#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\ + ((__BGPPWR__) == PMU_BGPPWR_OFF)) +/* AVCCPower */ +#define PMU_AVCCPWR_ON (0UL) +#define PMU_AVCCPWR_OFF (ANA_REG8_AVCCLDOPD) +#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\ + ((__AVCCPWR__) == PMU_AVCCPWR_OFF)) + +/* VDCINDetector */ +#define PMU_VDCINDET_ENABLE (0UL) +#define PMU_VDCINDET_DISABLE (ANA_REGA_VDCINDETPD) +#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\ + ((__VDCINDET__) == PMU_VDCINDET_DISABLE)) + +/* VDDDetector */ +#define PMU_VDDDET_ENABLE (0UL) +#define PMU_VDDDET_DISABLE (ANA_REG9_VDDDETPD) +#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\ + ((__VDDDET__) == PMU_VDDDET_DISABLE)) + +#define PMU_APB_ALL (MISC2_PCLKEN_DMA \ + |MISC2_PCLKEN_I2C \ + |MISC2_PCLKEN_SPI1 \ + |MISC2_PCLKEN_UART0 \ + |MISC2_PCLKEN_UART1 \ + |MISC2_PCLKEN_UART2 \ + |MISC2_PCLKEN_UART3 \ + |MISC2_PCLKEN_UART4 \ + |MISC2_PCLKEN_UART5 \ + |MISC2_PCLKEN_ISO78160 \ + |MISC2_PCLKEN_ISO78161 \ + |MISC2_PCLKEN_TIMER \ + |MISC2_PCLKEN_MISC1 \ + |MISC2_PCLKEN_MISC2 \ + |MISC2_PCLKEN_U32K0 \ + |MISC2_PCLKEN_U32K1 \ + |MISC2_PCLKEN_SPI2 \ + |MISC2_PCLKEN_SPI3) +#define PMU_APB_DMA MISC2_PCLKEN_DMA +#define PMU_APB_I2C MISC2_PCLKEN_I2C +#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1 +#define PMU_APB_UART0 MISC2_PCLKEN_UART0 +#define PMU_APB_UART1 MISC2_PCLKEN_UART1 +#define PMU_APB_UART2 MISC2_PCLKEN_UART2 +#define PMU_APB_UART3 MISC2_PCLKEN_UART3 +#define PMU_APB_UART4 MISC2_PCLKEN_UART4 +#define PMU_APB_UART5 MISC2_PCLKEN_UART5 +#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160 +#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161 +#define PMU_APB_TIMER MISC2_PCLKEN_TIMER +#define PMU_APB_MISC1 MISC2_PCLKEN_MISC1 +#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0 +#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1 +#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2 +#define PMU_APB_SPI3 MISC2_PCLKEN_SPI3 + +#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \ + |MISC2_HCLKEN_GPIO \ + |MISC2_HCLKEN_CRYPT \ + |MISC2_HCLKEN_LCD) +#define PMU_AHB_DMA MISC2_HCLKEN_DMA +#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO +#define PMU_AHB_LCD MISC2_HCLKEN_LCD +#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT + +//PMU interrupt +#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN +#define PMU_INT_32K PMU_CONTROL_INT_32K_EN +#define PMU_INT_6M PMU_CONTROL_INT_6M_EN +#define PMU_INT_Msk (PMU_INT_IOAEN \ + |PMU_INT_32K \ + |PMU_INT_6M) +#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0UL) &&\ + (((__INT__)&(~PMU_INT_Msk)) == 0UL)) + +//INTStatus +#define PMU_INTSTS_32K PMU_STS_INT_32K +#define PMU_INTSTS_6M PMU_STS_INT_6M +#define PMU_INTSTS_Msk (PMU_INTSTS_32K \ + |PMU_INTSTS_6M) +#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\ + ((__INTFLAG__) == PMU_INTSTS_6M)) + +#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0UL) &&\ + (((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0UL)) + +/***** Reset Source Status *****/ +#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST +#define PMU_RSTSRC_PORST PMU_STS_PORST +#define PMU_RSTSRC_DPORST PMU_STS_DPORST +#define PMU_RSTSRC_WDTRST PMU_STS_WDTRST +#define PMU_RSTSRC_SFTRST PMU_STS_SFTRST +#define PMU_RSTSRC_MODERST PMU_STS_MODERST +#define PMU_RSTSRC_Msk (PMU_RSTSRC_EXTRST |\ + PMU_RSTSRC_PORST |\ + PMU_RSTSRC_DPORST |\ + PMU_RSTSRC_WDTRST |\ + PMU_RSTSRC_SFTRST |\ + PMU_RSTSRC_MODERST) +#define PMU_RSTSRC_ALL PMU_RSTSRC_Msk +#define PMU_RESETSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_PORST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_DPORST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_WDTRST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_SFTRST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_MODERST)) +#define PMU_RESETSRC_CLR(__RSTSRC__) ((((__RSTSRC__) & PMU_RSTSRC_Msk) != 0UL) &&\ + (((__RSTSRC__) & (~PMU_RSTSRC_Msk)) == 0UL)) + +/***** DeepSleep wakeup Source Status *****/ +#define PMU_DSLEEPWKUSRC_MODE PMU_STS_WKUMODE +#define PMU_DSLEEPWKUSRC_XTAL PMU_STS_WKUXTAL +#define PMU_DSLEEPWKUSRC_U32K PMU_STS_WKUU32K +#define PMU_DSLEEPWKUSRC_ANA PMU_STS_WKUANA +#define PMU_DSLEEPWKUSRC_RTC PMU_STS_WKURTC +#define PMU_DSLEEPWKUSRC_IOA PMU_STS_WKUIOA +#define PMU_DSLEEPWKUSRC_Msk (PMU_DSLEEPWKUSRC_MODE |\ + PMU_DSLEEPWKUSRC_XTAL |\ + PMU_DSLEEPWKUSRC_U32K |\ + PMU_DSLEEPWKUSRC_ANA |\ + PMU_DSLEEPWKUSRC_RTC |\ + PMU_DSLEEPWKUSRC_IOA) +#define IS_PMU_DSLEEPWKUSRC(__SRC__) (((__SRC__) == PMU_DSLEEPWKUSRC_MODE) ||\ + ((__SRC__) == PMU_DSLEEPWKUSRC_XTAL) ||\ + ((__SRC__) == PMU_DSLEEPWKUSRC_U32K) ||\ + ((__SRC__) == PMU_DSLEEPWKUSRC_ANA) ||\ + ((__SRC__) == PMU_DSLEEPWKUSRC_RTC) ||\ + ((__SRC__) == PMU_DSLEEPWKUSRC_IOA)) + + +//Status +#define PMU_STS_32K PMU_STS_EXIST_32K +#define PMU_STS_6M PMU_STS_EXIST_6M +#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M)) + +//Wakeup_Event +#define IOA_DISABLE (0UL) +#define IOA_RISING (1UL) +#define IOA_FALLING (2UL) +#define IOA_HIGH (3UL) +#define IOA_LOW (4UL) +#define IOA_EDGEBOTH (5UL) +#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\ + ((__WAKEUP__) == IOA_RISING) ||\ + ((__WAKEUP__) == IOA_FALLING) ||\ + ((__WAKEUP__) == IOA_HIGH) ||\ + ((__WAKEUP__) == IOA_LOW) ||\ + ((__WAKEUP__) == IOA_EDGEBOTH)) + +/***** Wakeup_Event (PMU_SleepWKUSRCConfig_RTC) *****/ +#define PMU_RTCEVT_ALARM RTC_INTSTS_INTSTS10 +#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6 +#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5 +#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4 +#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3 +#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2 +#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1 +#define PMU_RTCEVT_ITVSITV RTC_INTSTS_INTSTS0 +#define PMU_RTCEVT_Msk (PMU_RTCEVT_WKUCNT \ + |PMU_RTCEVT_MIDNIGHT \ + |PMU_RTCEVT_WKUHOUR \ + |PMU_RTCEVT_WKUMIN \ + |PMU_RTCEVT_WKUSEC \ + |PMU_RTCEVT_TIMEILLE \ + |PMU_RTCEVT_ITVSITV \ + |PMU_RTCEVT_ALARM) +#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0UL) &&\ + (((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0UL)) + + +/***** BATRTCDisc (PMU_BATDischargeConfig) *****/ +#define PMU_BAT1 ANA_REG6_BAT1DISC +#define PMU_BATRTC ANA_REG6_BATRTCDISC +#define IS_PMU_BATRTCDISC(__BATRTCDISC__) (((__BATRTCDISC__) == PMU_BAT1) || ((__BATRTCDISC__) == PMU_BATRTC)) + +/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/ +#define PMU_VDDALARM_4_5V ANA_REG8_VDDPVDSEL_0 +#define PMU_VDDALARM_4_2V ANA_REG8_VDDPVDSEL_1 +#define PMU_VDDALARM_3_9V ANA_REG8_VDDPVDSEL_2 +#define PMU_VDDALARM_3_6V ANA_REG8_VDDPVDSEL_3 +#define PMU_VDDALARM_3_2V ANA_REG8_VDDPVDSEL_4 +#define PMU_VDDALARM_2_9V ANA_REG8_VDDPVDSEL_5 +#define PMU_VDDALARM_2_6V ANA_REG8_VDDPVDSEL_6 +#define PMU_VDDALARM_2_3V ANA_REG8_VDDPVDSEL_7 + +#define IS_PMU_VDDALARM_THR(__VDDALARM__) (((__VDDALARM__) == PMU_VDDALARM_4_5V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_4_2V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_3_9V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_3_6V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_3_2V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_2_9V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_2_6V) ||\ + ((__VDDALARM__) == PMU_VDDALARM_2_3V)) + +/***** RTCLDOSel (PMU_RTCLDOConfig) *****/ +#define PMU_RTCLDO_1_5 (0UL) +#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL + +/***** StatusMask (PMU_GetPowerStatus) *****/ +#define PMU_PWRSTS_AVCCLV ANA_CMPOUT_AVCCLV +#define PMU_PWRSTS_VDCINDROP ANA_CMPOUT_VDCINDROP +#define PMU_PWRSTS_VDDALARM ANA_CMPOUT_VDDALARM + +/***** PMU_PDNDSleepConfig *****/ +//VDCIN_PDNS +#define PMU_VDCINPDNS_0 (0UL) +#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS) +#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\ + ((__VDCINPDNS__) == PMU_VDCINPDNS_1)) +//VDD_PDNS +#define PMU_VDDPDNS_0 (0UL) +#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2) +#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\ + ((__VDDPDNS__) == PMU_VDDPDNS_1)) + +#define PMU_VDDALARM_CHKFRE_NOCHECK (0x0UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos) +#define PMU_VDDALARM_CHKFRE_30US (0x1UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos) +#define IS_PMU_VDDALARM_CHKFRE(__CHKFRE__) (((__CHKFRE__) == PMU_VDDALARM_CHKFRE_NOCHECK) ||\ + ((__CHKFRE__) == PMU_VDDALARM_CHKFRE_30US)) + +#define IS_PMU_PWR_DEBSEL(__DEBSEL__) ((__DEBSEL__) < 256UL) + +#define PMU_VDCINHYSSEL_100MV (0x0UL << ANA_REG7_VDCINHYSSEL_Pos) +#define PMU_VDCINHYSSEL_200MV (0x1UL << ANA_REG7_VDCINHYSSEL_Pos) +#define IS_PMU_VDCIN_HYSSEL(__HYSSEL__) (((__HYSSEL__) == PMU_VDCINHYSSEL_100MV) ||\ + ((__HYSSEL__) == PMU_VDCINHYSSEL_200MV)) +/* Exported Functions ------------------------------------------------------- */ + +uint32_t PMU_EnterDSleepMode(void); +void PMU_EnterIdleMode(void); +uint32_t PMU_EnterSleepMode(void); + +void PMU_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t PMU_GetINTStatus(uint32_t INTMask); +void PMU_ClearINTStatus(uint32_t INTMask); + +uint8_t PMU_GetCrystalStatus(uint32_t Mask); +uint16_t PMU_GetIOAAllINTStatus(void); +uint8_t PMU_GetIOAINTStatus(uint16_t INTMask); +void PMU_ClearIOAINTStatus(uint16_t INTMask); + +void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event); + +uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); +uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); +#ifndef __GNUC__ +void PMU_EnterIdle_LowPower(void); +#endif +void PMU_SleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority); +void PMU_SleepWKUSRCConfig_RTC(uint32_t Wakeup_Event, uint32_t Priority); +void PMU_DeepSleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event); +void PMU_DeepSleepWKUSRCConfig_RTC(uint32_t Wakeup_Event); +void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS); + +/***** BGP functions *****/ +void PMU_BGPCmd(uint32_t NewState); + +/***** VDD functions *****/ +void PMU_VDDAlarmConfig(uint32_t CheckTHR, uint32_t CheckFrequency); +uint8_t PMU_GetVDDAlarmStatus(void); + +/***** AVCC functions *****/ +void PMU_AVCCCmd(uint32_t NewState); +void PMU_AVCCOutputCmd(uint32_t NewState); +void PMU_AVCCLVDetectorCmd(uint32_t NewState); +uint8_t PMU_GetAVCCLVStatus(void); + +/***** VDCIN functions *****/ +void PMU_VDCINDetectorCmd(uint32_t NewState); +void PMU_VDCINHYSSEL(uint32_t HYSSEL); +uint8_t PMU_GetVDCINDropStatus(void); + +void PMU_PWRDEBSel(uint32_t DEBSel); + +/***** BAT functions *****/ +void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState); + +/***** Other functions *****/ +uint8_t PMU_GetModeStatus(void); +uint8_t PMU_GetPowerStatus(uint32_t StatusMask); + +uint8_t PMU_GetResetSource(uint32_t Mask); +void PMU_ClearResetSource(uint32_t Mask); +uint32_t PMU_GetAllResetSource(void); + +uint8_t PMU_GetDSleepWKUSource(uint32_t Mask); +uint32_t PMU_GetAllDSleepWKUSource(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_PMU_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_pwm.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_pwm.h new file mode 100644 index 0000000000..1b194514bb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_pwm.h @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * @file lib_pwm.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief PWM library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_PWM_H +#define __LIB_PWM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t ClockDivision; + uint32_t Mode; + uint32_t ClockSource; +} PWM_BaseInitType; + +/************** Bits definition for PWMx_CTL register ******************/ +#define PWM_CTL_TESL_APBDIV128 (0x0U << PWM_CTL_TSEL_Pos) /*!< 0x00000000 */ +#define PWM_CTL_TESL_APBDIV1 (0x1U << PWM_CTL_TSEL_Pos) /*!< 0x00000008 */ +#define PWM_CTL_MC_STOP (0x0U << PWM_CTL_MC_Pos) /*!< 0x00000000 */ +#define PWM_CTL_MC_UP (0x1U << PWM_CTL_MC_Pos) /*!< 0x00000010 */ +#define PWM_CTL_MC_CONTINUE (0x2U << PWM_CTL_MC_Pos) /*!< 0x00000020 */ +#define PWM_CTL_MC_UPDOWN (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */ +#define PWM_CTL_ID_DIV2 (0x0U << PWM_CTL_ID_Pos) /*!< 0x00000000 */ +#define PWM_CTL_ID_DIV4 (0x1U << PWM_CTL_ID_Pos) /*!< 0x00000040 */ +#define PWM_CTL_ID_DIV8 (0x2U << PWM_CTL_ID_Pos) /*!< 0x00000080 */ +#define PWM_CTL_ID_DIV16 (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */ + +/************** Bits definition for PWMx_TAR register ******************/ + +/************** Bits definition for PWMx_CCTLy register ******************/ +////////////#define PWM_CCTL_OUTMOD_CONST (0x00UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_SET (0x01UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE_RESET (0x02UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_SET_RESET (0x03UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE (0x04UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_RESET (0x05UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE_SET (0x06UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_RESET_SET (0x07UL << PWM_CCTL_OUTMOD_Pos) +//////////////////// + +//ClockDivision +#define PWM_CLKDIV_2 (0x0U << PWM_CTL_ID_Pos) +#define PWM_CLKDIV_4 (0x1U << PWM_CTL_ID_Pos) +#define PWM_CLKDIV_8 (0x2U << PWM_CTL_ID_Pos) +#define PWM_CLKDIV_16 (0x3U << PWM_CTL_ID_Pos) +#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\ + ((__CLKDIV__) == PWM_CLKDIV_4) ||\ + ((__CLKDIV__) == PWM_CLKDIV_8) ||\ + ((__CLKDIV__) == PWM_CLKDIV_16)) + +//Mode +#define PWM_MODE_STOP (0x0U << PWM_CTL_MC_Pos) +#define PWM_MODE_UPCOUNT (0x1U << PWM_CTL_MC_Pos) +#define PWM_MODE_CONTINUOUS (0x2U << PWM_CTL_MC_Pos) +#define PWM_MODE_UPDOWN (0x3U << PWM_CTL_MC_Pos) +#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\ + ((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\ + ((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\ + ((__CNTMODE__) == PWM_MODE_UPDOWN)) + +//ClockSource +#define PWM_CLKSRC_APB (0x1U << PWM_CTL_TSEL_Pos) +#define PWM_CLKSRC_APBD128 (0x0U << PWM_CTL_TSEL_Pos) +#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\ + ((__CLKSRC__) == PWM_CLKSRC_APBD128)) + +typedef struct +{ + uint32_t Channel; + uint32_t Period; + uint32_t OutMode; +} PWM_OCInitType; +typedef struct +{ + uint32_t Channel; + uint32_t CaptureMode; +} PWM_ICInitType; +//Channel +#define PWM_CHANNEL_0 (0UL) +#define PWM_CHANNEL_1 (1UL) +#define PWM_CHANNEL_2 (2UL) +#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\ + ((__CHANNEL__) == PWM_CHANNEL_1) ||\ + ((__CHANNEL__) == PWM_CHANNEL_2)) +//OutMode +#define PWM_OUTMOD_CONST (0x0U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_SET (0x1U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_TOGGLE_RESET (0x2U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_SET_RESET (0x3U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_TOGGLE (0x4U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_RESET (0x5U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_TOGGLE_SET (0x6U << PWM_CCTL_OUTMOD_Pos) +#define PWM_OUTMOD_RESET_SET (0x7U << PWM_CCTL_OUTMOD_Pos) +#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\ + ((__OUTMODE__) == PWM_OUTMOD_SET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\ + ((__OUTMODE__) == PWM_OUTMOD_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_RESET_SET)) + +//CaptureMode +#define PWM_CM_DISABLE (0x0U << PWM_CCTL_CM_Pos) +#define PWM_CM_RISING (0x1U << PWM_CCTL_CM_Pos) +#define PWM_CM_FALLING (0x2U << PWM_CCTL_CM_Pos) +#define PWM_CM_BOTH (0x3U << PWM_CCTL_CM_Pos) +#define IS_PWM_CAPMODE(__CAPMODE__) (((__CAPMODE__) == PWM_CM_DISABLE) ||\ + ((__CAPMODE__) == PWM_CM_RISING) ||\ + ((__CAPMODE__) == PWM_CM_FALLING) ||\ + ((__CAPMODE__) == PWM_CM_BOTH)) + +//Interrupt +#define PWM_INT_CCIFG PWM_CCTL_CCIFG +#define PWM_INT_COV PWM_CCTL_COV +#define PWM_INT_Msk (PWM_INT_CCIFG | PWM_INT_COV) +#define IS_PWM_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == PWM_INT_CCIFG) ||\ + ((__INTFLAGR__) == PWM_INT_COV)) +#define IS_PWM_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & PWM_INT_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~PWM_INT_Msk) == 0U)) + +//PWM output selection +#define PWM0_OUT0 0 +#define PWM0_OUT1 1 +#define PWM0_OUT2 2 +#define PWM1_OUT0 4 +#define PWM1_OUT1 5 +#define PWM1_OUT2 6 +#define PWM2_OUT0 8 +#define PWM2_OUT1 9 +#define PWM2_OUT2 10 +#define PWM3_OUT0 12 +#define PWM3_OUT1 13 +#define PWM3_OUT2 14 +#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\ + ((__OUTSEL__) == PWM0_OUT1) ||\ + ((__OUTSEL__) == PWM0_OUT2) ||\ + ((__OUTSEL__) == PWM1_OUT0) ||\ + ((__OUTSEL__) == PWM1_OUT1) ||\ + ((__OUTSEL__) == PWM1_OUT2) ||\ + ((__OUTSEL__) == PWM2_OUT0) ||\ + ((__OUTSEL__) == PWM2_OUT1) ||\ + ((__OUTSEL__) == PWM2_OUT2) ||\ + ((__OUTSEL__) == PWM3_OUT0) ||\ + ((__OUTSEL__) == PWM3_OUT1) ||\ + ((__OUTSEL__) == PWM3_OUT2)) + +//outline +#define PWM_OLINE_0 1 +#define PWM_OLINE_1 2 +#define PWM_OLINE_2 4 +#define PWM_OLINE_3 8 +#define PWM_OLINE_Msk 0xF +#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\ + (((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U)) + +//inline +#define PWM_ILINE_0 0 +#define PWM_ILINE_1 1 +#define PWM_ILINE_2 2 +#define PWM_ILINE_3 3 +#define IS_PWM_INLINE(__INLINE__) (((__INLINE__) == PWM_ILINE_0) ||\ + ((__INLINE__) == PWM_ILINE_1) ||\ + ((__INLINE__) == PWM_ILINE_2) ||\ + ((__INLINE__) == PWM_ILINE_3)) + +//PWM input selection +#define PWM1_IN2 0x014 +#define PWM1_IN1 0x012 +#define PWM1_IN0 0x010 +#define PWM0_IN2 0x004 +#define PWM0_IN1 0x002 +#define PWM0_IN0 0x000 +#define PWM3_IN2 0x114 +#define PWM3_IN1 0x112 +#define PWM3_IN0 0x110 +#define PWM2_IN2 0x104 +#define PWM2_IN1 0x102 +#define PWM2_IN0 0x100 +#define IS_PWM_INSEL(__INSEL__) (((__INSEL__) == PWM1_IN2) ||\ + ((__INSEL__) == PWM1_IN1) ||\ + ((__INSEL__) == PWM1_IN0) ||\ + ((__INSEL__) == PWM0_IN2) ||\ + ((__INSEL__) == PWM0_IN1) ||\ + ((__INSEL__) == PWM0_IN0) ||\ + ((__INSEL__) == PWM3_IN2) ||\ + ((__INSEL__) == PWM3_IN1) ||\ + ((__INSEL__) == PWM3_IN0) ||\ + ((__INSEL__) == PWM2_IN2) ||\ + ((__INSEL__) == PWM2_IN1) ||\ + ((__INSEL__) == PWM2_IN0)) + +//Level +#define PWM_LEVEL_HIGH (0x1U << PWM_CCTL_OUT_Pos) +#define PWM_LEVEL_LOW 0 +#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\ + ((__OUTLVL__) == PWM_LEVEL_LOW)) + +#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U) + + +/****************************** PWM Instances *********************************/ +#define IS_PWM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PWM0) || \ + ((INSTANCE) == PWM1) || \ + ((INSTANCE) == PWM2) || \ + ((INSTANCE) == PWM3)) + +#define IS_PWMMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PWMMUX) + +/* Exported Functions ------------------------------------------------------- */ +/* PWM Exported Functions Group1: + Initialization ----------------------------*/ +void PWM_BaseInit(PWM_Type *PWMx, PWM_BaseInitType *InitStruct); +void PWM_BaseStructInit(PWM_BaseInitType *InitStruct); +void PWM_OCStructInit(PWM_OCInitType *OCInitType); +void PWM_OCInit(PWM_Type *PWMx, PWM_OCInitType *OCInitType); +void PWM_ICStructInit(PWM_ICInitType *ICInitType); +void PWM_ICInit(PWM_Type *PWMx, PWM_ICInitType *ICInitType); +/* PWM Exported Functions Group2: + Interrupt ---------------------------------*/ +void PWM_BaseINTConfig(PWM_Type *PWMx, uint32_t NewState); +uint8_t PWM_GetBaseINTStatus(PWM_Type *PWMx); +void PWM_ClearBaseINTStatus(PWM_Type *PWMx); +void PWM_ChannelINTConfig(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState); +uint8_t PWM_GetChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask); +void PWM_ClearChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask); +/* PWM Exported Functions Group3: + MISC --------------------------------------*/ +void PWM_ClearCounter(PWM_Type *PWMx); +void PWM_CCRConfig(PWM_Type *PWMx, uint32_t Channel, uint16_t Period); +//Compare output +void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine); +void PWM_OutputCmd(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState); +void PWM_SetOutLevel(PWM_Type *PWMx, uint32_t Channel, uint32_t Level); +void PWM_ILineConfig(uint32_t InSelection, uint32_t ILine); +uint8_t PWM_GetSCCI(PWM_Type *PWMx, uint32_t Channel); +uint32_t PWM_GetCapture(PWM_Type *PWMx, uint32_t Channel); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_PWM_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_rtc.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_rtc.h new file mode 100644 index 0000000000..b56aed2b29 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_rtc.h @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file lib_rtc.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief RTC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_RTC_H +#define __LIB_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* RTC Time struct */ +typedef struct +{ + uint32_t Year; + uint32_t Month; + uint32_t Date; + uint32_t WeekDay; + uint32_t Hours; + uint32_t Minutes; + uint32_t Seconds; + uint32_t SubSeconds; +} RTC_TimeTypeDef; + +/* RTC Alarm Time struct */ +typedef struct +{ + uint32_t AlarmHours; + uint32_t AlarmMinutes; + uint32_t AlarmSeconds; + uint32_t AlarmSubSeconds; +}RTC_AlarmTypeDef; + +#define RTC_ACCURATE 0 +#define RTC_INACCURATE 1 +#define IS_RTC_ACCURATESEL(__ACCURATESEL__) (((__ACCURATESEL__) == RTC_ACCURATE) ||\ + ((__ACCURATESEL__) == RTC_INACCURATE)) + +/************** Bits definition for RTC_WKUCNT register ******************/ +#define RTC_WKUCNT_CNTSEL_0 (0x0U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_1 (0x1U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_2 (0x2U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_3 (0x3U << RTC_WKUCNT_CNTSEL_Pos) + +/************** Bits definition for RTC_PSCA register ******************/ +#define RTC_PSCA_PSCA_0 (0x0U << RTC_PSCA_PSCA_Pos) +#define RTC_PSCA_PSCA_1 (0x1U << RTC_PSCA_PSCA_Pos) +//#define RTC_PSCA_PSCA_2 (0x2U << RTC_PSCA_PSCA_Pos) +//#define RTC_PSCA_PSCA_3 (0x3U << RTC_PSCA_PSCA_Pos) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +//INT +#define RTC_INT_ALARM RTC_INTSTS_INTSTS10 +#define RTC_INT_CEILLE RTC_INTSTS_INTSTS8 +#define RTC_INT_WKUCNT RTC_INTSTS_INTSTS6 +#define RTC_INT_MIDNIGHT RTC_INTSTS_INTSTS5 +#define RTC_INT_WKUHOUR RTC_INTSTS_INTSTS4 +#define RTC_INT_WKUMIN RTC_INTSTS_INTSTS3 +#define RTC_INT_WKUSEC RTC_INTSTS_INTSTS2 +#define RTC_INT_TIMEILLE RTC_INTSTS_INTSTS1 +#define RTC_INT_ITVSITV RTC_INTSTS_INTSTS0 +#define RTC_INT_Msk (0x57FUL) + +//INTSTS +#define RTC_INTSTS_ALARM RTC_INTSTS_INTSTS10 +#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8 +#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6 +#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5 +#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4 +#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3 +#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2 +#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1 +#define RTC_INTSTS_ITVSITV RTC_INTSTS_INTSTS0 +#define RTC_INTSTS_Msk (0x57FUL) + +//CNTCLK +#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0 +#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1 +#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2 +#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3 + +//Prescaler +#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0 +#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1 + +//PLLDIVSOUCE +#define RTC_PLLDIVSOURCE_PCLK 0 +#define RTC_PLLDIVSOURCE_PLLL (0x1U << RTC_CTL_RTCPLLCLKSEL_Pos) + +//RTC_ITV +#define RTC_ITV_SEC (0x80) +#define RTC_ITV_MIN (1 << RTC_ITV_ITV_Pos) +#define RTC_ITV_HOUR (2 << RTC_ITV_ITV_Pos) +#define RTC_ITV_DAY (3 << RTC_ITV_ITV_Pos) +#define RTC_ITV_500MS (4 << RTC_ITV_ITV_Pos) +#define RTC_ITV_250MS (5 << RTC_ITV_ITV_Pos) +#define RTC_ITV_125MS (6 << RTC_ITV_ITV_Pos) +#define RTC_ITV_62MS (7 << RTC_ITV_ITV_Pos) +#define RTC_ITV_SITVSEC (7 << RTC_ITV_ITV_Pos) +//RTC_SITV +#define RTC_SITV_EN (1 << RTC_SITV_SITVEN_Pos) //Control Multi Second interval.1:enable; 0:disable. + +/* Private macros ------------------------------------------------------------*/ +#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U) +/* Year 0 ~ 99 */ +#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU) +/* Month 1 ~ 12 */ +#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U)) +/* Date 1 ~ 31 */ +#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32U)) +/* Weekday 0 ~ 6 */ +#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U) +/* Hours 0 ~ 23 */ +#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24U) +/* Minutes 0 ~ 59 */ +#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5AU) +/* Seconds 0 ~ 59 */ +#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5AU) +/* SubSeconds 0 ~ 0x999 */ +#define IS_RTC_TIME_SubSECS(__SubSECS__) ((__SubSECS__) < 0x1000U) + +#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\ + (((__INT__) & ~RTC_INT_Msk) == 0U)) + +#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\ + ((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\ + ((__INTFLAGR_) == RTC_INTSTS_ALARM) ||\ + ((__INTFLAGR_) == RTC_INTSTS_TIMEILLE) ||\ + ((__INTFLAGR_) == RTC_INTSTS_ITVSITV)) + +#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U)) + +#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) (((__PERIOD__) < 0x21U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) (((__PERIOD__) < 0x1000001U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\ + ((__CNTSEL__) == RTC_WKUCNT_2048) ||\ + ((__CNTSEL__) == RTC_WKUCNT_512) ||\ + ((__CNTSEL__) == RTC_WKUCNT_128)) + +#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\ + ((__CLKDIV__) == RTC_CLKDIV_4)) + +#define IS_RTC_PLLDIVSOURCE(__PLLDIVSOURCE__) (((__PLLDIVSOURCE__) == RTC_PLLDIVSOURCE_PCLK) ||\ + ((__PLLDIVSOURCE__) == RTC_PLLDIVSOURCE_PLLL)) + +#define IS_RTC_ITV(__ITV__) (((__ITV__) == RTC_ITV_SEC) ||\ + ((__ITV__) == RTC_ITV_MIN) ||\ + ((__ITV__) == RTC_ITV_HOUR) ||\ + ((__ITV__) == RTC_ITV_DAY) ||\ + ((__ITV__) == RTC_ITV_500MS) ||\ + ((__ITV__) == RTC_ITV_250MS) ||\ + ((__ITV__) == RTC_ITV_125MS) ||\ + ((__ITV__) == RTC_ITV_62MS) ||\ + ((__ITV__) == RTC_ITV_SITVSEC)) + +#define IS_RTC_SITV(__SITV__) (((__SITV__) < 65U) && ((__SITV__) > 0U)) + +/* Exported Functions ------------------------------------------------------- */ +/* RTC Exported Functions Group1: + Time functions -----------------------------*/ +void RTC_SetTime(RTC_TimeTypeDef *sTime, uint32_t AccurateSel); +void RTC_GetTime(RTC_TimeTypeDef *gTime, uint32_t AccurateSel); +void RTC_SubSecondCmd(uint32_t NewState); +/* RTC Exported Functions Group2: + Alarms configuration functions -------------*/ +void RTC_SetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel); +void RTC_GetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel); +void RTC_AlarmCmd(uint32_t NewState); +void RTC_AlarmAccurateCmd(uint32_t NewState); +/* RTC Exported Functions Group3: + Registers operation functions --------------*/ +void RTC_WriteProtection(uint32_t NewState); +void RTC_WaitForSynchro(void); +void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len); +void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len); +/* RTC Exported Functions Group4: + Interrupt functions ------------------------*/ +void RTC_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t RTC_GetINTStatus(uint32_t FlagMask); +void RTC_ClearINTStatus(uint32_t FlagMask); + +/* RTC Exported Functions Group5: + Wake-up functions --------------------------*/ +void RTC_WKUSecondsConfig(uint8_t nPeriod); +void RTC_WKUMinutesConfig(uint8_t nPeriod); +void RTC_WKUHoursConfig(uint8_t nPeriod); +void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK); +void RTC_WAKE_ITV(uint8_t nType); +void RTC_WAKE_SITV(uint8_t nPeriod); +uint32_t RTC_GetWKUCounterValue(void); +/* RTC Exported Functions Group6: + MISC functions -----------------------------*/ +void RTC_PrescalerConfig(uint32_t Prescaler); +void RTC_PLLDIVConfig(uint32_t DIVSource,uint32_t nfrequency); +void RTC_PLLDIVOutputCmd(uint8_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_RTC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_spi.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_spi.h new file mode 100644 index 0000000000..59681ad12c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_spi.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file lib_spi.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief SPI library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_SPI_H +#define __LIB_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Mode; + uint32_t SPH; + uint32_t SPO; + uint32_t ClockDivision; + uint32_t CSNSoft; + uint32_t SWAP; +} SPI_InitType; + +/************** Bits definition for SPIx_CTRL register ******************/ +#define SPI_CTRL_SCKSEL_0 (0x1U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000001 */ +#define SPI_CTRL_SCKSEL_1 (0x2U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL_SCKSEL_2 (0x4U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000004 */ + +/************** Bits definition for SPIx_TXSTS register ******************/ +#define SPI_TXSTS_TXFFLAG_0 (0x1U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000001 */ +#define SPI_TXSTS_TXFFLAG_1 (0x2U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000002 */ +#define SPI_TXSTS_TXFFLAG_2 (0x4U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000004 */ +#define SPI_TXSTS_TXFFLAG_3 (0x8U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x00000008 */ +#define SPI_TXSTS_TXFLEV_0 (0x1U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000010 */ +#define SPI_TXSTS_TXFLEV_1 (0x2U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000020 */ +#define SPI_TXSTS_TXFLEV_2 (0x4U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000040 */ + +/************** Bits definition for SPIx_TXDAT register ******************/ + +/************** Bits definition for SPIx_RXSTS register ******************/ +#define SPI_RXSTS_RXFFLAG_0 (0x1U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000001 */ +#define SPI_RXSTS_RXFFLAG_1 (0x2U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000002 */ +#define SPI_RXSTS_RXFFLAG_2 (0x4U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000004 */ +#define SPI_RXSTS_RXFFLAG_3 (0x8U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x00000008 */ +#define SPI_RXSTS_RXFLEV_0 (0x1U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000010 */ +#define SPI_RXSTS_RXFLEV_1 (0x2U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000020 */ +#define SPI_RXSTS_RXFLEV_2 (0x4U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000040 */ +//Mode +#define SPI_MODE_MASTER 0 +#define SPI_MODE_SLAVE SPI_CTRL_MOD +//SPH +#define SPI_SPH_0 0 +#define SPI_SPH_1 SPI_CTRL_SCKPHA +//SPO +#define SPI_SPO_0 0 +#define SPI_SPO_1 SPI_CTRL_SCKPOL +//ClockDivision +#define SPI_CLKDIV_2 (0) +#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0) +#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1) +#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1) +#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2) +#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2) +#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2) +//CSNSoft +#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO +#define SPI_CSNSOFT_DISABLE 0 +//SWAP +#define SPI_SWAP_ENABLE SPI_CTRL_SWAP +#define SPI_SWAP_DISABLE 0 + +//INT +#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN) +#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN) + +//status +#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF) +#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY) +#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR) +#define SPI_STS_DMATXDONE (0x80000000|SPI_TXSTS_DMATXDONE) +#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF) +#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL) +#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV) +#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY) +#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF) +#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE) +#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF) +#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE) + +//TXFLEV +#define SPI_TXFLEV_0 (0) +#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0) +#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1) +#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1) +#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2) + +//RXFLEV +#define SPI_RXFLEV_0 (0) +#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0) +#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2) +#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0) +#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0) + + +/* Private macros ------------------------------------------------------------*/ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE)) + +#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1)) + +#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1)) + +#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\ + ((__CLKDIV__) == SPI_CLKDIV_4) ||\ + ((__CLKDIV__) == SPI_CLKDIV_8) ||\ + ((__CLKDIV__) == SPI_CLKDIV_16) ||\ + ((__CLKDIV__) == SPI_CLKDIV_32) ||\ + ((__CLKDIV__) == SPI_CLKDIV_64) ||\ + ((__CLKDIV__) == SPI_CLKDIV_128)) + +#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE)) + +#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE)) + +#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\ + (((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U)) + +#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\ + ((__STSR__) == SPI_STS_TXEMPTY) ||\ + ((__STSR__) == SPI_STS_TXFUR) ||\ + ((__STSR__) == SPI_STS_DMATXDONE) ||\ + ((__STSR__) == SPI_STS_RXFULL) ||\ + ((__STSR__) == SPI_STS_RXFOV) ||\ + ((__STSR__) == SPI_STS_BSY) ||\ + ((__STSR__) == SPI_STS_RFF) ||\ + ((__STSR__) == SPI_STS_RNE) ||\ + ((__STSR__) == SPI_STS_TNF) ||\ + ((__STSR__) == SPI_STS_TFE) ||\ + ((__STSR__) == SPI_STS_RXIF)) + +#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF | SPI_STS_DMATXDONE)) != 0U) &&\ + (((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF | SPI_STS_DMATXDONE)) == 0U)) + +#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\ + ((__TXFLEV__) == SPI_TXFLEV_1) ||\ + ((__TXFLEV__) == SPI_TXFLEV_2) ||\ + ((__TXFLEV__) == SPI_TXFLEV_3) ||\ + ((__TXFLEV__) == SPI_TXFLEV_4) ||\ + ((__TXFLEV__) == SPI_TXFLEV_5) ||\ + ((__TXFLEV__) == SPI_TXFLEV_6) ||\ + ((__TXFLEV__) == SPI_TXFLEV_7)) + +#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\ + ((__RXFLEV__) == SPI_RXFLEV_1) ||\ + ((__RXFLEV__) == SPI_RXFLEV_2) ||\ + ((__RXFLEV__) == SPI_RXFLEV_3) ||\ + ((__RXFLEV__) == SPI_RXFLEV_4) ||\ + ((__RXFLEV__) == SPI_RXFLEV_5) ||\ + ((__RXFLEV__) == SPI_RXFLEV_6) ||\ + ((__RXFLEV__) == SPI_RXFLEV_7)) + +/****************************** SPI Instances *********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/* Exported Functions ------------------------------------------------------- */ +/* SPI Exported Functions Group1: + (De)Initialization -------------------------*/ +void SPI_DeviceInit(SPI_Type *SPIx); +void SPI_Init(SPI_Type *SPIx, SPI_InitType *InitStruct); +void SPI_StructInit(SPI_InitType *InitStruct); +/* SPI Exported Functions Group2: + Interrupt (flag) ---------------------------*/ +void SPI_INTConfig(SPI_Type *SPIx, uint32_t INTMask, uint32_t NewState); +uint8_t SPI_GetStatus(SPI_Type *SPIx, uint32_t Status); +void SPI_ClearStatus(SPI_Type *SPIx, uint32_t Status); +/* SPI Exported Functions Group3: + Transfer datas -----------------------------*/ +void SPI_SendData(SPI_Type *SPIx, uint8_t ch); +uint8_t SPI_ReceiveData(SPI_Type *SPIx); +/* SPI Exported Functions Group4: + MISC Configuration -------------------------*/ +void SPI_Cmd(SPI_Type *SPIx, uint32_t NewState); +void SPI_TransmitFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel); +void SPI_ReceiveFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel); +uint8_t SPI_GetTransmitFIFOLevel(SPI_Type *SPIx); +uint8_t SPI_GetReceiveFIFOLevel(SPI_Type *SPIx); +void SPI_SmartModeCmd(SPI_Type *SPIx, uint32_t NewState); +void SPI_OverWriteModeCmd(SPI_Type *SPIx, uint32_t NewState); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_SPI_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_tmr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_tmr.h new file mode 100644 index 0000000000..9a5a2969e9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_tmr.h @@ -0,0 +1,68 @@ +/** + ****************************************************************************** + * @file lib_tmr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Timer library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_TMR_H +#define __LIB_TMR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Period; + uint32_t ClockSource; + uint32_t EXTGT; +} TMR_InitType; +//ClockSource +#define TMR_CLKSRC_INTERNAL 0 +#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK +//ClockGate +#define TMR_EXTGT_DISABLE 0 +#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN + +/* Private macros ------------------------------------------------------------*/ +#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL)) + +#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE)) + +/****************************** TMR Instances *********************************/ +#define IS_TMR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TMR0) || \ + ((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3)) + +/* Exported Functions ------------------------------------------------------- */ +/* Timer Exported Functions Group1: + (De)Initialization ----------------------*/ +void TMR_DeInit(TMR_Type *TMRx); +void TMR_Init(TMR_Type *TMRx, TMR_InitType *InitStruct); +void TMR_StructInit(TMR_InitType *InitStruct); +/* Timer Exported Functions Group2: + Interrupt (flag) -------------------------*/ +void TMR_INTConfig(TMR_Type *TMRx, uint32_t NewState); +uint8_t TMR_GetINTStatus(TMR_Type *TMRx); +void TMR_ClearINTStatus(TMR_Type *TMRx); +/* Timer Exported Functions Group3: + MISC Configuration -----------------------*/ +void TMR_Cmd(TMR_Type *TMRx, uint32_t NewState); +uint32_t TMR_GetCurrentValue(TMR_Type *TMRx); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_TMR_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_u32k.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_u32k.h new file mode 100644 index 0000000000..546d390a86 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_u32k.h @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file lib_u32k.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief UART 32K library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_U32K_H +#define __LIB_U32K_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Debsel; + uint32_t Parity; + uint32_t FirstBit; + uint32_t AutoCal; + uint32_t Baudrate; + uint32_t LineSel; +} U32K_InitType; + +/************** Bits definition for U32Kx_CTRL0 register ******************/ +#define U32K_CTRL0_PMODE_EVEN (0x0U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000000 */ +#define U32K_CTRL0_PMODE_ODD (0x1U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000010 */ +#define U32K_CTRL0_PMODE_0 (0x2U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000020 */ +#define U32K_CTRL0_PMODE_1 (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */ +#define U32K_CTRL0_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000000 */ +#define U32K_CTRL0_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000040 */ +#define U32K_CTRL0_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000080 */ +#define U32K_CTRL0_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */ + +/************** Bits definition for U32Kx_CTRL1 register ******************/ +#define U32K_CTRL1_RXSEL_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000000 */ +#define U32K_CTRL1_RXSEL_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000010 */ +#define U32K_CTRL1_RXSEL_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000020 */ +#define U32K_CTRL1_RXSEL_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */ +//Debsel +#define U32K_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos) +#define U32K_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos) +#define U32K_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos) +#define U32K_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos) +//Parity +#define U32K_PARITY_EVEN (0x1U << U32K_CTRL0_PMODE_Pos) +#define U32K_PARITY_ODD (0x3U << U32K_CTRL0_PMODE_Pos) +#define U32K_PARITY_0 (0x5U << U32K_CTRL0_PMODE_Pos) +#define U32K_PARITY_1 (0x7U << U32K_CTRL0_PMODE_Pos) +#define U32K_PARITY_NONE (0x0U << U32K_CTRL0_PMODE_Pos) +//FirstBit +#define U32K_FIRSTBIT_LSB 0 +#define U32K_FIRSTBIT_MSB (0x1U << U32K_CTRL0_MSB_Pos) +//AutoCal +#define U32K_AUTOCAL_ON 0 +#define U32K_AUTOCAL_OFF (0x1U << U32K_CTRL0_ACOFF_Pos) +//Line +#define U32K_LINE_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos) +#define U32K_LINE_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos) +#define U32K_LINE_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos) +#define U32K_LINE_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos) + +//INT +#define U32K_INT_RXOV (0x1U << U32K_CTRL1_RXOVIE_Pos) +#define U32K_INT_RXPE (0x1U << U32K_CTRL1_RXPEIE_Pos) +#define U32K_INT_RX (0x1U << U32K_CTRL1_RXIE_Pos) +#define U32K_INT_Msk (U32K_INT_RXOV \ + |U32K_INT_RXPE \ + |U32K_INT_RX) + +//INT Status +#define U32K_INTSTS_RXOV (0x1U << U32K_STS_RXOV_Pos) +#define U32K_INTSTS_RXPE (0x1U << U32K_STS_RXPE_Pos) +#define U32K_INTSTS_RX (0x1U << U32K_STS_RXIF_Pos) +#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \ + |U32K_INTSTS_RXPE \ + |U32K_INTSTS_RX) + +//WKUMode +#define U32K_WKUMOD_RX 0 // Wake-up when receive data +#define U32K_WKUMOD_PC (0x1U << U32K_CTRL0_WKUMODE_Pos) // Wake-up when receive data and parity/stop bit correct + + +/****************************** U32K Instances ********************************/ +#define IS_U32K_ALL_INSTANCE(INSTANCE) (((INSTANCE) == U32K0) || \ + ((INSTANCE) == U32K1)) + +/* Private macros ------------------------------------------------------------*/ +#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\ + ((__DEBSEL__) == U32K_DEBSEL_1) ||\ + ((__DEBSEL__) == U32K_DEBSEL_2) ||\ + ((__DEBSEL__) == U32K_DEBSEL_3)) + +#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\ + ((__PARITY__) == U32K_PARITY_ODD) ||\ + ((__PARITY__) == U32K_PARITY_0) ||\ + ((__PARITY__) == U32K_PARITY_1) ||\ + ((__PARITY__) == U32K_PARITY_NONE)) + +#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B)) + +#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB)) + +#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF)) + +#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\ + ((__LINE__) == U32K_LINE_RX1) ||\ + ((__LINE__) == U32K_LINE_RX2) ||\ + ((__LINE__) == U32K_LINE_RX3)) + +#define IS_U32K_BAUDRATE(__BAUDRATE__) ((300UL <= (__BAUDRATE__)) &&\ + ((__BAUDRATE__) <= 14400UL)) + +#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\ + (((__INT__) & ~U32K_INT_Msk) == 0U)) + +#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\ + ((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\ + ((__INTFLAGR__) == U32K_INTSTS_RX)) + +#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U)) + +#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC)) + +/* Exported Functions ------------------------------------------------------- */ +/* U32K Exported Functions Group1: + (De)Initialization -----------------------*/ +void U32K_DeInit(U32K_Type *U32Kx); +void U32K_Init(U32K_Type *U32Kx, U32K_InitType *InitStruct); +void U32K_StructInit(U32K_InitType *InitStruct); +/* U32K Exported Functions Group2: + Interrupt (flag) configure ---------------*/ +void U32K_INTConfig(U32K_Type *U32Kx, uint32_t INTMask, uint8_t NewState); +uint8_t U32K_GetINTStatus(U32K_Type *U32Kx, uint32_t INTMask); +void U32K_ClearINTStatus(U32K_Type *U32Kx, uint32_t INTMask); +/* U32K Exported Functions Group3: + Receive datas -----------------------------*/ +uint8_t U32K_ReceiveData(U32K_Type *U32Kx); +/* U32K Exported Functions Group4: + MISC Configuration -------- ---------------*/ +void U32K_BaudrateConfig(U32K_Type *U32Kx, uint32_t BaudRate); +void U32K_Cmd(U32K_Type *U32Kx, uint32_t NewState); +void U32K_LineConfig(U32K_Type *U32Kx, uint32_t Line); +void U32K_WKUModeConfig(U32K_Type *U32Kx, uint32_t WKUMode); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_U32K_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_uart.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_uart.h new file mode 100644 index 0000000000..b91f852889 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_uart.h @@ -0,0 +1,172 @@ +/** + ****************************************************************************** + * @file lib_uart.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief UART library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_UART_H +#define __LIB_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//UART Init struct +typedef struct +{ + uint32_t Mode; + uint32_t Parity; + uint32_t FirstBit; + uint32_t Baudrate; +} UART_InitType; + +//Mode +#define UART_MODE_RX (0x1U << UART_CTRL_RXEN_Pos) +#define UART_MODE_TX (0x1U << UART_CTRL_TXEN_Pos) +#define UART_MODE_OFF 0 +#define UART_MODE_Msk (UART_MODE_RX | UART_MODE_TX) +//Parity +#define UART_PARITY_EVEN (0x1U << UART_CTRL2_PMODE_Pos) +#define UART_PARITY_ODD (0x3U << UART_CTRL2_PMODE_Pos) +#define UART_PARITY_0 (0x5U << UART_CTRL2_PMODE_Pos) +#define UART_PARITY_1 (0x7U << UART_CTRL2_PMODE_Pos) +#define UART_PARITY_NONE (0x0U << UART_CTRL2_PMODE_Pos) + +//FirstBit +#define UART_FIRSTBIT_LSB 0 +#define UART_FIRSTBIT_MSB (0x1U << UART_CTRL2_MSB_Pos) + +//UART Configration Information struct +typedef struct +{ + uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable + uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable + uint32_t Baudrate; //The value of current budrate + uint8_t Parity; //0:1+8+1 mode; 1: Even parity; 3:Odd parity; 5: parity bit=0; 7: parity bit=1; + uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first +} UART_ConfigINFOType; + +//status +#define UART_FLAG_DMATXDONE (0x1U << UART_STATE_DMATXDONE_Pos) +#define UART_FLAG_RXPARITY (0x1U << UART_STATE_RXPSTS_Pos) +#define UART_FLAG_TXDONE (0x1U << UART_STATE_TXDONE_Pos) +#define UART_FLAG_RXPE (0x1U << UART_STATE_RXPE_Pos) +#define UART_FLAG_RXOV (0x1U << UART_STATE_RXOV_Pos) +#define UART_FLAG_TXOV (0x1U << UART_STATE_TXOV_Pos) +#define UART_FLAG_RXFULL (0x1U << UART_STATE_RXFULL_Pos) +#define UART_FLAG_RCMsk (UART_FLAG_DMATXDONE \ + |UART_FLAG_TXDONE \ + |UART_FLAG_RXPE \ + |UART_FLAG_RXOV \ + |UART_FLAG_RXFULL \ + |UART_FLAG_TXOV) + +//interrupt +#define UART_INT_TXDONE (0x1U << UART_CTRL_TXDONEIE_Pos) +#define UART_INT_RXPE (0x1U << UART_CTRL_RXPEIE_Pos) +#define UART_INT_RXOV (0x1U << UART_CTRL_RXOVIE_Pos) +#define UART_INT_TXOV (0x1U << UART_CTRL_TXOVIE_Pos) +#define UART_INT_RX (0x1U << UART_CTRL_RXIE_Pos) +#define UART_INT_Msk (UART_INT_TXDONE \ + |UART_INT_RXPE \ + |UART_INT_RXOV \ + |UART_INT_TXOV \ + |UART_INT_RX) + +//INTStatus +#define UART_INTSTS_TXDONE (0x1U << UART_INTSTS_TXDONEIF_Pos) +#define UART_INTSTS_RXPE (0x1U << UART_INTSTS_RXPEIF_Pos) +#define UART_INTSTS_RXOV (0x1U << UART_INTSTS_RXOVIF_Pos) +#define UART_INTSTS_TXOV (0x1U << UART_INTSTS_TXOVIF_Pos) +#define UART_INTSTS_RX (0x1U << UART_INTSTS_RXIF_Pos) +#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \ + |UART_INTSTS_RXPE \ + |UART_INTSTS_RXOV \ + |UART_INTSTS_TXOV \ + |UART_INTSTS_RX) + +/* Private macros ------------------------------------------------------------*/ +#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U))) + +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\ + ((__PARITY__) == UART_PARITY_ODD) ||\ + ((__PARITY__) == UART_PARITY_0) ||\ + ((__PARITY__) == UART_PARITY_1) ||\ + ((__PARITY__) == UART_PARITY_NONE)) + +#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\ + ((__FIRSTBIT__) == UART_FIRSTBIT_MSB)) + +#define IS_UART_BAUDRATE(__BAUDRATE__) ((300UL <= (__BAUDRATE__)) &&\ + ((__BAUDRATE__) <= 819200UL)) + +#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_DMATXDONE) ||\ + ((__FLAGR__) == UART_FLAG_RXPARITY) ||\ + ((__FLAGR__) == UART_FLAG_TXDONE) ||\ + ((__FLAGR__) == UART_FLAG_RXPE) ||\ + ((__FLAGR__) == UART_FLAG_RXOV) ||\ + ((__FLAGR__) == UART_FLAG_TXOV) ||\ + ((__FLAGR__) == UART_FLAG_RXFULL)) + +#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\ + (((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U)) + +#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\ + (((__INT__) & ~UART_INT_Msk) == 0U)) + +#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\ + ((__INTFLAGR__) == UART_INTSTS_RXPE) ||\ + ((__INTFLAGR__) == UART_INTSTS_RXOV) ||\ + ((__INTFLAGR__) == UART_INTSTS_TXOV) ||\ + ((__INTFLAGR__) == UART_INTSTS_RX)) + +#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U)) + +/****************************** UART Instances ********************************/ +#define IS_UART_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UART0) || \ + ((INSTANCE) == UART1) || \ + ((INSTANCE) == UART2) || \ + ((INSTANCE) == UART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/* Exported Functions ------------------------------------------------------- */ +/* UART Exported Functions Group1: + Initialization and functions --------------*/ +void UART_DeInit(UART_Type *UARTx); +void UART_Init(UART_Type *UARTx, UART_InitType *InitStruct); +void UART_StructInit(UART_InitType *InitStruct); +/* UART Exported Functions Group2: + (Interrupt) Flag --------------------------*/ +uint8_t UART_GetFlag(UART_Type *UARTx, uint32_t FlagMask); +void UART_ClearFlag(UART_Type *UARTx, uint32_t FlagMask); +void UART_INTConfig(UART_Type *UARTx, uint32_t INTMask, uint8_t NewState); +uint8_t UART_GetINTStatus(UART_Type *UARTx, uint32_t INTMask); +void UART_ClearINTStatus(UART_Type *UARTx, uint32_t INTMask); +/* UART Exported Functions Group3: + Transfer datas ----------------------------*/ +void UART_SendData(UART_Type *UARTx, uint8_t ch); +uint8_t UART_ReceiveData(UART_Type *UARTx); +/* UART Exported Functions Group4: + MISC Configuration ------------------------*/ +void UART_BaudrateConfig(UART_Type *UARTx, uint32_t BaudRate); +void UART_Cmd(UART_Type *UARTx, uint32_t Mode, uint32_t NewState); +void UART_GetConfigINFO(UART_Type *UARTx, UART_ConfigINFOType *ConfigInfo); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_UART_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_version.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_version.h new file mode 100644 index 0000000000..542d05e1e2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_version.h @@ -0,0 +1,36 @@ +/** +******************************************************************************* + * @file lib_version.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Version library. +*******************************************************************************/ + +#ifndef __LIB_VERSION_H +#define __LIB_VERSION_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor)) + +/* Exported Functions ------------------------------------------------------- */ + +/** + * @brief Read receive data register. + * @param None + * @retval Version value + */ +uint16_t Target_GetDriveVersion(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_VERSION_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_wdt.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_wdt.h new file mode 100644 index 0000000000..300884dc26 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/inc/lib_wdt.h @@ -0,0 +1,47 @@ +/** + ****************************************************************************** + * @file lib_wdt.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief WDT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_WDT_H +#define __LIB_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + + +#define WDT_2_SECS (0x0U << PMU_WDTEN_WDTSEL_Pos) +#define WDT_4_SECS (0x1U << PMU_WDTEN_WDTSEL_Pos) +#define WDT_8_SECS (0x2U << PMU_WDTEN_WDTSEL_Pos) +#define WDT_16_SECS (0x3U << PMU_WDTEN_WDTSEL_Pos) + +/* Private macros ------------------------------------------------------------*/ +#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\ + ((__PERIOD__) == WDT_4_SECS) ||\ + ((__PERIOD__) == WDT_8_SECS) ||\ + ((__PERIOD__) == WDT_16_SECS)) + +/* Exported Functions ------------------------------------------------------- */ +void WDT_Enable(void); +void WDT_Disable(void); +void WDT_Clear(void); +void WDT_SetPeriod(uint32_t period); +uint16_t WDT_GetCounterValue(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_WDT_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_adc.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_adc.c new file mode 100644 index 0000000000..decb391094 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_adc.c @@ -0,0 +1,988 @@ +/** + ****************************************************************************** + * @file lib_adc.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief ADC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_adc.h" +#include "main.h" + +#define ANA_INTEN_ADCMsk (0x3FC003U) +#define ANA_INTSTS_ADCMsk (0x3FC003U) + +#define ADC_SYNC_WR(); {__NOP(); __NOP(); __NOP(); __NOP();} + +/** + * @brief Initializes ADC peripheral registers to their default reset values. + * @note 1. Disable ADC + 2. Disable resistor division. + 3. Disable ADC auto/manual done interrupt. + 4. The ADC correlation (register) is written to the default value. + * @param None + * @retval status: - 0 Function succeeded. + * - nep 0 Function failed. + */ +uint32_t ADC_DeInit(void) +{ + uint32_t tmp[3]; + uint32_t ANA_ADCCTRL0_RSTValue = (0x300000U); + uint32_t ANA_ADCCTRL1_RSTValue = (0x02U); + uint32_t ANA_ADCCTRL2_RSTValue = (0x8014U); + uint32_t ANA_ADCDATATHD1_0_RSTValue = (0U); + uint32_t ANA_ADCDATATHD3_2_RSTValue = (0U); + uint32_t ANA_ADCDATATHD_CH_RSTValue = (0U); + uint32_t RTC_ADCUCALK_RSTValue = (0x599A599AU); + uint32_t RTC_ADCMACTL_RSTValue = (0x78000000U); + uint32_t RTC_ADCDTCTL_RSTValue = (0x80000000); + uint32_t i, nCount, nValue, nAddress, nChecksum; + uint8_t need_check = 0; + uint32_t retval = 0; + + nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1; + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4)) + { + nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET); + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4)) + { + retval = 0xFFFFFFFFUL; + } + else + { + need_check = 1; + } + } + else + { + need_check = 1; + } + + if (need_check) + { + for(i=0; iADCCTRL0)) + { + ANA_ADCCTRL0_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&ANA->ADCCTRL1)) + { + ANA_ADCCTRL1_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&ANA->ADCCTRL2)) + { + ANA_ADCCTRL2_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&ANA->ADCDATATHD1_0)) + { + ANA_ADCDATATHD1_0_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&ANA->ADCDATATHD3_2)) + { + ANA_ADCDATATHD3_2_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&ANA->ADCDATATHD_CH)) + { + ANA_ADCDATATHD_CH_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&RTC->ADCUCALK)) + { + RTC_ADCUCALK_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&RTC->ADCMACTL)) + { + RTC_ADCMACTL_RSTValue = nValue; + } + else if(nAddress == (uint32_t)(&RTC->ADCDTCTL)) + { + RTC_ADCDTCTL_RSTValue = nValue; + } + else + { /* No operation */ } + } + } + + if((ANA->ADCSTATE&0x07) != 0) + { + ADC_Cmd(DISABLE); + } + + /* 6.5MHz clock. */ + ANA->REG0 &= ~ANA_REG0_ADCFRQSEL; + /* ADC mode */ + ANA->REG1 &= ~ANA_REG1_ADCMODESEL; + /* Power up VINBUF and REFBUF. */ + ANA->REG11 = 0; + /* Power down ADC */ + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + /* Disable interrupt, Clear interrupt flag */ + ANA->INTEN &= ~ANA_INTEN_ADCMsk; + ANA->INTSTS = ANA_INTSTS_ADCMsk; + while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG); + ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue; + while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG); + ANA->ADCCTRL1 = ANA_ADCCTRL1_RSTValue; + ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue|ANA_ADCCTRL2_CONV_ERR_CLR|ANA_ADCCTRL2_CAL_ERR_CLR; + + ANA->ADCDATATHD1_0= ANA_ADCDATATHD1_0_RSTValue; + ANA->ADCDATATHD3_2 = ANA_ADCDATATHD3_2_RSTValue; + ANA->ADCDATATHD_CH = ANA_ADCDATATHD_CH_RSTValue; + tmp[0] = RTC_ADCUCALK_RSTValue; + tmp[1] = RTC_ADCMACTL_RSTValue; + tmp[2] = RTC_ADCDTCTL_RSTValue; + RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3); + + ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue; + + return (retval); +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct: pointer to an ADC_InitType structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitType* ADC_InitStruct) +{ + /*------ Reset ADC init structure parameters values ------*/ + ADC_InitStruct->Mode = ADC_MODE_DC; + ADC_InitStruct->ClockSource = ADC_CLKSRC_RCH; + ADC_InitStruct->ClockFrq = ADC_CLKFRQ_HIGH; + ADC_InitStruct->SkipSample = ADC_SKIP_0; + ADC_InitStruct->AverageSample = ADC_AVERAGE_2; + ADC_InitStruct->TriggerSource = ADC_TRIGSOURCE_OFF; + ADC_InitStruct->Channel = ADC_CHANNEL_GND0; + ADC_InitStruct->ResDivEnable = 0; + ADC_InitStruct->AverageEnable = 0; +} + +/** + * @brief Initializes ADC. + * @param ADC_InitStruct: pointer to an ADC_InitType structure which will be initialized. + Mode: + ADC_MODE_DC (Not include ADC_CHANNEL_TEMP) + ADC_MODE_AC (Only ADC_CHANNEL_CHx be valid) + ADC_MODE_TEMP (Only ADC_CHANNEL_TEMP be valid) + ClockSource: + ADC_CLKSRC_RCH + ADC_CLKSRC_PLLL + ClockFrq: + ADC_CLKFRQ_HIGH + ADC_CLKFRQ_LOW + SkipSample: + ADC_SKIP_0 + ADC_SKIP_4 + ADC_SKIP_8 + ADC_SKIP_12 + AverageSample: + ADC_AVERAGE_2 + ADC_AVERAGE_4 + ADC_AVERAGE_8 + ADC_AVERAGE_16 + ADC_AVERAGE_32 + ADC_AVERAGE_64 + TriggerSource: + ADC_TRIGSOURCE_OFF + ADC_TRIGSOURCE_ITVSITV + ADC_TRIGSOURCE_WKUSEC + ADC_TRIGSOURCE_ALARM + ADC_TRIGSOURCE_TMR0 + ADC_TRIGSOURCE_TMR1 + ADC_TRIGSOURCE_TMR2 + ADC_TRIGSOURCE_TMR3 + Channel: + ResDivEnable: (also can be ADC_CHANNEL_NONE) + AverageEnable: (also can be ADC_CHANNEL_NONE) + ADC_CHANNEL_GND0 + ADC_CHANNEL_BAT1 + ADC_CHANNEL_BATRTC + ADC_CHANNEL_CH3 + ADC_CHANNEL_CH4 + ADC_CHANNEL_CH5 + ADC_CHANNEL_CH6 + ADC_CHANNEL_CH7 + ADC_CHANNEL_CH8 + ADC_CHANNEL_CH9 + ADC_CHANNEL_TEMP + ADC_CHANNEL_CH11 + ADC_CHANNEL_DVCC + ADC_CHANNEL_GND13 + ADC_CHANNEL_GND14 + ADC_CHANNEL_GND15 + ADC_CHANNEL_DC_ALL + ADC_CHANNEL_AC_ALL + * @retval None + */ +void ADC_Init(ADC_InitType *ADC_InitStruct) +{ + uint32_t tmp_anareg0, tmp_anareg1, tmp_anareg3, tmp_anareg11; + uint32_t tmp_adcctrl0, tmp_adcctrl1, tmp_adcctrl2; + uint32_t tmp_rtcadcmactl; + + /* Check parameters */ + assert_parameters(IS_ADC_MODE(ADC_InitStruct->Mode)); + assert_parameters(IS_ADC_CLKSRC(ADC_InitStruct->ClockSource)); + assert_parameters(IS_ADC_CLKFRQ(ADC_InitStruct->ClockFrq)); + assert_parameters(IS_ADC_SKIP(ADC_InitStruct->SkipSample)); + assert_parameters(IS_ADC_AVERAG(ADC_InitStruct->AverageSample)); + assert_parameters(IS_ADC_TRIGSOURCE(ADC_InitStruct->TriggerSource)); + + while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG); + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + + tmp_adcctrl0 = ANA->ADCCTRL0; + tmp_adcctrl1 = ANA->ADCCTRL1; + tmp_adcctrl2 = ANA->ADCCTRL2; + tmp_anareg0 = ANA->REG0; + tmp_anareg1 = ANA->REG1; + tmp_anareg3 = ANA->REG3; + tmp_anareg11 = 0; + tmp_rtcadcmactl = RTC->ADCMACTL; + + /* Configure clock source and trigger source */ + tmp_adcctrl0 &= ~(ANA_ADCCTRL0_AEN | ANA_ADCCTRL0_CLKSRCSEL); + tmp_adcctrl0 |= (ADC_InitStruct->TriggerSource | ADC_InitStruct->ClockSource); + + /* Configure ClockFrq */ + if (ADC_InitStruct->ClockFrq == ADC_CLKFRQ_HIGH) + { + tmp_anareg0 &= ~ANA_REG0_ADCFRQSEL; + tmp_adcctrl2 &= ~ANA_ADCCTRL2_ADCCR; + } + else + { + tmp_anareg0 |= ANA_REG0_ADCFRQSEL; + tmp_adcctrl2 |= ANA_ADCCTRL2_ADCCR; + } + + /* Configure skip samples and average samples */ + tmp_rtcadcmactl &= ~(RTC_ADCMACTL_SKIP_SAMPLE | RTC_ADCMACTL_AVERAGE_SAMPLE); + tmp_rtcadcmactl |= (ADC_InitStruct->SkipSample | ADC_InitStruct->AverageSample); + + /* Mode: DC */ + if (ADC_InitStruct->Mode == ADC_MODE_DC) + { + /* Check parameters */ + assert_parameters(IS_ADC_CHANNEL_DC(ADC_InitStruct->Channel)); + assert_parameters(IS_ADC_CHANNEL_EN_DC(ADC_InitStruct->AverageEnable)); + assert_parameters(IS_ADC_CHANNEL_EN_DC(ADC_InitStruct->ResDivEnable)); + + /* Enable or disable Channels */ + tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx; + tmp_adcctrl2 |= (ADC_InitStruct->Channel << ADC_CHANNEL_SHIFT); + /* Enable or disable average */ + tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx; + tmp_rtcadcmactl |= (ADC_InitStruct->AverageEnable << ADC_AVERAGECH_SHIFT); + /* Enable or disable RESDIV */ + tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx; + tmp_adcctrl1 |= (ADC_InitStruct->ResDivEnable << ADC_RESDIVCH_SHIFT); + /* Others */ + tmp_anareg1 &= ~ANA_REG1_ADCMODESEL; + } + /* Mode: AC */ + else if (ADC_InitStruct->Mode == ADC_MODE_AC) + { + /* Check parameters */ + assert_parameters(IS_ADC_CHANNEL_AC(ADC_InitStruct->Channel)); + assert_parameters(IS_ADC_CHANNEL_EN_AC(ADC_InitStruct->AverageEnable)); + + /* Enable or disable Channels */ + tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx; + tmp_adcctrl2 |= (ADC_InitStruct->Channel << ADC_CHANNEL_SHIFT); + /* Enable or disable average */ + tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx; + tmp_rtcadcmactl |= (ADC_InitStruct->AverageEnable << ADC_AVERAGECH_SHIFT); + /* Enable or disable RESDIV */ + tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx; + tmp_adcctrl1 |= (ADC_InitStruct->Channel << ADC_RESDIVCH_SHIFT); + /* Others */ + tmp_anareg1 |= ANA_REG1_ADCMODESEL; + } + /* Mode: TEMP */ + else + { + /* Check parameters */ + assert_parameters(IS_ADC_CHANNEL_TEMP(ADC_InitStruct->Channel)); + + /* Enable ADC_CHANNEL_TEMP */ + tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx; + tmp_adcctrl2 |= (ADC_CHANNEL_TEMP << ADC_CHANNEL_SHIFT); + /* Enable average */ + tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx; + tmp_rtcadcmactl |= (ADC_CHANNEL_TEMP << ADC_AVERAGECH_SHIFT); + /* Disable RESDIV */ + tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx; + /* Others */ + tmp_anareg1 &= ~ANA_REG1_ADCMODESEL; + if(ADC_InitStruct->ClockFrq == ADC_CLKFRQ_LOW) + { + /* It can improve the accuracy of temperature measurement */ + tmp_anareg11 |= (ANA_REG11_VINBUFPD | ANA_REG11_REFBUFPD); + } + } + + ANA->ADCCTRL0 = tmp_adcctrl0&(~ANA_ADCCTRL0_MTRIG); + ANA->ADCCTRL1 = tmp_adcctrl1; + ANA->ADCCTRL2 = tmp_adcctrl2; + ANA->REG0 = tmp_anareg0; + ANA->REG1 = tmp_anareg1; + ANA->REG3 = tmp_anareg3; + ANA->REG11 = tmp_anareg11; + RTC_WriteRegisters((uint32_t)&RTC->ADCMACTL, &tmp_rtcadcmactl, 1); +} + +/** + * @brief Fills each ADCTHD_InitType member with its default value. + * @param ADC_THDStruct: pointer to an ADC_THDStruct structure which will be initialized. + * @retval None + */ +void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct) +{ + ADC_THDStruct->THDChannel = ADC_THDCHANNEL0; + ADC_THDStruct->UpperTHD = 0x0000; + ADC_THDStruct->LowerTHD = 0x0000; + ADC_THDStruct->TriggerSel = ADC_THDSEL_HIGH; + ADC_THDStruct->THDSource = ADC_CHANNEL_GND0; +} + +/** + * @brief Initializes ADC threshold. + * @param ADC_THDStruct: + * THDChannel: + * ADC_THDCHANNEL0 + * ADC_THDCHANNEL1 + * ADC_THDCHANNEL2 + * ADC_THDCHANNEL3 + * UpperTHD: + * 0~0xFF + * LowerTHD: + * 0~0xFF + * TriggerSel: + * ADC_THDSEL_HIGH + * ADC_THDSEL_RISING + * ADC_THDSEL_FALLING + * ADC_THDSEL_BOTH + * THDSource: + * ADC_CHANNEL_GND0 + * ADC_CHANNEL_BAT1 + * ADC_CHANNEL_BATRTC + * ADC_CHANNEL_CH3 + * ADC_CHANNEL_CH4 + * ADC_CHANNEL_CH5 + * ADC_CHANNEL_CH6 + * ADC_CHANNEL_CH7 + * ADC_CHANNEL_CH8 + * ADC_CHANNEL_CH9 + * ADC_CHANNEL_TEMP + * ADC_CHANNEL_CH11 + * ADC_CHANNEL_DVCC + * ADC_CHANNEL_GND13 + * ADC_CHANNEL_GND14 + * ADC_CHANNEL_GND15 + * @retval None + */ +void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct) +{ + uint32_t tmp = 0; + uint32_t position = 0x00U; + uint32_t currentch = 0x00U; + + /* Check parameters */ + assert_parameters(IS_ADC_THDCHANNEL(ADC_THDStruct->THDChannel)); + assert_parameters(IS_ADC_THDSEL(ADC_THDStruct->TriggerSel)); + assert_parameters(IS_ADC_CHANNEL_GETDATA(ADC_THDStruct->THDSource)); + + while ((ADC_THDStruct->THDSource >> position) != 0U) + { + /* Get current ch position */ + currentch = ADC_THDStruct->THDSource & (0x01U << position); + + if (currentch) + { + break; + } + position++; + } + + if ((ADC_THDStruct->THDChannel == ADC_THDCHANNEL0) || (ADC_THDStruct->THDChannel == ADC_THDCHANNEL1)) + { + ANA->ADCDATATHD1_0 &= ~((ANA_ADCDATATHD1_0_LOWER_THD0|ANA_ADCDATATHD1_0_UPPER_THD0) << (16*ADC_THDStruct->THDChannel)); + ANA->ADCDATATHD1_0 |= (((ADC_THDStruct->UpperTHD<<8)|ADC_THDStruct->LowerTHD) << (16*ADC_THDStruct->THDChannel)); + } + else + { + ANA->ADCDATATHD3_2 &= ~((ANA_ADCDATATHD3_2_LOWER_THD2|ANA_ADCDATATHD3_2_UPPER_THD2) << (16*(ADC_THDStruct->THDChannel - 2))); + ANA->ADCDATATHD3_2 |= (((ADC_THDStruct->UpperTHD<<8)|ADC_THDStruct->LowerTHD) << (16*(ADC_THDStruct->THDChannel - 2))); + } + + tmp = ANA->ADCDATATHD_CH; + tmp &= ~(ANA_ADCDATATHD_CH_THD0_SEL << (ADC_THDStruct->THDChannel*2)); + tmp |= (ADC_THDStruct->TriggerSel << (ADC_THDStruct->THDChannel*2 + ANA_ADCDATATHD_CH_THD0_SEL_Pos)); + + tmp &= ~(ANA_ADCDATATHD_CH_THD0_CH << (ADC_THDStruct->THDChannel*4)); + tmp |= (position << (ADC_THDStruct->THDChannel*4+ANA_ADCDATATHD_CH_THD0_CH_Pos)); + + ANA->ADCDATATHD_CH = tmp; +} + +/** + * @brief Starts ADC calibration (ADC calibration is implemented when DPORST or ADC RESET happened). + * @param None + * @retval None + */ +void ADC_Calibration(void) +{ + //Set 6.5M ADC clock + ANA->REG0 &= ~ANA_REG0_ADCFRQSEL; + ADC_SYNC_WR(); + + //Disable ADC + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + ADC_SYNC_WR(); + ANA->ADCCTRL2 |= ANA_ADCCTRL2_CAL_ERR_CLR; + ADC_SYNC_WR(); + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_CAL_ERR_CLR; + ADC_SYNC_WR(); + + while(1) + { + //ADC STOP + ANA->ADCCTRL0 |= ANA_ADCCTRL0_STOP; + ADC_SYNC_WR(); + ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP; + ADC_SYNC_WR(); + + //Reset ADC + ANA->ADCCTRL2 |= ANA_ADCCTRL2_RESET; + ADC_SYNC_WR(); + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_RESET; + ADC_SYNC_WR(); + + //Enable ADC TRG_CAL + ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN_TRG_CAL; + ADC_SYNC_WR(); + ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN; + ADC_SYNC_WR(); + + /* while loop until ADC calibration is done */ + ADC_SYNC_WR(); + while (!(ANA->ADCCTRL2 & ANA_ADCCTRL2_ADC_CAL_DONE)); + + //Disable ADC TRG_CAL + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN_TRG_CAL; + ADC_SYNC_WR(); + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + ADC_SYNC_WR(); + + if(ANA->ADCCTRL2 & ANA_ADCCTRL2_CAL_ERR) + { + ANA->ADCCTRL2 |= ANA_ADCCTRL2_CAL_ERR_CLR; + ADC_SYNC_WR(); + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_CAL_ERR_CLR; + ADC_SYNC_WR(); + } + else + { + break; + } + } +} + +/** + * @brief Calculates ADC value via ADC original data. + * @param [in]Mode: + ADC_3V_ADCCHx_NODIV + ADC_3V_ADCCHx_RESDIV + ADC_3V_BAT1_RESDIV + ADC_3V_BATRTC_RESDIV + ADC_5V_ADCCHx_NODIV + ADC_5V_ADCCHx_RESDIV + ADC_5V_BAT1_RESDIV + ADC_5V_BATRTC_RESDIV + ADC_TEMP + * @param [in]adc_data: The ADC original data + * @param [out]value: The pointer of value calculated by this function + * @retval 1 NVR checksum error. + 0 Function successed. + */ +uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value) +{ + NVR_ADCVOLPARA parameter; + NVR_TempParams TempParams; + + /* Check parameters */ + assert_parameters(IS_ADCVOL_MODE(Mode)); + + if (Mode == ADC_TEMP) + { + if (NVR_GetTempParameters(&TempParams)) + { + return 1; + } + else + { + /* Calculate temperature */ + *value = ((TempParams.RTCTempP0 * ((adc_data*adc_data)>>16)) + TempParams.RTCTempP1*adc_data + TempParams.RTCTempP2) >> 8; + } + } + else + { + if (NVR_GetVoltageParameters(Mode, ¶meter)) + { + return 1; + } + else + { + *value = (int16_t)((parameter.aParameter*(float)adc_data + parameter.bParameter) + parameter.OffsetParameter); + } + } + + return 0; +} + +/** + * @brief Enables or disables ADC. + * @note None + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_Cmd(uint32_t NewState) +{ + __IO uint32_t dly = 400UL; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG); + if (NewState == DISABLE) + { + if(ANA->ADCSTATE & ANA_ADCSTATE_ADCSTATE) + { + ANA->ADCCTRL0 |= ANA_ADCCTRL0_STOP; + if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK) + { + __NOP(); + __NOP(); + } + else + { + while (dly--) + __NOP(); + } + ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP; + } + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + } + else + { + ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP; + ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN; + + if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK) + { + __NOP(); + __NOP(); + } + else + { + while (dly--) + __NOP(); + } + /* Start Manual ADC conversion */ + ADC_StartManual(); + /* Waiting Manual ADC conversion done */ + ADC_WaitForManual(DELAY_MS(100)); + } +} + +/** + * @brief Enables or disables ADC lower threshold detect function. + * @note None + * @param THDChannel: + ADC_THDCHANNEL0~ADC_THDCHANNEL3 + NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ADC_THDCHANNEL(THDChannel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + ANA->ADCCTRL1 &= ~(ANA_ADCCTRL1_LOWER_THD0_EN << (THDChannel*2)); + } + else + { + ANA->ADCCTRL1 |= (ANA_ADCCTRL1_LOWER_THD0_EN << (THDChannel*2)); + } +} + +/** + * @brief Enables or disables ADC upper threshold detect function. + * @note None + * @param THDChannel: + ADC_THDCHANNEL0~ADC_THDCHANNEL3 + NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ADC_THDCHANNEL(THDChannel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + ANA->ADCCTRL1 &= ~(ANA_ADCCTRL1_UPPER_THD0_EN << (THDChannel*2)); + } + else + { + ANA->ADCCTRL1 |= (ANA_ADCCTRL1_UPPER_THD0_EN << (THDChannel*2)); + } +} + +/** + * @brief Starts ADC manual-trigger. + * @param None + * @retval None + */ +void ADC_StartManual(void) +{ + while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG); + ANA->ADCCTRL0 |= ANA_ADCCTRL0_MTRIG; +} + +/** + * @brief Waits until the last Manual ADC conversion done. + * @param Timeout + * @retval 0:adc finish + 1:adc timeout + + */ +uint8_t ADC_WaitForManual(uint32_t Timeout) +{ + uint32_t TickCurrent; + + SysTick->LOAD = Timeout; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \ + |SysTick_CTRL_ENABLE_Msk; + + while(1) + { + /* Check adc done */ + if(0 == (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG)) + { + SysTick->CTRL = 0; + return 0; + } + /* Check timeout */ + TickCurrent = SysTick->CTRL; + if ((TickCurrent & SysTick_CTRL_COUNTFLAG_Msk)) + { + break; + } + } + + SysTick->CTRL = 0; + return 1; + +} + +/** + * @brief ADC soft reset + * @param ADC init values + * @retval 0:adc success + 1:adc fail + + */ +uint8_t ADC_SoftReset(ADC_InitType* ADC_InitStruct) +{ + /* ADC DeInit */ + ADC_DeInit(); + + /* ADC Calibration */ + ADC_Calibration(); + + /* ADC Init */ + ADC_Init(ADC_InitStruct); + + /* ADC Enable */ + ADC_Cmd(ENABLE); + + return 0; +} + +/** + * @brief Waits until the last Auto ADC conversion done. + * @param None + * @retval 0:adc finish + 1:adc timeout + + */ +uint8_t ADC_WaitForAuto(uint32_t Timeout) +{ + uint32_t TickCurrent; + + SysTick->LOAD = Timeout; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \ + |SysTick_CTRL_ENABLE_Msk; + + while(1) + { + /* Check adc done */ + if(ADC_GetINTStatus(ADC_INTSTS_AUTODONE)) + { + ADC_ClearINTStatus(ADC_INTSTS_AUTODONE); + SysTick->CTRL = 0; + return 0; + } + /* Check timeout */ + TickCurrent = SysTick->CTRL; + if ((TickCurrent & SysTick_CTRL_COUNTFLAG_Msk)) + { + break; + } + } + + SysTick->CTRL = 0; + return 1; + +} +/** + * @brief Gets ADC vonversion value. + * @param Channel: + * ADC_CHANNEL_GND0 + * ADC_CHANNEL_BAT1 + * ADC_CHANNEL_BATRTC + * ADC_CHANNEL_CH3 + * ADC_CHANNEL_CH4 + * ADC_CHANNEL_CH5 + * ADC_CHANNEL_CH6 + * ADC_CHANNEL_CH7 + * ADC_CHANNEL_CH8 + * ADC_CHANNEL_CH9 + * ADC_CHANNEL_TEMP + * ADC_CHANNEL_CH11 + * ADC_CHANNEL_DVCC + * ADC_CHANNEL_GND13 + * ADC_CHANNEL_GND14 + * ADC_CHANNEL_GND15 + * @retval ADC conversion value. + */ +int16_t ADC_GetADCConversionValue(uint32_t Channel) +{ + uint32_t position = 0x0000UL; + uint32_t chcurrent = 0x0000UL; + + /* Check parameters */ + assert_parameters(IS_ADC_CHANNEL_GETDATA(Channel)); + + while ((Channel >> position) != 0UL) + { + chcurrent = Channel & (0x01U << position); + if (chcurrent) + break; + position++; + } + return (ANA->ADCDATA[position]); +} + +/** + * @brief Enables or disables ADC interrupt. + * @param INTMask: can use the '|' operator + ADC_INT_UPPER_TH3 + ADC_INT_LOWER_TH3 + ADC_INT_UPPER_TH2 + ADC_INT_LOWER_TH2 + ADC_INT_UPPER_TH1 + ADC_INT_LOWER_TH1 + ADC_INT_UPPER_TH0 + ADC_INT_LOWER_TH0 + ADC_INT_AUTODONE + ADC_INT_MANUALDONE + NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_ADC_INT(INTMask)); + + if (NewState == ENABLE) + ANA->INTEN |= INTMask; + else + ANA->INTEN &= ~INTMask; +} + +/** + * @brief Clears ADC interrupt status. + * @param INTMask: can use the '|' operator + ADC_INTSTS_UPPER_TH3 + ADC_INTSTS_LOWER_TH3 + ADC_INTSTS_UPPER_TH2 + ADC_INTSTS_LOWER_TH2 + ADC_INTSTS_UPPER_TH1 + ADC_INTSTS_LOWER_TH1 + ADC_INTSTS_UPPER_TH0 + ADC_INTSTS_LOWER_TH0 + ADC_INTSTS_AUTODONE + ADC_INTSTS_MANUALDONE + * @retval None + */ +void ADC_ClearINTStatus(uint32_t INTMask) +{ + /* Parameter check */ + assert_parameters(IS_ADC_INTFLAGC(INTMask)); + + ANA->INTSTS = INTMask; +} + +/** + * @brief Gets ADC interrupt status. + * @param INTMask: + ADC_INTSTS_UPPER_TH3 + ADC_INTSTS_LOWER_TH3 + ADC_INTSTS_UPPER_TH2 + ADC_INTSTS_LOWER_TH2 + ADC_INTSTS_UPPER_TH1 + ADC_INTSTS_LOWER_TH1 + ADC_INTSTS_UPPER_TH0 + ADC_INTSTS_LOWER_TH0 + ADC_INTSTS_AUTODONE + ADC_INTSTS_MANUALDONE + * @retval 1: status set + 0: status reset. + */ +uint8_t ADC_GetINTStatus(uint32_t INTMask) +{ + /* Parameter check */ + assert_parameters(IS_ADC_INTFLAGR(INTMask)); + + if (ANA->INTSTS & INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Gets ADC flag + * @param FlagMask + ADC_FLAG_CONV_ERR + ADC_FLAG_CAL_ERR + ADC_FLAG_CAL_DONE + ADC_FLAG_BUSY + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t ADC_GetFlag(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_ADC_ADCFLAG(FlagMask)); + + if (ANA->ADCCTRL2 & FlagMask) + return 1; + else + return 0; +} + +/** + * @brief Clears ADC flag + * @param FlagMask: status to clear, can use the '|' operator. + ADC_FLAG_CONV_ERR + ADC_FLAG_CAL_ERR + * @retval None + */ +void ADC_ClearFlag(uint32_t FlagMask) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_ADC_ADCFLAGC(FlagMask)); + + if (FlagMask == ADC_FLAG_CONV_ERR) + { + tmp = ANA->ADCCTRL2; + tmp &= ~ANA_ADCCTRL2_CAL_ERR_CLR; + tmp |= ANA_ADCCTRL2_CONV_ERR_CLR; + } + else if (FlagMask == ADC_FLAG_CAL_ERR) + { + tmp = ANA->ADCCTRL2; + tmp &= ~ANA_ADCCTRL2_CONV_ERR_CLR; + tmp |= ANA_ADCCTRL2_CAL_ERR_CLR; + } + else + { + tmp = ANA->ADCCTRL2; + tmp |= (ANA_ADCCTRL2_CAL_ERR_CLR | ANA_ADCCTRL2_CONV_ERR_CLR); + } + ANA->ADCCTRL2 = tmp; +} + +/** + * @brief Gets threshold flag + * @param THDFlagMask + ADC_THDFLAG_UPPER3 + ADC_THDFLAG_LOWER3 + ADC_THDFLAG_UPPER2 + ADC_THDFLAG_LOWER2 + ADC_THDFLAG_UPPER1 + ADC_THDFLAG_LOWER1 + ADC_THDFLAG_UPPER0 + ADC_THDFLAG_LOWER0 + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask) +{ + /* Parameter check */ + assert_parameters(IS_ADC_THDFLAG(THDFlagMask)); + + if(ANA->ADCDATATHD_CH & THDFlagMask) + return 1; + else + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_adc_tiny.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_adc_tiny.c new file mode 100644 index 0000000000..b24a8863e7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_adc_tiny.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file lib_adc_tiny.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief ADC_TINY library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_adc_tiny.h" + +#define ANA_REGF_RSTValue (0U) + +/** + * @brief Initializes the Tiny ADC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void TADC_DeInit(void) +{ + ANA->REGF = ANA_REGF_RSTValue; + ANA->INTSTS = ANA_INTSTS_INTSTS13; + ANA->INTEN &= ~ANA_INTEN_INTEN13; + ANA->MISC &= ~ANA_MISC_TADCTH; +} + +/** + * @brief Fills each TADC_InitStruct member with its default value. + * @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized. + * @retval None + */ +void TADC_StructInit(TADCInitType* TADC_InitStruct) +{ + /*--------------- Reset TADC init structure parameters values ---------------*/ + /* Initialize the SignalSel member */ + TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6; + /* Initialize the ADTREF1 member */ + TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9; + /* Initialize the ADTREF2 member */ + TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8; + /* Initialize the ADTREF3 member */ + TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7; +} + +/** + * @brief Initializes Tiny ADC. + * @param TADC_InitStruct + SelADT: + ADCTINY_SIGNALSEL_IOE6 + ADCTINY_SIGNALSEL_IOE7 + ADTREF1: + ADCTINY_REF1_0_9 + ADCTINY_REF1_0_7 + ADTREF2: + ADCTINY_REF2_1_8 + ADCTINY_REF2_1_6 + ADTREF3: + ADCTINY_REF3_2_7 + ADCTINY_REF3_2_5 + * @retval None + */ +void TADC_Init(TADCInitType* TADC_InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel)); + assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1)); + assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2)); + assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3)); + + tmp = ANA->REGF; + tmp &= ~(ANA_REGF_ADTSEL \ + |ANA_REGF_ADTREF1SEL\ + |ANA_REGF_ADTREF2SEL\ + |ANA_REGF_ADTREF3SEL); + tmp |= (TADC_InitStruct->SignalSel \ + |TADC_InitStruct->ADTREF1\ + |TADC_InitStruct->ADTREF2\ + |TADC_InitStruct->ADTREF3); + ANA->REGF = tmp; +} + +/** + * @brief Enables or disables Tiny ADC . + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void TADC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == ENABLE) + ANA->REGF |= ANA_REGF_ADTPDN; + else + ANA->REGF &= ~ANA_REGF_ADTPDN; +} + +/** + * @brief Gets Tiny ADC output value. + * @param None + * @retval Output of Tiny ADC(0 ~ 3). + */ +uint8_t TADC_GetOutput(void) +{ + return ((ANA->CMPOUT & ANA_CMPOUT_TADCO) >> ANA_CMPOUT_TADCO_Pos); +} + +/** + * @brief Configures Tiny ADC interrupt threshold. + * @param THSel: + ADCTINY_THSEL_0 + ADCTINY_THSEL_1 + ADCTINY_THSEL_2 + ADCTINY_THSEL_3 + * @retval None. + */ +void TADC_IntTHConfig(uint32_t THSel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADCTINY_THSEL(THSel)); + + tmp = ANA->MISC; + tmp &= ~ANA_MISC_TADCTH; + tmp |= THSel; + ANA->MISC = tmp; +} + +/** + * @brief Enables or disables Tiny ADC interrupt. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void TADC_INTConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == ENABLE) + ANA->INTEN |= ANA_INTEN_INTEN13; + else + ANA->INTEN &= ~ANA_INTEN_INTEN13; +} + +/** + * @brief Gets Tiny ADC interrupt status. + * @param None + * @retval Interrupt status. + */ +uint8_t TADC_GetINTStatus(void) +{ + if (ANA->INTSTS & ANA_INTSTS_INTSTS13) + return 1; + else + return 0; +} + +/** + * @brief Clears Tiny ADC interrupt status. + * @param None + * @retval None + */ +void TADC_ClearINTStatus(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS13; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_ana.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_ana.c new file mode 100644 index 0000000000..a9ed925f29 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_ana.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file lib_ana.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Analog library. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_ana.h" + +/** + * @brief Gets analog status. + * @param StatusMask: + ANA_STATUS_AVCCLV + ANA_STATUS_VDCINDROP + ANA_STATUS_VDDALARM + ANA_STATUS_CMP2 + ANA_STATUS_CMP1 + ANA_STATUS_LOCKL + ANA_STATUS_LOCKH + * @retval Analog status + */ +uint8_t ANA_GetStatus(uint32_t StatusMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_STATUS(StatusMask)); + + if (ANA->CMPOUT & StatusMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Gets analog interrupt status. + * @param IntMask: + ANA_INT_UPPER_TH3 + ANA_INT_LOWER_TH3 + ANA_INT_UPPER_TH2 + ANA_INT_LOWER_TH2 + ANA_INT_UPPER_TH1 + ANA_INT_LOWER_TH1 + ANA_INT_UPPER_TH0 + ANA_INT_LOWER_TH0 + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SLPFAIL_VDCIN + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_CMP2 + ANA_INT_CMP1 + ANA_INT_ADCA + ANA_INT_ADCM + * @retval interrupt status. + */ +uint8_t ANA_GetINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_INTSTSR(IntMask)); + + if (ANA->INTSTS&IntMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears analog interrupt status. + * @param IntMask:status to clear, can use the '|' operator. + ANA_INT_UPPER_TH3 + ANA_INT_LOWER_TH3 + ANA_INT_UPPER_TH2 + ANA_INT_LOWER_TH2 + ANA_INT_UPPER_TH1 + ANA_INT_LOWER_TH1 + ANA_INT_UPPER_TH0 + ANA_INT_LOWER_TH0 + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SLPFAIL_VDCIN + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_CMP2 + ANA_INT_CMP1 + ANA_INT_ADCA + ANA_INT_ADCM + * @retval None + */ +void ANA_ClearINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_INTSTSC(IntMask)); + + ANA->INTSTS = IntMask; +} + +/** + * @brief Enables or disables analog interrupt. + * @param IntMask:status to clear, can use the '|' operator. + ANA_INT_UPPER_TH3 + ANA_INT_LOWER_TH3 + ANA_INT_UPPER_TH2 + ANA_INT_LOWER_TH2 + ANA_INT_UPPER_TH1 + ANA_INT_LOWER_TH1 + ANA_INT_UPPER_TH0 + ANA_INT_LOWER_TH0 + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SLPFAIL_VDCIN + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_CMP2 + ANA_INT_CMP1 + ANA_INT_ADCA + ANA_INT_ADCM + NewState: + ENABLE + DISABLE + * @retval None + */ +void ANA_INTConfig(uint32_t IntMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ANA_INT(IntMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->INTEN; + if (NewState == ENABLE) + { + tmp |= IntMask; + } + else + { + tmp &= ~IntMask; + } + ANA->INTEN = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_clk.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_clk.c new file mode 100644 index 0000000000..d81f6e5e97 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_clk.c @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file lib_clk.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Clock library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_clk.h" + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the CLK_ClkInitStruct. + * + * @note This function performs the following: + * 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC, + * AHB clock source switch to RCH first. + * 2. configure clock (except AHB clock source configuration). - optional + * 3. configure AHB clock source. - optional + * 4. HCLK/PCLK divider configuration. - optional + * + * @note CLK_InitTypeDef *CLK_ClkInitStruct + * [in]CLK_ClkInitStruct->ClockType, can use the '|' operator, the selection of parameters is as follows + * CLK_TYPE_ALL + * CLK_TYPE_AHBSRC + * CLK_TYPE_PLLL + * CLK_TYPE_PLLH + * CLK_TYPE_XTALH + * CLK_TYPE_RTCCLK + * CLK_TYPE_HCLK + * CLK_TYPE_PCLK + * + * CLK_TYPE_ALL All clocks' configurations is valid + * CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid + * [in]CLK_ClkInitStruct->AHBSource: + * CLK_AHBSEL_6_5MRC + * CLK_AHBSEL_6_5MXTAL + * CLK_AHBSEL_HSPLL + * CLK_AHBSEL_RTCCLK + * CLK_AHBSEL_LSPLL + * CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid + * [in]CLK_ClkInitStruct->PLLL.State: + * CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid) + * CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid) + * [in]CLK_ClkInitStruct->PLLL.Source: + * CLK_PLLLSRC_RCL + * CLK_PLLLSRC_XTALL + * [in]CLK_ClkInitStruct->PLLL.Frequency: + * CLK_PLLL_26_2144MHz + * CLK_PLLL_13_1072MHz + * CLK_PLLL_6_5536MHz + * CLK_PLLL_3_2768MHz + * CLK_PLLL_1_6384MHz + * CLK_PLLL_0_8192MHz + * CLK_PLLL_0_4096MHz + * CLK_PLLL_0_2048MHz + * CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid + * [in]CLK_ClkInitStruct->PLLH.State: + * CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid) + * CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid) + * [in]CLK_ClkInitStruct->PLLH.Source: + * CLK_PLLHSRC_RCH + * CLK_PLLHSRC_XTALH + * [in]CLK_ClkInitStruct->PLLH.Frequency: + * CLK_PLLH_13_1072MHz + * CLK_PLLH_16_384MHz + * CLK_PLLH_19_6608MHz + * CLK_PLLH_22_9376MHz + * CLK_PLLH_26_2144MHz + * CLK_PLLH_29_4912MHz + * CLK_PLLH_32_768MHz + * CLK_PLLH_36_0448MHz + * CLK_PLLH_39_3216MHz + * CLK_PLLH_42_5984MHz + * CLK_PLLH_45_8752MHz + * CLK_PLLH_49_152MHz + * CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid + * [in]CLK_ClkInitStruct->XTALH.State: + * CLK_XTALH_ON + * CLK_XTALH_OFF + * CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid + * [in]CLK_ClkInitStruct->RTCCLK.Source: + * CLK_RTCCLKSRC_XTALL + * CLK_RTCCLKSRC_RCL + * [in]CLK_ClkInitStruct->RTCCLK.Divider: + * CLK_RTCCLKDIV_1 + * CLK_RTCCLKDIV_4 + * CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid + * [in]CLK_ClkInitStruct->HCLK.Divider: + * 1 ~ 256 + * CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid + * [in]CLK_ClkInitStruct->PCLK.Divider: + * 1 ~ 256 + * + * @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that + * contains the configuration information for the clocks. + * + * @retval None + */ +void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct) +{ + uint32_t tmp; + + assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType)); + + if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC) + { + /* Enable BGP */ + ANA->REG3 &= ~ANA_REG3_BGPPD; + /* Enable 6.5M RC */ + ANA->REG3 &= ~ANA_REG3_RCHPD; + + /* AHB clock source switch to RCH */ + MISC2->CLKSEL = 0; + } + + /*---------- XTALH configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH) + { + assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State)); + + /* XTALH state configure */ + ANA->REG3 &= ~ANA_REG3_XOHPDN; + ANA->REG3 |= CLK_ClkInitStruct->XTALH.State; + + } + + /*-------------------- PLLL configuration --------------------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL) + { + assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source)); + assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State)); + assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency)); + + /* PLLL state configure */ + if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON) + { + /* power up PLLL */ + ANA->REG3 |= ANA_REG3_PLLLPDN; + + /* Configure PLLL frequency */ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PLLLSEL; + tmp |= CLK_ClkInitStruct->PLLL.Frequency; + ANA->REG9 = tmp; + + /* Configure PLLL input clock selection */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_PLLL_SEL; + tmp |= CLK_ClkInitStruct->PLLL.Source; + PMU->CONTROL = tmp; + } + else + { + /* power down PLLL */ + ANA->REG3 &= ~ANA_REG3_PLLLPDN; + } + } + + /*-------------------- PLLH configuration --------------------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH) + { + assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source)); + assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State)); + assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency)); + + /* PLLH state configure */ + if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON) + { + /* Power up PLLH */ + ANA->REG3 |= ANA_REG3_PLLHPDN; + + /* Configure PLLH frequency */ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PLLHSEL; + tmp |= CLK_ClkInitStruct->PLLH.Frequency; + ANA->REG9 = tmp; + + /* Clock input source, XTALH, XOH power on*/ + if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH) + { + ANA->REG3 |= ANA_REG3_XOHPDN; + } + + /* Configure PLLH input clock selection */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_PLLH_SEL; + tmp |= CLK_ClkInitStruct->PLLH.Source; + PMU->CONTROL = tmp; + } + else + { + /* Power down PLLH */ + ANA->REG3 &= ~ANA_REG3_PLLHPDN; + } + } + + /*---------- RTCCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK) + { + assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source)); + assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider)); + + /* RTCCLK source(optional) */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_RTCCLK_SEL; + tmp |= CLK_ClkInitStruct->RTCCLK.Source; + PMU->CONTROL = tmp; + + /*----- RTCCLK Divider -----*/ + RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider); + } + + /*---------- AHB clock source configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC) + { + assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource)); + + /* clock source: 6.5M RC */ + if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC) + { + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: 6_5MXTAL */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL) + { + /* Power up 6.5M xtal */ + ANA->REG3 |= ANA_REG3_XOHPDN; + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: PLLH */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL) + { + /* Power up PLLH */ + ANA->REG3 |= ANA_REG3_PLLHPDN; + /* while loop until PLLL is lock */ + while (!(ANA->CMPOUT & ANA_CMPOUT_LOCKH)) + { + } + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: PLLL */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL) + { + /* Power up PLLL */ + ANA->REG3 |= ANA_REG3_PLLLPDN; + /* while loop until PLLL is lock */ + while (!(ANA->CMPOUT & ANA_CMPOUT_LOCKL)) + { + } + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + /* clock source: RTCCLK */ + else + { + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + } + + /*---------- HCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK) + { + assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider)); + + MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1; + } + + /*---------- PCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK) + { + assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider)); + + MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1; + } +} + +/** + * @brief Enables or disables AHB Periphral clock. + * @param Periphral: can use the '|' operator + CLK_AHBPERIPHRAL_DMA + CLK_AHBPERIPHRAL_GPIO + CLK_AHBPERIPHRAL_LCD + CLK_AHBPERIPHRAL_CRYPT + NewState: + ENABLE + DISABLE + * @retval None. + */ +void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC2->HCLKEN |= Periphral; + } + else + { + MISC2->HCLKEN &= ~Periphral; + } +} + +/** + * @brief Enables or disables APB Periphral clock. + * @param Periphral: can use the '|' operator + CLK_APBPERIPHRAL_DMA + CLK_APBPERIPHRAL_I2C + CLK_APBPERIPHRAL_SPI1 + CLK_APBPERIPHRAL_SPI2 + CLK_APBPERIPHRAL_UART0 + CLK_APBPERIPHRAL_UART1 + CLK_APBPERIPHRAL_UART2 + CLK_APBPERIPHRAL_UART3 + CLK_APBPERIPHRAL_UART4 + CLK_APBPERIPHRAL_UART5 + CLK_APBPERIPHRAL_ISO78160 + CLK_APBPERIPHRAL_ISO78161 + CLK_APBPERIPHRAL_TIMER + CLK_APBPERIPHRAL_MISC1 + CLK_APBPERIPHRAL_MISC2 + CLK_APBPERIPHRAL_PMU + CLK_APBPERIPHRAL_RTC + CLK_APBPERIPHRAL_ANA + CLK_APBPERIPHRAL_U32K0 + CLK_APBPERIPHRAL_U32K1 + CLK_APBPERIPHRAL_SPI3 + NewState: + ENABLE + DISABLE + * @retval None. + */ +void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CLK_APBPERIPHRAL(Periphral)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC2->PCLKEN |= Periphral; + } + else + { + MISC2->PCLKEN &= ~Periphral; + } +} + +/** + * @brief Returns the HCLK frequency + * @param None + * @retval HCLK frequency + */ +uint32_t CLK_GetHCLKFreq(void) +{ + uint32_t ahb_clksrc; + uint32_t ahb_div; + uint32_t pllh_frq; + uint32_t plll_frq; + uint32_t rtcclk_div; + uint32_t hclk; + + /* Get current AHB clock source */ + ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL; + /* Get AHB clock divider */ + ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1; + + switch (ahb_clksrc) + { + /* AHB Clock source : 6.5M RC */ + case MISC2_CLKSEL_CLKSEL_RCOH: + hclk = 6553600 / ahb_div; + break; + + /* AHB Clock source : 6.5M XTAL */ + case MISC2_CLKSEL_CLKSEL_XOH: + hclk = 6553600 / ahb_div; + break; + + /* AHB Clock source : PLLH */ + case MISC2_CLKSEL_CLKSEL_PLLH: + /* Get PLLH Frequency */ + pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL; + switch (pllh_frq) + { + case ANA_REG9_PLLHSEL_X2: + hclk = 13107200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X2_5: + hclk = 16384000 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X3: + hclk = 19660800 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X3_5: + hclk = 22937600 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X4: + hclk = 26214400 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X4_5: + hclk = 29491200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X5: + hclk = 32768000 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X5_5: + hclk = 36044800 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X6: + hclk = 39321600 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X6_5: + hclk = 42598400 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X7: + hclk = 45875200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X7_5: + hclk = 49152000 / ahb_div; + break; + + default: + hclk = 0; + break; + } + break; + + /* AHB Clock source : RTCCLK */ + case MISC2_CLKSEL_CLKSEL_RTCCLK: + /* Get current RTC clock divider */ + rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA; + if (rtcclk_div == RTC_PSCA_PSCA_0) + { + hclk = 32768 / ahb_div; + } + else if (rtcclk_div == RTC_PSCA_PSCA_1) + { + hclk = 8192 / ahb_div; + } + else + { + hclk = 0; + } + break; + + /* AHB Clock source : PLLL */ + case MISC2_CLKSEL_CLKSEL_PLLL: + /* Get PLLL Frequency */ + plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL; + switch (plll_frq) + { + case ANA_REG9_PLLLSEL_26M: + hclk = 26214400 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_13M: + hclk = 13107200 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_6_5M: + hclk = 6553600 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_3_2M: + hclk = 3276800 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_1_6M: + hclk = 1638400 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_800K: + hclk = 819200 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_400K: + hclk = 409600 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_200K: + hclk = 204800 / ahb_div; + break; + + default: + hclk = 0; + break; + } + break; + + default: + hclk = 0; + break; + } + + return (hclk); +} + +/** + * @brief Returns the PLLL frequency + * @param None + * @retval PLLL frequency + */ +uint32_t CLK_GetPLLLFreq(void) +{ + uint32_t plll_frq; + + if (!(ANA->REG3 & ANA_REG3_PLLLPDN)) + return 0; + /* Get PLLL Frequency */ + plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL; + switch (plll_frq) + { + case ANA_REG9_PLLLSEL_26M: + plll_frq = 26214400; + break; + + case ANA_REG9_PLLLSEL_13M: + plll_frq = 13107200; + break; + + case ANA_REG9_PLLLSEL_6_5M: + plll_frq = 6553600; + break; + + case ANA_REG9_PLLLSEL_3_2M: + plll_frq = 3276800; + break; + + case ANA_REG9_PLLLSEL_1_6M: + plll_frq = 1638400; + break; + + case ANA_REG9_PLLLSEL_800K: + plll_frq = 819200; + break; + + case ANA_REG9_PLLLSEL_400K: + plll_frq = 409600; + break; + + case ANA_REG9_PLLLSEL_200K: + plll_frq = 204800; + break; + + default: + plll_frq = 0; + break; + } + + return (plll_frq); +} + +/** + * @brief Returns the PCLK frequency + * @param None + * @retval PCLK frequency + */ +uint32_t CLK_GetPCLKFreq(void) +{ + return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1)); +} + +/** + * @brief Get the CLK_ClkInitStruct according to the internal + * Clock configuration registers. + * + * @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that + * contains the current clock configuration. + * + * @retval None + */ +void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL; + + /* Get AHB clock source ----------------------------------------------------*/ + CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL); + /* Get PLLL clock configration ---------------------------------------------*/ + CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL); + CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL); + CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN); + /* Get PLLH clock configuration --------------------------------------------*/ + CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL); + CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL); + CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN); + /* Get XTALH configuration -------------------------------------------------*/ + CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN); + /* Get HCLK(Divider) configuration -----------------------------------------*/ + CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1); + /* Get PCLK((Divider) configuration ----------------------------------------*/ + CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1); +} + +/** + * @brief Gets current external 6.5M crystal status. + * + * @param None + * + * @retval 6.5M crystal status + * 0: 6.5536M crystal is absent. + * 1: 6.5536M crystal is present. + */ +uint8_t CLK_GetXTALHStatus(void) +{ + if (PMU->STS & PMU_STS_EXIST_6M) + return (1); + else + return (0); +} + +/** + * @brief Gets current external 32K crystal status. + * + * @param None + * + * @retval 32K crystal status + * 0: 32K crystal is absent + * 1: 32K crystal is present. + */ +uint8_t CLK_GetXTALLStatus(void) +{ + if (PMU->STS & PMU_STS_EXIST_32K) + return (1); + else + return (0); +} + +/** + * @brief Gets PLL lock status. + * @param PLLStatus: + * CLK_STATUS_LOCKL + * CLK_STATUS_LOCKH + * @retval PLL lock status + * 0 PLL is not locked. + * 1 PLL is locked. + */ +uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus) +{ + /* Check parameters */ + assert_parameters(IS_CLK_PLLLOCK(PLLStatus)); + + if (ANA->CMPOUT & PLLStatus) + return 1; + else + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_cmp.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_cmp.c new file mode 100644 index 0000000000..3621936444 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_cmp.c @@ -0,0 +1,583 @@ +/** + ****************************************************************************** + * @file lib_cmp.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief CMP library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_cmp.h" + +/* CMP1 reset values */ +#define CMP1_REG2_Msk (0x13UL) +#define CMP1_REG3_Msk (0x02UL) +#define CMP1_REG5_Msk (0x03UL) +#define CMP1_REGF_Msk (0x01UL) +#define CMP1_CTRL_Msk (0x300003UL) +#define CMP1_INTSTS_Msk (0x04UL) +#define CMP1_INTEN_Msk (0x04UL) +#define CMP1_THR_Msk (0xFFFFUL) +#define CMP1_CTL_Msk (0x300FFUL) +/* CMP2 reset values */ +#define CMP2_REG2_Msk (0x2CUL) +#define CMP2_REG3_Msk (0x04UL) +#define CMP2_REG5_Msk (0x0CUL) +#define CMP2_REGF_Msk (0x02UL) +#define CMP2_CTRL_Msk (0xC0000CUL) +#define CMP2_INTSTS_Msk (0x08UL) +#define CMP2_INTEN_Msk (0x08UL) +#define CMP2_THR_Msk (0xFFFF0000UL) +#define CMP2_CTL_Msk (0x30FF00UL) + +/** + * @brief Initializes the Comparator peripheral registers to their default reset values. + * @param CMPx: + CMP_1 + CMP_2 + * @retval None + */ +void CMP_DeInit(uint32_t CMPx) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + + if (CMPx == CMP_1) + { + ANA->REG2 &= ~CMP1_REG2_Msk; + ANA->REG3 &= ~CMP1_REG3_Msk; + ANA->REG5 &= ~CMP1_REG5_Msk; + ANA->REGF &= ~CMP1_REGF_Msk; + ANA->CTRL &= ~CMP1_CTRL_Msk; + ANA->INTSTS = CMP1_INTSTS_Msk; + ANA->INTEN &= ~CMP1_INTEN_Msk; + ANA->CMPTHR &= ~CMP1_THR_Msk; + ANA->CMPCTL &= ~CMP1_CTL_Msk; + ANA->CMPCNT1 = 0; + } + else + { + ANA->REG2 &= ~CMP2_REG2_Msk; + ANA->REG3 &= ~CMP2_REG3_Msk; + ANA->REG5 &= ~CMP2_REG5_Msk; + ANA->REGF &= ~CMP2_REGF_Msk; + ANA->CTRL &= ~CMP2_CTRL_Msk; + ANA->INTSTS = CMP2_INTSTS_Msk; + ANA->INTEN &= ~CMP2_INTEN_Msk; + ANA->CMPTHR &= ~CMP2_THR_Msk; + ANA->CMPCTL &= ~CMP2_CTL_Msk; + ANA->CMPCNT2 = 0; + } +} + +/** + * @brief Initializes comparator. + * @param CMPx: + CMP_1 + CMP_2 + InitStruct: Comparator configuration + DebSel: + CMP_DEB_NONE + CMP_DEB_RTCCLK_2 + CMP_DEB_RTCCLK_3 + CMP_DEB_RTCCLK_4 + SignalSourceSel: + CMP_SIGNALSRC_PPIN_TO_VREF + CMP_SIGNALSRC_PPIN_TO_BGPREF + CMP_SIGNALSRC_PBAT_TO_VREF + CMP_SIGNALSRC_PBAT_TO_BGPREF + CMP_SIGNALSRC_NPIN_TO_VREF + CMP_SIGNALSRC_NPIN_TO_BGPREF + CMP_SIGNALSRC_PPIN_TO_NPIN + CMP_SIGNALSRC_PBAT_TO_NPIN + BiasSel: + CMP_BIAS_20nA + CMP_BIAS_100nA + CMP_BIAS_500nA + * @retval None + */ +void CMP_Init(uint32_t CMPx, CMP_TypeDef *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + assert_parameters(IS_CMP_DEB(InitStruct->DebSel)); + assert_parameters(IS_CMP_SIGNALSRC(InitStruct->SignalSourceSel)); + assert_parameters(IS_CMP_BIAS(InitStruct->BiasSel)); + + /* CMP1 Configure */ + if (CMPx == CMP_1) + { + tmp = ANA->CTRL; + tmp &= ~ANA_CTRL_CMP1DEB; + tmp |= (InitStruct->DebSel << ANA_CTRL_CMP1DEB_Pos); + ANA->CTRL = tmp; + + tmp = ANA->REG5; + tmp &= ~ANA_REG5_CMP1IT; + tmp |= (InitStruct->BiasSel << ANA_REG5_CMP1IT_Pos); + ANA->REG5 = tmp; + + ANA->REG2 &= ~(ANA_REG2_CMP1SEL|ANA_REG2_CMP1REFSEL); + ANA->REGF &= ~ANA_REGF_BAT1DETEN; + switch(InitStruct->SignalSourceSel) + { + case CMP_SIGNALSRC_PPIN_TO_VREF: + break; + case CMP_SIGNALSRC_PPIN_TO_BGPREF: + ANA->REG2 |= ANA_REG2_CMP1REFSEL; + break; + case CMP_SIGNALSRC_PBAT_TO_VREF: + ANA->REGF |= ANA_REGF_BAT1DETEN; + break; + case CMP_SIGNALSRC_PBAT_TO_BGPREF: + ANA->REG2 |= ANA_REG2_CMP1REFSEL; + ANA->REGF |= ANA_REGF_BAT1DETEN; + break; + case CMP_SIGNALSRC_NPIN_TO_VREF: + ANA->REG2 |= ANA_REG2_CMP1SEL_1; + break; + case CMP_SIGNALSRC_NPIN_TO_BGPREF: + ANA->REG2 |= (ANA_REG2_CMP1SEL_1|ANA_REG2_CMP1REFSEL); + break; + case CMP_SIGNALSRC_PPIN_TO_NPIN: + ANA->REG2 |= ANA_REG2_CMP1SEL_3; + break; + case CMP_SIGNALSRC_PBAT_TO_NPIN: + ANA->REG2 |= ANA_REG2_CMP1SEL_3; + ANA->REGF |= ANA_REGF_BAT1DETEN; + break; + default: + break; + } + } + /* CMP2 Configure */ + else + { + tmp = ANA->CTRL; + tmp &= ~ANA_CTRL_CMP2DEB; + tmp |= (InitStruct->DebSel << ANA_CTRL_CMP2DEB_Pos); + ANA->CTRL = tmp; + + tmp = ANA->REG5; + tmp &= ~ANA_REG5_CMP2IT; + tmp |= (InitStruct->BiasSel << ANA_REG5_CMP2IT_Pos); + ANA->REG5 = tmp; + + ANA->REG2 &= ~(ANA_REG2_CMP2SEL|ANA_REG2_CMP2REFSEL); + ANA->REGF &= ~ANA_REGF_BATRTCDETEN; + switch(InitStruct->SignalSourceSel) + { + case CMP_SIGNALSRC_PPIN_TO_VREF: + break; + case CMP_SIGNALSRC_PPIN_TO_BGPREF: + ANA->REG2 |= ANA_REG2_CMP2REFSEL; + break; + case CMP_SIGNALSRC_PBAT_TO_VREF: + ANA->REGF |= ANA_REGF_BATRTCDETEN; + break; + case CMP_SIGNALSRC_PBAT_TO_BGPREF: + ANA->REG2 |= ANA_REG2_CMP2REFSEL; + ANA->REGF |= ANA_REGF_BATRTCDETEN; + break; + case CMP_SIGNALSRC_NPIN_TO_VREF: + ANA->REG2 |= ANA_REG2_CMP2SEL_1; + break; + case CMP_SIGNALSRC_NPIN_TO_BGPREF: + ANA->REG2 |= (ANA_REG2_CMP2SEL_1|ANA_REG2_CMP2REFSEL); + break; + case CMP_SIGNALSRC_PPIN_TO_NPIN: + ANA->REG2 |= ANA_REG2_CMP2SEL_3; + break; + case CMP_SIGNALSRC_PBAT_TO_NPIN: + ANA->REG2 |= ANA_REG2_CMP2SEL_3; + ANA->REGF |= ANA_REGF_BATRTCDETEN; + break; + default: + break; + } + } +} + +/** + * @brief Fills each CMP_TypeDef member with its default value. + * @param InitStruct: pointer to an CMP_TypeDef structure which will be initialized. + * @retval None + */ +void CMP_StructInit(CMP_TypeDef *InitStruct) +{ + InitStruct->DebSel = CMP_DEB_NONE; + InitStruct->SignalSourceSel = CMP_SIGNALSRC_PPIN_TO_VREF; + InitStruct->BiasSel = CMP_BIAS_20nA; +} + +/** + * @brief Initializes comparator Count. + * @param CMPx: + CMP_1 + CMP_2 + InitStruct: Comparator configuration + ModeSel: + CMP_MODE_OFF + CMP_MODE_RISING + CMP_MODE_FALLING + CMP_MODE_BOTH + CheckPeriod: + CMP_PERIOD_30US + CMP_PERIOD_7_8125MS + CMP_PERIOD_125MS + CMP_PERIOD_250MS + CMP_PERIOD_500MS + CheckNum: + CMP_CHKNUM_1~CMP_CHKNUM_16 + * @retval None + */ +void CMP_CountInit(uint32_t CMPx, CMP_CountTypeDef *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + assert_parameters(IS_CMP_MODE(InitStruct->ModeSel)); + assert_parameters(IS_CMP_CHECKPERIOD(InitStruct->CheckPeriod)); + assert_parameters(IS_CMP_CHKNUM(InitStruct->CheckNum)); + + /* CMP1 Configure */ + if (CMPx == CMP_1) + { + /* Configure ModeSel */ + tmp = ANA->CTRL; + tmp &= ~ANA_CTRL_CMP1SEL; + tmp |= (InitStruct->ModeSel << ANA_CTRL_CMP1SEL_Pos); + ANA->CTRL = tmp; + + /* Configure CheckPeriod/CheckNum */ + tmp = ANA->CMPCTL; + tmp &= ~(ANA_CMPCTL_CMP1_CHK_FRQ|ANA_CMPCTL_CMP1_CHK_NUM); + tmp |= ((InitStruct->CheckPeriod << ANA_CMPCTL_CMP1_CHK_FRQ_Pos) | \ + (InitStruct->CheckNum << ANA_CMPCTL_CMP1_CHK_NUM_Pos)); + ANA->CMPCTL = tmp; + } + /* CMP2 Configure */ + else + { + /* Configure ModeSel */ + tmp = ANA->CTRL; + tmp &= ~ANA_CTRL_CMP2SEL; + tmp |= (InitStruct->ModeSel << ANA_CTRL_CMP2SEL_Pos); + ANA->CTRL = tmp; + + /* Configure CheckPeriod/CheckNum */ + tmp = ANA->CMPCTL; + tmp &= ~(ANA_CMPCTL_CMP2_CHK_FRQ|ANA_CMPCTL_CMP2_CHK_NUM); + tmp |= ((InitStruct->CheckPeriod << ANA_CMPCTL_CMP2_CHK_FRQ_Pos) | \ + (InitStruct->CheckNum << ANA_CMPCTL_CMP2_CHK_NUM_Pos)); + ANA->CMPCTL = tmp; + } +} + +/** + * @brief Fill each CMP_CountTypeDef member with its default value. + * @param InitStruct: pointer to an CMP_CountTypeDef structure which will be initialized. + * @retval None + */ +void CMP_CountStructInit(CMP_CountTypeDef *InitStruct) +{ + InitStruct->ModeSel = CMP_MODE_OFF; + InitStruct->CheckPeriod = CMP_PERIOD_30US; + InitStruct->CheckNum = CMP_CHKNUM_1; +} + +/** + * @brief Initializes Comparator interrupt. + * @param CMPx: + CMP_1 + CMP_2 + InitStruct: Comparator configuration + INTNumSel: + CMP_INTNUM_EVERY + CMP_INTNUM_1 + SubSel: + CMP_COUNT_NOSUB + CMP_COUNT_SUB + THRNum:0~65535 + * @retval None + */ +void CMP_INTInit(uint32_t CMPx, CMP_INTTypeDef *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + assert_parameters(IS_CMP_INTNUM(InitStruct->INTNumSel)); + assert_parameters(IS_CMP_COUNT(InitStruct->SubSel)); + assert_parameters(IS_CMP_THRNUM(InitStruct->THRNum)); + + /* CMP1 Configure */ + if (CMPx == CMP_1) + { + /* Configure INTNumSel/SubSel */ + tmp = ANA->CMPCTL; + tmp &= ~(ANA_CMPCTL_CMP1_THR_EN|ANA_CMPCTL_CMP1_INT_MASK_EN); + tmp |= ((InitStruct->SubSel << ANA_CMPCTL_CMP1_THR_EN_Pos) | \ + (InitStruct->INTNumSel << ANA_CMPCTL_CMP1_INT_MASK_EN_Pos)); + ANA->CMPCTL = tmp; + + /* Configure THRNum */ + tmp = ANA->CMPTHR; + tmp &= ~ANA_CMPTHR_CMP1_THR; + tmp |= (InitStruct->THRNum << ANA_CMPTHR_CMP1_THR_Pos); + ANA->CMPTHR = tmp; + } + /* CMP2 Configure */ + else + { + /* Configure INTNumSel/SubSel */ + tmp = ANA->CMPCTL; + tmp &= ~(ANA_CMPCTL_CMP2_THR_EN|ANA_CMPCTL_CMP2_INT_MASK_EN); + tmp |= ((InitStruct->SubSel << ANA_CMPCTL_CMP2_THR_EN_Pos) | \ + (InitStruct->INTNumSel << ANA_CMPCTL_CMP2_INT_MASK_EN_Pos)); + ANA->CMPCTL = tmp; + + /* Configure THRNum */ + tmp = ANA->CMPTHR; + tmp &= ~ANA_CMPTHR_CMP2_THR; + tmp |= (InitStruct->THRNum << ANA_CMPTHR_CMP2_THR_Pos); + ANA->CMPTHR = tmp; + } +} + +/** + * @brief Fills each CMP_INTTypeDef member with its default value. + * @param InitStruct: pointer to an CMP_INTTypeDef structure which will be initialized. + * @retval None + */ +void CMP_INTStructInit(CMP_INTTypeDef *InitStruct) +{ + InitStruct->INTNumSel = CMP_INTNUM_EVERY; + InitStruct->SubSel = CMP_COUNT_NOSUB; + InitStruct->THRNum = 0; +} + +/** + * @brief Initializes Comparator Output IO. + * @param CMPx: + CMP_1 + CMP_2 + InitStruct: Comparator configuration + DebSel: + CMP_OUTPUT_DEB + CMP_OUTPUT_NODEB + OutputSel: + ENABLE + DISABLE + * @retval None + */ +void CMP_OutputInit(uint32_t CMPx, CMP_OutputTypeDef *InitStruct) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + assert_parameters(IS_CMP_OUTPUTDEB(InitStruct->DebSel)); + assert_parameters(IS_FUNCTIONAL_STATE(InitStruct->OutputSel)); + + /* CMP1 Configure */ + if (CMPx == CMP_1) + { + ANA->CMPCTL &= ~ANA_CMPCTL_CMP1_IO_NODEB; + ANA->CMPCTL |= (InitStruct->DebSel << ANA_CMPCTL_CMP1_IO_NODEB_Pos); + + GPIOAF->IOE_SEL &= ~GPIOAF_IOE_SEL_SEL7; + GPIOAF->IOE_SEL |= (InitStruct->OutputSel << GPIOAF_IOE_SEL_SEL7_Pos); + } + /* CMP2 Configure */ + else + { + ANA->CMPCTL &= ~ANA_CMPCTL_CMP2_IO_NODEB; + ANA->CMPCTL |= (InitStruct->DebSel << ANA_CMPCTL_CMP2_IO_NODEB_Pos); + + GPIOA->SEL &= ~GPIOA_SEL_SEL6; + GPIOA->SEL |= (InitStruct->OutputSel << GPIOA_SEL_SEL6_Pos); + } +} + +/** + * @brief Fills each CMP_OutputTypeDef member with its default value. + * @param InitStruct: pointer to an CMP_OutputTypeDef structure which will be initialized. + * @retval None + */ +void CMP_OutputStructInit(CMP_OutputTypeDef *InitStruct) +{ + InitStruct->DebSel = CMP_OUTPUT_DEB; + InitStruct->OutputSel = DISABLE; +} + +/** + * @brief Gets comparator count value. + * @param CMPx: + CMP_1 + CMP_2 + * @retval Comparator count value. + */ +uint32_t CMP_GetCNTValue(uint32_t CMPx) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + + if (CMPx == CMP_1) + { + return ANA->CMPCNT1; + } + else + { + return ANA->CMPCNT2; + } +} + +/** + * @brief Clears comparator counter value. + * @param CMPx: + CMP_1 + CMP_2 + * @retval None + */ +void CMP_ClearCNTValue(uint32_t CMPx) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + + if (CMPx == CMP_1) + { + ANA->CMPCNT1 = 0; + } + else + { + ANA->CMPCNT2 = 0; + } +} + +/** + * @brief Enables or disables Comparator. + * @param CMPx: + CMP_1 + CMP_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void CMP_Cmd(uint32_t CMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (CMPx == CMP_1) + { + ANA->REG3 &= ~ANA_REG3_CMP1PDN; + ANA->REG3 |= (NewState << ANA_REG3_CMP1PDN_Pos); + } + else + { + ANA->REG3 &= ~ANA_REG3_CMP2PDN; + ANA->REG3 |= (NewState << ANA_REG3_CMP2PDN_Pos); + } +} + +/** + * @brief Gets comparator output level + * @param None + * @retval Output of comparator + */ +uint8_t CMP_GetOutputValue(uint32_t CMPx) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + + if (CMPx == CMP_1) + { + return ((ANA->CMPOUT & ANA_CMPOUT_CMP1) >> ANA_CMPOUT_CMP1_Pos); + } + else + { + return ((ANA->CMPOUT & ANA_CMPOUT_CMP2) >> ANA_CMPOUT_CMP2_Pos); + } +} + +/** + * @brief Enables or disables Comparator interrupt. + * @param CMPx: + * CMP_1 + * CMP_2 + * NewState: + * ENABLE + * DISABLE + * @retval None + */ +void CMP_INTConfig(uint32_t CMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + + if (CMPx == CMP_1) + { + ANA->INTEN &= ~ANA_INTEN_INTEN2; + ANA->INTEN |= (NewState<INTEN &= ~ANA_INTEN_INTEN3; + ANA->INTEN |= (NewState<INTSTS & ANA_INTSTS_INTSTS2) >> ANA_INTSTS_INTSTS2_Pos); + } + else + { + return ((ANA->INTSTS & ANA_INTSTS_INTSTS3) >> ANA_INTSTS_INTSTS3_Pos); + } +} + +/** + * @brief Clears comparator interrupt flag. + * @param CMPx: + * CMP_1 + * CMP_2 + * @retval None + */ +void CMP_ClearINTStatus(uint32_t CMPx) +{ + /* Check parameters */ + assert_parameters(IS_CMP(CMPx)); + + if (CMPx == CMP_1) + { + ANA->INTSTS = ANA_INTSTS_INTSTS2; + } + else + { + ANA->INTSTS = ANA_INTSTS_INTSTS3; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_crypt.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_crypt.c new file mode 100644 index 0000000000..9c253482ae --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_crypt.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file lib_crypt.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief CRYPT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_crypt.h" + +/** + * @brief Configures PTRA register, data in this address will be read out to do + * the CRYPT calculation + * @param AddrA: the SRAM address(Bit 15:0) + * @retval None + */ +void CRYPT_AddressAConfig(uint16_t AddrA) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrA)); + + CRYPT->PTRA = AddrA & CRYPT_PTRA_PTRA; +} + +/** + * @brief Configures PTRB register, data in this address will be read out to do + * the CRYPT calculation + * @param AddrB: the SRAM address(Bit 15:0) + * @retval None + */ +void CRYPT_AddressBConfig(uint16_t AddrB) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrB)); + + CRYPT->PTRB = AddrB & CRYPT_PTRB_PTRB; +} + +/** + * @brief Configures PTRO register, The CRYPT engine will write calculation + * result into this address + * @param AddrO: the SRAM address(Bit 15:0) + * @retval None + */ +void CRYPT_AddressOConfig(uint16_t AddrO) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrO)); + + CRYPT->PTRO = AddrO & CRYPT_PTRO_PTRO; +} + +/** + * @brief Gets carry/borrow bit of add/sub operation. + * @param None + * @retval carry/borrow bit value + */ +uint8_t CRYPT_GetCarryBorrowBit(void) +{ + if (CRYPT->CARRY & CRYPT_CARRY_CARRY) + return (1); + else + return (0); +} + +/** + * @brief Starts addition operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_ADD \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Starts multiplication operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_MULTIPLY \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Starts subtraction operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartSub(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_SUB \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Starts rigth shift 1-bit operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_RSHIFT1 \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Waits until last operation to complete. + * @param None + * @retval None + */ +void CRYPT_WaitForLastOperation(void) +{ + while (CRYPT->CTRL & CRYPT_CTRL_ACT) + { + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_dma.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_dma.c new file mode 100644 index 0000000000..5f8bcee7fb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_dma.c @@ -0,0 +1,473 @@ +/** + ****************************************************************************** + * @file lib_dma.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief DMA library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_dma.h" + +//registers default reset values +#define DMA_CxCTL_RSTValue (0UL) +#define DMA_CxSRC_RSTValue (0UL) +#define DMA_CxDST_RSTValue (0UL) +#define DMA_AESCTL_RSTValue (0UL) +#define DMA_AESKEY_RSTValue (0UL) + +/** + * @brief Initializes the DMA channel peripheral registers to their default reset values. + * @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3 + * @retval None + */ +void DMA_DeInit(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + /* channel x disable, clear stop */ + addr = &DMA->C0CTL + Channel*4; + *addr &= ~(DMA_CCTL_EN | DMA_CCTL_STOP); + + /* interrupt disable */ + DMA->IE &= ~((1<<(Channel))\ + |(1<<(Channel+4))\ + |(1<<(Channel+8))); + + /* interrupt state clear */ + DMA->STS = (1<<(Channel+4))\ + |(1<<(Channel+8))\ + |(1<<(Channel+12)); + + /* DMA_CxCTL */ + addr = &DMA->C0CTL + Channel*4; + *addr = DMA_CxCTL_RSTValue; + + /* DMA_CxSRC */ + addr = &DMA->C0SRC + Channel*4; + *addr = DMA_CxSRC_RSTValue; + + /* DMA_CxDST */ + addr = &DMA->C0DST + Channel*4; + *addr = DMA_CxDST_RSTValue; +} +/** + * @brief Fills each DMA_InitType member with its default value. + * @param InitStruct: pointer to an DMA_InitType structure which will be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitType *InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ---------------*/ + /* Initialize the DestAddr member */ + InitStruct->DestAddr = 0; + /* Initialize the SrcAddr member */ + InitStruct->SrcAddr = 0; + /* Initialize the FrameLen member */ + InitStruct->FrameLen = 0; + /* Initialize the PackLen member */ + InitStruct->PackLen = 0; + /* Initialize the ContMode member */ + InitStruct->ContMode = DMA_CONTMODE_DISABLE; + /* Initialize the TransMode member */ + InitStruct->TransMode = DMA_TRANSMODE_SINGLE; + /* Initialize the ReqSrc member */ + InitStruct->ReqSrc = DMA_REQSRC_SOFT; + /* Initialize the DestAddrMode member */ + InitStruct->DestAddrMode = DMA_DESTADDRMODE_FIX; + /* Initialize the SrcAddrMode member */ + InitStruct->SrcAddrMode = DMA_SRCADDRMODE_FIX; + /* Initialize the TransSize member */ + InitStruct->TransSize = DMA_TRANSSIZE_BYTE; +} +/** + * @brief Initializes DMA channel. + * @param InitStruct: DMA configuration. + DestAddr : destination address + SrcAddr : source address + FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1) + PackLen : Package length (Ranges 0~255, actual length PackLen+1) + ContMode: + DMA_CONTMODE_ENABLE + DMA_CONTMODE_DISABLE + TransMode: + DMA_TRANSMODE_SINGLE + DMA_TRANSMODE_PACK + ReqSrc: + DMA_REQSRC_SOFT + DMA_REQSRC_ADC + DMA_REQSRC_UART0TX + DMA_REQSRC_UART0RX + DMA_REQSRC_UART1TX + DMA_REQSRC_UART1RX + DMA_REQSRC_UART2TX + DMA_REQSRC_UART2RX + DMA_REQSRC_UART3TX + DMA_REQSRC_UART3RX + DMA_REQSRC_UART4TX + DMA_REQSRC_UART4RX + DMA_REQSRC_UART5TX + DMA_REQSRC_UART5RX + DMA_REQSRC_ISO78160TX + DMA_REQSRC_ISO78160RX + DMA_REQSRC_ISO78161TX + DMA_REQSRC_ISO78161RX + DMA_REQSRC_TIMER0 + DMA_REQSRC_TIMER1 + DMA_REQSRC_TIMER2 + DMA_REQSRC_TIMER3 + DMA_REQSRC_SPI1TX + DMA_REQSRC_SPI1RX + DMA_REQSRC_U32K0 + DMA_REQSRC_U32K1 + DMA_REQSRC_CMP1 + DMA_REQSRC_CMP2 + DMA_REQSRC_SPI2TX + DMA_REQSRC_SPI2RX + DMA_REQSRC_SPI3TX + DMA_REQSRC_SPI3RX + DestAddrMode: + DMA_DESTADDRMODE_FIX + DMA_DESTADDRMODE_PEND + DMA_DESTADDRMODE_FEND + SrcAddrMode: + DMA_SRCADDRMODE_FIX + DMA_SRCADDRMODE_PEND + DMA_SRCADDRMODE_FEND + TransSize: + DMA_TRANSSIZE_BYTE + DMA_TRANSSIZE_HWORD + DMA_TRANSSIZE_WORD + Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval None + */ +void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel) +{ + uint32_t tmp; + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode)); + assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode)); + assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc)); + assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode)); + assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode)); + assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize)); + + if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD) + { + assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr)); + assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr)); + } + if (InitStruct->TransSize == DMA_TRANSSIZE_WORD) + { + assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr)); + assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr)); + } + + addr = &DMA->C0DST + Channel*4; + *addr = InitStruct->DestAddr; + + addr = &DMA->C0SRC + Channel*4; + *addr = InitStruct->SrcAddr; + + addr = &DMA->C0CTL + Channel*4; + + tmp = *addr; + tmp &= ~(DMA_CCTL_FLEN\ + |DMA_CCTL_PLEN\ + |DMA_CCTL_CONT\ + |DMA_CCTL_TMODE\ + |DMA_CCTL_DMASEL\ + |DMA_CCTL_DMODE\ + |DMA_CCTL_SMODE\ + |DMA_CCTL_SIZE); + tmp |= ((InitStruct->FrameLen<PackLen<ContMode)\ + |(InitStruct->TransMode)\ + |(InitStruct->ReqSrc)\ + |(InitStruct->DestAddrMode)\ + |(InitStruct->SrcAddrMode)\ + |(InitStruct->TransSize)); + *addr = tmp; +} + +/** + * @brief Initializes the DMA AES channel3 registers to their default reset values. + * @param None + * @retval None + */ +void DMA_AESDeInit(void) +{ + DMA->AESCTL = DMA_AESCTL_RSTValue; + DMA->AESKEY[0] = DMA_AESKEY_RSTValue; + DMA->AESKEY[1] = DMA_AESKEY_RSTValue; + DMA->AESKEY[2] = DMA_AESKEY_RSTValue; + DMA->AESKEY[3] = DMA_AESKEY_RSTValue; + DMA->AESKEY[4] = DMA_AESKEY_RSTValue; + DMA->AESKEY[5] = DMA_AESKEY_RSTValue; + DMA->AESKEY[6] = DMA_AESKEY_RSTValue; + DMA->AESKEY[7] = DMA_AESKEY_RSTValue; +} + +/** + * @brief Initializes AES. + * @param InitStruct: AES configuration. + Mode: + DMA_AESMODE_128 + DMA_AESMODE_192 + DMA_AESMODE_256 + Direction: + DMA_AESDIRECTION_ENCODE + DMA_AESDIRECTION_DECODE + KeyStr: the pointer to DMA_AESKEYx register + * @retval None + */ +void DMA_AESInit(DMA_AESInitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_DMA_AESMOD(InitStruct->Mode)); + assert_parameters(IS_DMA_AESDIR(InitStruct->Direction)); + + tmp = DMA->AESCTL; + tmp &= ~(DMA_AESCTL_MODE\ + |DMA_AESCTL_ENC); + tmp |= (InitStruct->Mode\ + |InitStruct->Direction); + DMA->AESCTL = tmp; + DMA->AESKEY[0] = InitStruct->KeyStr[0]; + DMA->AESKEY[1] = InitStruct->KeyStr[1]; + DMA->AESKEY[2] = InitStruct->KeyStr[2]; + DMA->AESKEY[3] = InitStruct->KeyStr[3]; + + if ((InitStruct->Mode == DMA_AESMODE_192) ||\ + (InitStruct->Mode == DMA_AESMODE_256)) + { + DMA->AESKEY[4] = InitStruct->KeyStr[4]; + DMA->AESKEY[5] = InitStruct->KeyStr[5]; + } + if (InitStruct->Mode == DMA_AESMODE_256) + { + DMA->AESKEY[6] = InitStruct->KeyStr[6]; + DMA->AESKEY[7] = InitStruct->KeyStr[7]; + } +} + +/** + * @brief Enables or disables DMA interrupt. + * @param INTMask: can use the '|' operator + DMA_INT_C3DA + DMA_INT_C2DA + DMA_INT_C1DA + DMA_INT_C0DA + DMA_INT_C3FE + DMA_INT_C2FE + DMA_INT_C1FE + DMA_INT_C0FE + DMA_INT_C3PE + DMA_INT_C2PE + DMA_INT_C1PE + DMA_INT_C0PE + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + DMA->IE |= INTMask; + else + DMA->IE &= ~INTMask; +} + +/** + * @brief Gets DMA interrupt status. + * @param INTMask: + DMA_INTSTS_C3DA + DMA_INTSTS_C2DA + DMA_INTSTS_C1DA + DMA_INTSTS_C0DA + DMA_INTSTS_C3FE + DMA_INTSTS_C2FE + DMA_INTSTS_C1FE + DMA_INTSTS_C0FE + DMA_INTSTS_C3PE + DMA_INTSTS_C2PE + DMA_INTSTS_C1PE + DMA_INTSTS_C0PE + DMA_INTSTS_C3BUSY + DMA_INTSTS_C2BUSY + DMA_INTSTS_C1BUSY + DMA_INTSTS_C0BUSY + * @retval interrupt status. + */ +uint8_t DMA_GetINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INTFLAGR(INTMask)); + + if (DMA->STS&INTMask) + return 1; + else + return 0; +} + +/** + * @brief Clears DMA interrupt status. + * @param INTMask: can use the '|' operator + DMA_INTSTS_C3DA + DMA_INTSTS_C2DA + DMA_INTSTS_C1DA + DMA_INTSTS_C0DA + DMA_INTSTS_C3FE + DMA_INTSTS_C2FE + DMA_INTSTS_C1FE + DMA_INTSTS_C0FE + DMA_INTSTS_C3PE + DMA_INTSTS_C2PE + DMA_INTSTS_C1PE + DMA_INTSTS_C0PE + * @retval None + */ +void DMA_ClearINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INTFLAGC(INTMask)); + + DMA->STS = INTMask; +} + +/** + * @brief Enables or disables DMA channel. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_Cmd(uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &DMA->C0CTL + Channel*4; + + if (NewState == ENABLE) + *addr |= DMA_CCTL_EN; + else + *addr &= ~DMA_CCTL_EN; +} + +/** + * @brief Enables or disables AES encrypt/decrypt function of DMA channel3. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_AESCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + DMA->C3CTL |= DMA_CCTL_AESEN; + else + DMA->C3CTL &= ~DMA_CCTL_AESEN; +} + +/** + * @brief Stops DMA transmit. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_StopTransmit(uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &DMA->C0CTL + Channel*4; + + if (NewState == ENABLE) + *addr |= DMA_CCTL_STOP; + else + *addr &= ~DMA_CCTL_STOP; +} + +/** + * @brief Gets current frame transferred length. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval Current frame transferred length. + */ +uint8_t DMA_GetFrameLenTransferred(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + addr = &DMA->C0LEN + Channel*4; + return ((*addr&0xFF00)>>8); +} + +/** + * @brief Gets current package transferred length. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval Current package transferred length. + */ +uint8_t DMA_GetPackLenTransferred(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + addr = &DMA->C0LEN + Channel*4; + return (*addr&0xFF); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_flash.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_flash.c new file mode 100644 index 0000000000..fd6c74ba29 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_flash.c @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file lib_flash.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief FLASH library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_flash.h" +#include "lib_clk.h" + +/* FLASH Keys */ +#define FLASH_PASS_KEY 0x55AAAA55 +#define FLASH_SERASE_KEY 0xAA5555AA +#define FLASH_CERASE_KEY 0xAA5555AA +#define FLASH_DSTB_KEY 0xAA5555AA +#define FLASH_ICE_KEY 0xAA5555AA + +#define FLASH_MODE_MASK 0x1F3 + +/** + * @brief Initializes FLASH mode. + * @param CSMode: + FLASH_CSMODE_DISABLE + FLASH_CSMODE_ALWAYSON + FLASH_CSMODE_TMR2OV + FLASH_CSMODE_RTC + * @retval None + */ +void FLASH_Init(uint32_t CSMode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_CSMODE(CSMode)); + + tmp = FLASH->CTRL; + tmp &= ~FLASH_MODE_MASK; + tmp |= CSMode; + FLASH->CTRL = tmp; +} + +/** + * @brief Enables or disables FLASH interrupt. + * @param IntMask: + FLASH_INT_CS + NewState: + ENABLE + DISABLE + * @retval None + */ +void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = FLASH->CTRL; + tmp &= ~IntMask; + if (NewState == ENABLE) + { + tmp |= IntMask; + } + FLASH->CTRL = tmp; +} + +/** + * @brief Initializes FLASH 1USCYCLE. + * @param None + * @retval None + */ +void FLASH_CycleInit(void) +{ + uint32_t hclk; + + hclk = CLK_GetHCLKFreq(); + + if (hclk > 1000000) + MISC2->FLASHWC = (hclk/1000000)<FLASHWC = 0; +} + +/** + * @brief Erases a specified FLASH sector. + * @param Addr: The address of flash to be erased. The entire sector corresponding to the address will be erased. + * @retval None + */ +void FLASH_SectorErase(uint32_t Addr) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_ADDRESS(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + FLASH->SERASE = FLASH_SERASE_KEY; + while (FLASH->SERASE != 0); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Erases chip. + * @param None. + * @retval None + */ +void FLASH_ChipErase(void) +{ + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = 0; + FLASH->CERASE = FLASH_CERASE_KEY; + while (FLASH->CERASE != 0); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Programs n word at a specified start address. + * @param Addr: program start address + WordBuffer: The pointer of WordBuffer to be programmed + Length: The length of WordBuffer to be programmed + * @retval None + */ +void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADRRW(Addr)); + + FLASH->PGADDR = Addr; + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + for (i=0; iPGDATA = *(WordBuffer++); + while (FLASH->STS != 1); + } + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Programs n half-word at a specified start address. + * @param Addr: program start address + HWordBuffer: The pointer of HWordBuffer to be programmed + Length: The length of HWordBuffer to be programmed + * @retval None + */ +void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADRRHW(Addr)); + + FLASH->PGADDR = Addr; + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + for (i=0; iPGDATA)) = *(HWordBuffer++); + else + *((__IO uint16_t*)(&FLASH->PGDATA ) + 1) = *(HWordBuffer++); + while (FLASH->STS != 1); + } + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Programs n byte at a specified start address. + * @param Addr: program start address + ByteBuffer: The pointer of ByteBuffer to be programmed + Length: The length of ByteBuffer to be programmed + * @retval None + */ +void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADDRESS(Addr)); + + FLASH->PGADDR = Addr; + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + for (i=0; iPGDATA)) = *(ByteBuffer++); + else if (((Addr + i)&0x3) == 1) + *((__IO uint8_t*)(&FLASH->PGDATA) + 1) = *(ByteBuffer++); + else if (((Addr + i)&0x3) == 2) + *((__IO uint8_t*)(&FLASH->PGDATA) + 2) = *(ByteBuffer++); + else + *((__IO uint8_t*)(&FLASH->PGDATA) + 3) = *(ByteBuffer++); + while (FLASH->STS != 1); + } + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Enables FLASH read protection. + * @param Block: can use the '|' operator. + FLASH_BLOCK_0 ~ FLASH_BLOCK_31 or FLASH_BLOCK_ALL + * @retval None + */ +void FLASH_SetReadProtection(uint32_t Block) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_RWBLOCK(Block)); + + tmp = *(volatile unsigned int *)(0x0007FC00); + tmp &= ~Block; + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = 0x7FC00; + FLASH->PGDATA = tmp; + while (FLASH->STS != 1); + /* Lock flash */ + FLASH->PASS = 0; + + tmp = *(volatile unsigned int *)(0x0007FC00); +} + +/** + * @brief Enables or disables FLASH write protection. + * @param Block: can use the '|' operator. + FLASH_BLOCK_0 ~ FLASH_BLOCK_31 or FLASH_BLOCK_ALL + NewState: + ENABLE + DISABLE + * @retval None + */ +void FLASH_WriteProtection(uint32_t Block, uint32_t NewState) +{ + uint32_t wrprot; + + /* Check parameters */ + assert_parameters(IS_FLASH_RWBLOCK(Block)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + wrprot = FLASH->WRPROT; + + if (NewState == ENABLE) + { + wrprot |= Block; + } + else + { + wrprot &= ~Block; + } + FLASH->WRPROT = wrprot; +} + +/** + * @brief Enables or disables ICE protection. + * @param NewState: + ENABLE(ICE protection is successful when 0x7FC08 is 0x0A ) + DISABLE + * @retval None. + */ +void FLASH_ICEProtection(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = 0x7FC08; + FLASH->PGDATA = 0x0A; + while (FLASH->STS != 1); + /* Lock flash */ + FLASH->PASS = 0; + } + else + { + FLASH_SectorErase(0x7FFFF); + CORTEX_NVIC_SystemReset(); + } +} + +/** + * @brief Gets read/write/erase protection status. + * @param Block: + FLASH_BLOCK_0 ~ FLASH_BLOCK_31 + Operation: + FLASH_READ + FLASH_WRITE + * @retval + When Operation is FLASH_READ: + 1: Read protection enabled. + 0: Read protection disabled. + When Operation is FLASH_WRITE: + 1: Write/erase protection enabled. + 0: Write/erase protection disabled. + */ +uint8_t FLASH_GetProtectionStatus(uint32_t Block, uint32_t Operation) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_BLOCK(Block)); + assert_parameters(IS_FLASH_OPERATION(Operation)); + + if (Operation == FLASH_READ) + { + if (FLASH->RDPROT & Block) + return 1; + else + return 0; + } + else + { + if (FLASH->WRPROT & Block) + return 1; + else + return 0; + } +} + +/** + * @brief Gets read/write/erase protection status. + * @param Operation: + FLASH_READ + FLASH_WRITE + * @retval Read or write/erase protection status. + */ +uint32_t FLASH_GetAllProtectionStatus(uint32_t Operation) +{ + if (Operation == FLASH_READ) + { + return FLASH->RDPROT; + } + else + { + return FLASH->WRPROT; + } +} + +/** + * @brief Sets checksum range. + * @param AddrStart: checksum start address + AddrEnd: checksum end address + * @retval None + */ +void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_CHECKSUMADDR(AddrStart,AddrEnd)); + + FLASH->CSSADDR = AddrStart; + FLASH->CSEADDR = AddrEnd; +} + +/** + * @brief Sets checksum compare value. + * @param Checksum: checksum compare value + * @retval None + */ +void FLASH_SetCheckSumCompValue(uint32_t Checksum) +{ + FLASH->CSCVALUE = Checksum; +} + +/** + * @brief Gets FLASH checksum value. + * @param None + * @retval Checksum + */ +uint32_t FLASH_GetCheckSum(void) +{ + return FLASH->CSVALUE; +} + +/** + * @brief Gets FLASH interrupt status. + * @param IntMask: + FLASH_INT_CS + * @retval 1: interrupt status set + 0: interrupt status reset + */ +uint8_t FLASH_GetINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + + if (FLASH->INTSTS & FLASH_INTSTS_CSERR) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears FLASH interrupt status. + * @param IntMask: + FLASH_INT_CS + * @retval None + */ +void FLASH_ClearINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + + if (IntMask == FLASH_INT_CS) + { + FLASH->INTSTS = FLASH_INTSTS_CSERR; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_gpio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_gpio.c new file mode 100644 index 0000000000..cebe65effe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_gpio.c @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file lib_gpio.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief GPIO library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_gpio.h" + + +/** + * @brief Initializes GPIO. + * @param GPIOx: GPIOB~GPIOF + InitStruct:GPIO configuration. + GPIO_Pin: can use the '|' operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + GPIO_Mode: + GPIO_MODE_INPUT + GPIO_MODE_OUTPUT_CMOS + GPIO_MODE_OUTPUT_OD + GPIO_MODE_INOUT_OD + GPIO_MODE_INOUT_CMOS + GPIO_MODE_FORBIDDEN + * @retval None + */ +void GPIOBToF_Init(GPIO_Type *GPIOx, GPIO_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin)); + assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode)); + + /* Configure ATT */ + if (InitStruct->GPIO_Mode & 0x2U) + { + tmp_reg1 = GPIOx->ATT; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x1U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->ATT = tmp_reg1; + } + + /* Configure output/input mode */ + tmp_reg1 = GPIOx->OEN; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + tmp_reg2 = GPIOx->IE; + tmp_reg2 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x8U) + { + tmp_reg2 |= InitStruct->GPIO_Pin; + } + if (InitStruct->GPIO_Mode & 0x4U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->OEN = tmp_reg1; + GPIOx->IE = tmp_reg2; +} + +/** + * @brief Initializes GPIOA. + * @param GPIOx: GPIOA + InitStruct:GPIO configuration. + GPIO_Pin: can use the '|' operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + GPIO_Mode: + GPIO_MODE_INPUT + GPIO_MODE_OUTPUT_CMOS + GPIO_MODE_OUTPUT_OD + GPIO_MODE_INOUT_OD + GPIO_MODE_INOUT_CMOS + GPIO_MODE_FORBIDDEN + * @retval None + */ +void GPIOA_Init(GPIOA_Type *GPIOx, GPIO_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin)); + assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode)); + + /* Configure ATT */ + if (InitStruct->GPIO_Mode & 0x2U) + { + tmp_reg1 = GPIOx->ATT; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x1U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->ATT = tmp_reg1; + } + + /* Configure output/input mode */ + tmp_reg1 = GPIOx->OEN; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + tmp_reg2 = GPIOx->IE; + tmp_reg2 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x8U) + { + tmp_reg2 |= InitStruct->GPIO_Pin; + } + if (InitStruct->GPIO_Mode & 0x4U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->OEN = tmp_reg1; + GPIOx->IE = tmp_reg2; +} + +/** + * @brief Reads input data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15. + * @retval input pin value. + */ +uint8_t GPIOBToF_ReadInputDataBit(GPIO_Type *GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + if (GPIOx->STS & GPIO_Pin) + return 1; + else + return 0; +} + +/** + * @brief Reads input data register bit. + * @param GPIOx: GPIOA + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15. + * @retval input pin value. + */ +uint8_t GPIOA_ReadInputDataBit(GPIOA_Type *GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + if (GPIOx->STS & GPIO_Pin) + return 1; + else + return 0; +} + +/** + * @brief Reads input data register. + * @param GPIOx: GPIOB~GPIOF + * @retval input port value. + */ +uint16_t GPIOBToF_ReadInputData(GPIO_Type* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->STS; +} + +/** + * @brief Reads input data register. + * @param GPIOx: GPIOA + * @retval input port value. + */ +uint16_t GPIOA_ReadInputData(GPIOA_Type* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->STS; +} + +/** + * @brief Reads output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15 + * @retval output pin value. + */ +uint8_t GPIOBToF_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + if (GPIOx->DAT & GPIO_Pin) + return 1; + else + return 0; +} + +/** + * @brief Reads output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15 + * @retval output pin value. + */ +uint8_t GPIOA_ReadOutputDataBit(GPIOA_Type* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + if (GPIOx->DAT & GPIO_Pin) + return 1; + else + return 0; +} + +/** + * @brief Reads output data register. + * @param GPIOx: GPIOB~GPIOF + * @retval Output port value. + */ +uint16_t GPIOBToF_ReadOutputData(GPIO_Type* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->DAT; +} + +/** + * @brief Reads output data register. + * @param GPIOx: GPIOA + * @retval Output port value. + */ +uint16_t GPIOA_ReadOutputData(GPIOA_Type* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->DAT; +} + +/** + * @brief Writes output data register bit. + * @param DATx: GPIO_A~GPIO_F + PinNum: 0~15 + val:value write to register bit. + * @retval None. + */ +void GPIO_WriteBit(GPIO_DATInitType* DATx, uint8_t PinNum, uint8_t val) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_DAT(DATx)); + assert_parameters(IS_GPIO_PINNUM(PinNum)); + assert_parameters(IS_GPIO_BITVAL(val)); + + DATx->DATBitBand[PinNum] = val; +} + +/** + * @brief Writes output data register. + * @param GPIOx: GPIOB~GPIOF + val:value write to register. + * @retval None. + */ +void GPIOBToF_Write(GPIO_Type* GPIOx, uint16_t val) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + GPIOx->DAT = val; +} + +/** + * @brief Writes output data register. + * @param GPIOx: GPIOA + val:value write to register. + * @retval None. + */ +void GPIOA_Write(GPIOA_Type* GPIOx, uint16_t val) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + GPIOx->DAT = val; +} + +/** + * @brief Enables or disables GPIO AF functiuon. + * @param GPIOx:GPIOB GPIOE + GPIO_AFx: + GPIOB_AF_PLLHDIV + GPIOB_AF_PLLLOUT + GPIOB_AF_OSC + GPIOE_AF_CMP1O + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOBToF_AFConfig(GPIO_Type* GPIOx, uint32_t GPIO_AFx, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_GPIOAF_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_GPIOAF(GPIO_AFx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (GPIOx == GPIOB) + { + if (NewState == ENABLE) + { + GPIOAF->IOB_SEL |= GPIO_AFx; + } + else + { + GPIOAF->IOB_SEL &= ~GPIO_AFx; + } + } + if (GPIOx == GPIOE) + { + if (NewState == ENABLE) + { + GPIOAF->IOE_SEL |= GPIO_AFx; + } + else + { + GPIOAF->IOE_SEL &= ~GPIO_AFx; + } + } +} + +/** + * @brief Enables or disables GPIOA AF function. + * @param PMUIO_AFx:can use the '|' operator + PMUIO7_AF_PLLDIV + PMUIO6_AF_CMP2O + PMUIO3_AF_PLLDIV + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PMUIOAF(PMUIO_AFx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + GPIOA->SEL |= PMUIO_AFx; + } + else + { + GPIOA->SEL &= ~PMUIO_AFx; + } +} + +/** + * @brief Enables or disables GPIO pin remap function. + * @param GPIO_Remap: + GPIO_REMAP_I2C + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_REMAP(GPIO_Remap)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + GPIOAF->IO_MISC |= GPIO_Remap; + } + else + { + GPIOAF->IO_MISC &= ~GPIO_Remap; + } +} + +/** + * @brief Configures GPIO PLLDIV function. + * @param Divider: + GPIO_PLLDIV_1 + GPIO_PLLDIV_2 + GPIO_PLLDIV_4 + GPIO_PLLDIV_8 + GPIO_PLLDIV_16 + * @retval None. + */ +void GPIO_PLLDIVConfig(uint32_t Divider) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_PLLDIV(Divider)); + + tmp = GPIOAF->IO_MISC; + tmp &= ~GPIOAF_IO_MISC_PLLHDIV; + tmp |= Divider; + GPIOAF->IO_MISC = tmp; +} + +/** + * @brief Enables or disables GPIOA de-glitch circuit. + * @param GPIO_Pin: can use the '|' operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOA_DeGlitchCmd(uint16_t GPIO_Pin, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + /*IOA wake-up signal will go through de-glitch circuit.*/ + if (NewState == ENABLE) + { + GPIOA->IOANODEG &= ~GPIO_Pin; + } + /*IOA wake-up signal will not go through de-glitch circuit.*/ + else + { + GPIOA->IOANODEG |= GPIO_Pin; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_i2c.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_i2c.c new file mode 100644 index 0000000000..b4aa2f515b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_i2c.c @@ -0,0 +1,694 @@ +/** + ****************************************************************************** + * @file lib_i2c.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief IIC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_i2c.h" + +//registers default reset values +#define I2C_ADDR_RSTValue 0 +#define I2C_CTRL_RSTValue 0 +#define I2C_CTRL2_RSTValue 0 + +/* Private Functions -------------------------------------------------------- */ +static uint16_t I2C_CheckState(uint8_t State); +static void I2C_SendStart(void); +static void I2C_SendRestart(void); +static void I2C_SendByte(uint8_t dat); +static void I2C_SendStop(void); +static uint8_t I2C_ReceiveByte(void); +static void I2C_ClearBus(uint32_t remap); +static void I2C_WaitForCrossPage(uint8_t sla); + +/** + * @brief Checks required state. + * @param State: + Required state. + * @retval 0: state OK + !0: state Error, [15:8]Required status code, [7:0] real status code. + */ +static uint16_t I2C_CheckState(uint8_t State) +{ + uint16_t ret; + if (I2C_GetStatusCode() != State) + { + ret = (State<<8)|(I2C_GetStatusCode()); + return ret; + } + else + { + return 0; + } +} + +/** + * @brief Sends start signal. + * @param None + * @retval None + */ +static void I2C_SendStart(void) +{ + I2C_GenerateSTART(ENABLE); + while (I2C_GetINTStatus() == 0); + I2C_GenerateSTART(DISABLE); +} + +/** + * @brief Sends restart signal. + * @param None + * @retval None + */ +static void I2C_SendRestart(void) +{ + I2C_GenerateSTART(ENABLE); + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); + I2C_GenerateSTART(DISABLE); +} + +/** + * @brief Sends stop signal. + * @param None + * @retval None + */ +static void I2C_SendStop(void) +{ + I2C_GenerateSTOP(ENABLE); + I2C_ClearINTStatus(); + I2C_GenerateSTOP(DISABLE); +} + +/** + * @brief Sends data. + * @param dat:data to send. + * @retval None + */ +static void I2C_SendByte(uint8_t dat) +{ + I2C_SendData(dat); + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); +} + +/** + * @brief Receives byte. + * @param None + * @retval Byte received + */ +static uint8_t I2C_ReceiveByte(void) +{ + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); + return I2C_ReceiveData(); +} + +/** + * @brief Waits until cross page operation done. + * @param None + * @retval None + */ +static void I2C_WaitForCrossPage(uint8_t sla) +{ + do + { + I2C_SendRestart(); + I2C_SendByte(sla); //device address + }while (I2C_GetStatusCode() !=0x18); + I2C_SendStop(); //stop +} + +/** + * @brief Clears bus. + * @param None + * @retval None + */ +static void I2C_ClearBus(uint32_t remap) +{ + __IO uint8_t i, j; + + if (remap) // I2C remap enable, SCL IOC4 + { + GPIOC->DAT &= ~BIT4; + GPIOC->ATT |= BIT4; + GPIOC->OEN &= ~BIT4; + for (i=0; i<9; i++) + { + GPIOC->DAT |= BIT4; + for (j=0; j<100; j++) + __NOP(); + GPIOC->DAT &= ~BIT4; + for (j=0; j<100; j++) + __NOP(); + } + GPIOC->DAT |= BIT4; + GPIOC->OEN |= BIT4; + GPIOC->IE &= ~BIT4; + } + else // I2C remap disable, SCL IOB13 + { + GPIOB->DAT &= ~BIT13; + GPIOB->ATT |= BIT13; + GPIOB->OEN &= ~BIT13; + for (i=0; i<9; i++) + { + GPIOB->DAT |= BIT13; + for (j=0; j<100; j++) + __NOP(); + GPIOB->DAT &= ~BIT13; + for (j=0; j<100; j++) + __NOP(); + } + GPIOB->DAT |= BIT13; + GPIOB->OEN |= BIT13; + GPIOB->IE &= ~BIT13; + } +} + +/* Exported Functions ------------------------------------------------------- */ + +/** + * @brief Initializes the I2C peripheral registers to their default reset values. + * @param remap: I2C_REMAP_ENABLE or I2C_REMAP_DISABLE + * @retval None + */ +void I2C_DeInit(uint32_t remap) +{ + I2C->CTRL &= ~I2C_CTRL_EN; + + I2C->ADDR = I2C_ADDR_RSTValue; + I2C->CTRL = I2C_CTRL_RSTValue; + I2C->CTRL2 = I2C_CTRL2_RSTValue; + + I2C_ClearBus(remap); +} + +/** + * @brief Fills each InitStruct member with its default value. + * @param InitStruct: pointer to an I2C_InitType structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitType *InitStruct) +{ + /*--------------- Reset I2C init structure parameters values ---------------*/ + /* Initialize the AssertAcknowledge member */ + InitStruct->AssertAcknowledge = I2C_ASSERTACKNOWLEDGE_DISABLE; + /* Initialize the ClockSource member */ + InitStruct->ClockSource = I2C_CLOCKSOURCE_APBD256; + /* Initialize the GeneralCallAck member */ + InitStruct->GeneralCallAck = I2C_GENERALCALLACK_DISABLE; + /* Initialize the SlaveAddr member */ + InitStruct->SlaveAddr = 0; +} + +/** + * @brief Initializes I2C. + * @param InitStruct: I2C configuration. + SlaveAddr: Own I2C slave address (7 bit) + GeneralCallAck: + I2C_GENERALCALLACK_ENABLE + I2C_GENERALCALLACK_DISABLE + AssertAcknowledge: + I2C_ASSERTACKNOWLEDGE_ENABLE + I2C_ASSERTACKNOWLEDGE_DISABLE + ClockSource: + I2C_CLOCKSOURCE_APBD256 + I2C_CLOCKSOURCE_APBD224 + I2C_CLOCKSOURCE_APBD192 + I2C_CLOCKSOURCE_APBD160 + I2C_CLOCKSOURCE_APBD960 + I2C_CLOCKSOURCE_APBD120 + I2C_CLOCKSOURCE_APBD60 + I2C_CLOCKSOURCE_TIM3OFD8 + * @retval None. + */ +void I2C_Init(I2C_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_I2C_GC(InitStruct->GeneralCallAck)); + assert_parameters(IS_I2C_AA(InitStruct->AssertAcknowledge)); + assert_parameters(IS_I2C_CLKSRC(InitStruct->ClockSource)); + + I2C->ADDR = InitStruct->SlaveAddr\ + |InitStruct->GeneralCallAck; + tmp = I2C->CTRL; + tmp &= ~(I2C_CTRL_CR\ + |I2C_CTRL_AA); + tmp |= (InitStruct->ClockSource\ + |InitStruct->AssertAcknowledge); + I2C->CTRL = tmp; +} + +/** + * @brief Enables or disables I2C interrupt. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_INTConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL2 |= I2C_CTRL2_INTEN; + else + I2C->CTRL2 &= ~I2C_CTRL2_INTEN; +} + +/** + * @brief Gets I2C interrupt status. + * @param None + * @retval Interrupt status. + */ +uint8_t I2C_GetINTStatus(void) +{ + if (I2C->CTRL&I2C_CTRL_SI) + return 1; + else + return 0; +} + +/** + * @brief Clears I2C interrupt status. + * @param None + * @retval None. + */ +void I2C_ClearINTStatus(void) +{ + I2C->CTRL &= ~I2C_CTRL_SI; +} + +/** + * @brief Reads a packge of data from slave device. + * @param InitStruct: I2C_WRType + SlaveAddr : Slave device address + SubAddress : start of slave device sub-address + PageRange : maximum range of page to Read operation + pBuffer : Read data pointer + Length : sum of Read datas + SubAddrType: + I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte) + I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes) + I2C_SUBADDR_OTHER (Slave device sub-address type: othres) + * @retval 0: true + £¡0: status code + bit15~8 status code(true) + bit7~0 status code(false) + */ +uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct) +{ + uint32_t i; + uint16_t ret_val; + + /* Check parameters */ + assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType)); + + I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA + /*-------------------------------- START -----------------------------------*/ + I2C_SendStart(); + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + + /*------------------------------ Send SLA+W --------------------------------*/ + /* Slave device sub-address type: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: 2 bytes */ + if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: othres */ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + /*------------------------------- Restart ----------------------------------*/ + I2C_SendRestart(); //restart + ret_val = I2C_CheckState(0x10); + if (ret_val) return ret_val; + + /*----------------------------- Send SLA+R ---------------------------------*/ + /* Slave device sub-address type: othres */ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>7)&0xE)); + else // 16 + x + I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>15)&0xE)); + } + else + I2C_SendByte(InitStruct->SlaveAddr|0x01); + + ret_val = I2C_CheckState(0x40); + if (ret_val) return ret_val; + + /*----------------------------- Read datas ---------------------------------*/ + for (i=0; i<(InitStruct->Length-1); i++) + { + *InitStruct->pBuffer = I2C_ReceiveByte(); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x50); + if (ret_val) return ret_val; + } + /*-------------------- Read the last data, disable AA ----------------------*/ + I2C_AssertAcknowledgeConfig(DISABLE); + *InitStruct->pBuffer = I2C_ReceiveByte(); + ret_val = I2C_CheckState(0x58); + if (ret_val) return ret_val; + /*--------------------------------- Stop -----------------------------------*/ + I2C_SendStop(); //stop + return 0; +} + +/** + * @brief Writes a packge of data to slave device. + * @param InitStruct: I2C_WRType + SlaveAddr : Slave device address + SubAddress : start of slave device sub-address + PageRange : maximum range of page to write operation + pBuffer : write data pointer + Length : sum of write datas + SubAddrType: + I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte) + I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes) + I2C_SUBADDR_OTHER (Slave device sub-address type: othres) + * @retval 0: true + £¡0: status code + bit15~8 status code(true) + bit7~0 status code(false) + */ +uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct) +{ + uint16_t ret_val; + uint32_t i; + + /* Check parameters */ + assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType)); + + I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA + /*-------------------------------- START -----------------------------------*/ + I2C_SendStart(); + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + + /*------------------------------ Send SLA+W --------------------------------*/ + /* Slave device sub-address type: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: 2 bytes */ + else if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); //device address + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); //first word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); //second word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: othres */ + else + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + /*----------------------------- Write datas --------------------------------*/ + for (i=0; i<(InitStruct->Length); i++) + { + /* Reach the page boundary */ + if ((i > 0) && ((InitStruct->SubAddress+i)%InitStruct->PageRange == 0)) + { + I2C_SendStop(); + I2C_WaitForCrossPage(InitStruct->SlaveAddr); + I2C_SendStart(); //start + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + /* WriteAddr: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* WriteAddr: 2 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); //device address + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); //first word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); //second word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* WriteAddr: (16 or 8)+x*/ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + I2C_SendByte(*InitStruct->pBuffer); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Not reaching the page boundary */ + else + { + I2C_SendByte(*InitStruct->pBuffer); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + I2C_SendStop(); + I2C_WaitForCrossPage(InitStruct->SlaveAddr); + return 0; +} + +/** + * @brief Enables or disables I2C. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_EN; + else + I2C->CTRL &= ~I2C_CTRL_EN; +} + +/* I2C Exported Functions Group5: + Others ------------------------------------*/ + +/** + * @brief Configures assert acknowledge. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_AssertAcknowledgeConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_AA; + else + I2C->CTRL &= ~I2C_CTRL_AA; +} + +/** + * @brief Receives a byte data. + * @param None. + * @retval Data received. + */ +uint8_t I2C_ReceiveData(void) +{ + return I2C->DATA; +} + +/** + * @brief Sends a byte data. + * @param Dat:data to transmit. + * @retval None + */ +void I2C_SendData(uint8_t Dat) +{ + I2C->DATA = Dat; +} + +/** + * @brief Generates start signal. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_GenerateSTART(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_STA; + else + I2C->CTRL &= ~I2C_CTRL_STA; +} + +/** + * @brief Generates stop signal. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_GenerateSTOP(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_STO; + else + I2C->CTRL &= ~I2C_CTRL_STO; +} + +/** + * @brief Gets status code. + * @param None + * @retval status code. + */ +uint8_t I2C_GetStatusCode(void) +{ + return (I2C->STS&I2C_STS_STS); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_iso7816.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_iso7816.c new file mode 100644 index 0000000000..83077dc8d6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_iso7816.c @@ -0,0 +1,405 @@ +/** + ****************************************************************************** + * @file lib_iso7816.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief ISO7816 library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_iso7816.h" +#include "lib_clk.h" + +//registers default reset values +#define ISO7816_BAUDDIVL_RSTValue (0UL) +#define ISO7816_BAUDDIVH_RSTValue (0UL) +#define ISO7816_CFG_RSTValue (0x400) +#define ISO7816_CLK_RSTValue (0UL) +#define ISO7816_INFO_RC_MASK (0x3ECUL) + + +/** + * @brief Initializes the ISO7816 peripheral registers to their default reset values. + * @param ISO7816x: ISO78160~ISO78161 + * @retval None + */ +void ISO7816_DeInit(ISO7816_Type *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + ISO7816x->CFG &= ~ISO7816_CFG_EN; + + ISO7816x->INFO = ISO7816_INFO_RC_MASK; /* clear interrupt flag */ + ISO7816x->BAUDDIVH = ISO7816_BAUDDIVH_RSTValue; + ISO7816x->BAUDDIVL = ISO7816_BAUDDIVL_RSTValue; + ISO7816x->CFG = ISO7816_CFG_RSTValue; + ISO7816x->CLK = ISO7816_CLK_RSTValue; +} + + +/** + * @brief Fills each InitStruct member with its default value. + * @param InitStruct: pointer to an ISO7816_InitType structure which will be initialized. + * @retval None + */ +void ISO7816_StructInit(ISO7816_InitType *InitStruct) +{ + /*--------------- Reset ISO7816 init structure parameters values ---------------*/ + /* Initialize the FirstBit member */ + InitStruct->FirstBit = ISO7816_FIRSTBIT_MSB; + /* Initialize the Parity member */ + InitStruct->Parity = ISO7816_PARITY_EVEN; + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the TXRetry member */ + InitStruct->TXRetry = ISO7816_TXRTY_0; + /* Initialize the RXACKLength member */ + InitStruct->RXACKLength = ISO7816_RXACKLEN_2; + /* Initialize the TXNACKLength member */ + InitStruct->TXNACKLength = ISO7816_TXNACKLEN_0; +} + +/** + * @brief Initializes ISO7816. + * @param ISO7816x: ISO78160~ISO78161 + Init_Struct:iso7816 configuration. + FirstBit: + ISO7816_FIRSTBIT_MSB + ISO7816_FIRSTBIT_LSB + Parity: + ISO7816_PARITY_EVEN + ISO7816_PARITY_ODD + Baudrate: baudrate value to configure, 200UL ~ 2625000UL + TXRetry: + ISO7816_TXRTY_0 ~ ISO7816_TXRTY_15 + RXACKLength: + ISO7816_RXACKLEN_2 + ISO7816_RXACKLEN_1 + TXNACKLength: + ISO7816_TXNACKLEN_0 + ISO7816_TXNACKLEN_1 + ISO7816_TXNACKLEN_2 + * @retval None + */ +void ISO7816_Init(ISO7816_Type *ISO7816x, ISO7816_InitType *Init_Struct) +{ + uint32_t tmp; + uint16_t div; + uint32_t pclk; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FIRSTBIT(Init_Struct->FirstBit)); + assert_parameters(IS_ISO7816_PARITY(Init_Struct->Parity)); + assert_parameters(IS_ISO7816_BAUDRATE(Init_Struct->Baudrate)); + assert_parameters(IS_ISO7816_TXRTY(Init_Struct->TXRetry)); + assert_parameters(IS_ISO7816_RXACKLEN(Init_Struct->RXACKLength)); + assert_parameters(IS_ISO7816_TXNACKLEN(Init_Struct->TXNACKLength)); + + tmp = ISO7816x->CFG; + tmp &= ~(ISO7816_CFG_ACKLEN\ + |ISO7816_CFG_AUTORXACK\ + |ISO7816_CFG_LSB\ + |ISO7816_CFG_CHKP\ + |ISO7816_CFG_RXACKSET\ + |ISO7816_CFG_TXRTYCNT); + tmp |= (Init_Struct->FirstBit\ + |Init_Struct->Parity\ + |Init_Struct->TXRetry\ + |Init_Struct->RXACKLength\ + |Init_Struct->TXNACKLength); + ISO7816x->CFG = tmp; + + pclk = CLK_GetPCLKFreq(); + div = 0x10000 - (pclk/Init_Struct->Baudrate); + ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH_BAUDDIVH; + ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL_BAUDDIVL; +} + +/** + * @brief Enables or disables ISO7816. + * @param ISO7816x: ISO78160~ISO78161 + NewState: + ENABLE + DISABLE + * @retval None. + */ +void ISO7816_Cmd(ISO7816_Type *ISO7816x, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + ISO7816x->CFG |= ISO7816_CFG_EN; + } + else + { + ISO7816x->CFG &= ~ISO7816_CFG_EN; + } +} + +/** + * @brief Configures ISO7816 baudrate. + * @param ISO7816x: ISO78160~ISO78161 + BaudRate:Baud rate value + * @retval None + */ +void ISO7816_BaudrateConfig(ISO7816_Type *ISO7816x, uint32_t BaudRate) +{ + uint32_t pclk; + uint16_t div; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_BAUDRATE(BaudRate)); + + pclk = CLK_GetPCLKFreq(); + div = 0x10000 - (pclk/BaudRate); + ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH_BAUDDIVH; + ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL_BAUDDIVL; +} + +/** + * @brief Configures ISO7816 clock divider. + * @param ISO7816x: ISO78160~ISO78161 + Prescaler:1~128 + * @retval None + */ +void ISO7816_CLKDIVConfig(ISO7816_Type *ISO7816x, uint32_t Prescaler) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_PRESCALER(Prescaler)); + + tmp = ISO7816x->CLK; + tmp &= ~ISO7816_CLK_CLKDIV; + tmp |= ((Prescaler - 1)&ISO7816_CLK_CLKDIV); + ISO7816x->CLK = tmp; +} + +/** + * @brief Enables or disables ISO7816 clock output function. + * @param ISO7816x: ISO78160~ISO78161 + NewState: + ENABLE + DISABLE + * @retval None + */ +void ISO7816_CLKOutputCmd(ISO7816_Type *ISO7816x, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + ISO7816x->CLK |= ISO7816_CLK_CLKEN; + } + else + { + ISO7816x->CLK &= ~ISO7816_CLK_CLKEN; + } +} + +/** + * @brief Reads ISO7816 data. + * @param ISO7816: ISO78160~ISO78161 + * @retval The received data. + */ +uint8_t ISO7816_ReceiveData(ISO7816_Type *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + return ISO7816x->DATA; +} + +/** + * @brief Writes ISO7816 data. + * @param ISO7816x: ISO78160~ISO78161 + * ch: data to send + * @retval None + */ +void ISO7816_SendData(ISO7816_Type *ISO7816x, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + ISO7816x->DATA = ch; +} + +/** + * @brief ENables or disables ISO7816 interrupt. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + This parameter can be any combination of the following values + ISO7816_INT_TXRTYERR + ISO7816_INT_RXOV + ISO7816_INT_RX + ISO7816_INT_TXDONE + ISO7816_INT_RXERR + NewState: + ENABLE + DISABLE + * @retval None + */ +void ISO7816_INTConfig(ISO7816_Type *ISO7816x, uint32_t INTMask, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + ISO7816x->CFG |= INTMask; + } + else + { + ISO7816x->CFG &= ~INTMask; + } +} + +/** + * @brief Gets ISO7816 interrupt state. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + ISO7816_INTSTS_TXRTYERR + ISO7816_INTSTS_TXDONE + ISO7816_INTSTS_RXOV + ISO7816_INTSTS_RX + ISO7816_INTSTS_RXERR + * @retval 1: state set + 0: state reset + */ +uint8_t ISO7816_GetINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INTFLAGR(INTMask)); + + if (ISO7816x->INFO & INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears ISO7816 interrupt state. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + This parameter can be any combination of the following values + ISO7816_INTSTS_TXRTYERR + ISO7816_INTSTS_TXDONE + ISO7816_INTSTS_RXOV + ISO7816_INTSTS_RX + ISO7816_INTSTS_RXERR + * @retval None + */ +void ISO7816_ClearINTStatus(ISO7816_Type *ISO7816x, uint32_t INTMask) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INTFLAGC(INTMask)); + + tmp = ISO7816x->INFO; + tmp &= ~ISO7816_INFO_RC_MASK; + tmp |= INTMask; + ISO7816x->INFO = tmp; +} + +/** + * @brief Gets ISO7816 peripheral flag. + * @param ISO7816x: ISO78160~ISO78161 + FlagMask: + ISO7816_FLAG_DMATXDONE + * @retval 1: state set + 0: state reset + */ +uint8_t ISO7816_GetFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FLAGR(FlagMask)); + + if (ISO7816x->INFO & FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears ISO7816 peripheral flag. + * @param ISO7816x: ISO78160~ISO78161 + FlagMask: + ISO7816_FLAG_DMATXDONE + * @retval None + */ +void ISO7816_ClearFlag(ISO7816_Type *ISO7816x, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FLAGC(FlagMask)); + + ISO7816x->INFO |= FlagMask; +} + +/** + * @brief Gets last transmited ACK. + * @param ISO7816: ISO78160~ISO78161 + * @retval ACK value + */ +uint8_t ISO7816_GetLastTransmitACK(ISO7816_Type *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + if (ISO7816x->INFO&ISO7816_INFO_RXACK) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Gets last received check sum bit. + * @param ISO7816: ISO78160~ISO78161 + * @retval CHKSUM bit value + */ +uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_Type *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + if (ISO7816x->INFO&ISO7816_INFO_CHKSUM) + { + return 1; + } + else + { + return 0; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_lcd.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_lcd.c new file mode 100644 index 0000000000..ad16d7ce7e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_lcd.c @@ -0,0 +1,255 @@ +/** + ****************************************************************************** + * @file lib_lcd.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief LCD library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_lcd.h" +#include "lib_LoadNVR.h" + +//registers default reset values +#define LCD_CTRL_RSTValue 0 +#define LCD_CTRL2_RSTValue 0 +#define LCD_SEGCTRL0_RSTValue 0 +#define LCD_SEGCTRL1_RSTValue 0 +#define LCD_SEGCTRL2_RSTValue 0 + +/* COMx IO */ +const LCD_COMIO lcd_comio[] = +{ + {&GPIOD->OEN, GPIO_Pin_0}, + {&GPIOD->OEN, GPIO_Pin_1}, + {&GPIOD->OEN, GPIO_Pin_2}, + {&GPIOD->OEN, GPIO_Pin_3}, + {&GPIOD->OEN, GPIO_Pin_4}, + {&GPIOD->OEN, GPIO_Pin_5}, + {&GPIOD->OEN, GPIO_Pin_6}, + {&GPIOD->OEN, GPIO_Pin_7}, +}; + +/** + * @brief Initializes LCD. + * @param InitStruct: LCD configuration. + Type: + LCD_TYPE_4COM + LCD_TYPE_6COM + LCD_TYPE_8COM + Drv: + LCD_DRV_300 + LCD_DRV_600 + LCD_DRV_150 + LCD_DRV_200 + FRQ: + LCD_FRQ_64H + LCD_FRQ_128H + LCD_FRQ_256H + LCD_FRQ_512H + SWPR: Frame buffer switch period(0.5 sec * (SWPR + 1)). + FBMODE: + LCD_FBMODE_BUFA + LCD_FBMODE_BUFAB + LCD_FBMODE_BUFABLANK + BKFILL: + LCD_BKFILL_1 + LCD_BKFILL_0 + * @retval None + */ +void LCD_Init(LCD_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_LCD_TYPE(InitStruct->Type)); + assert_parameters(IS_LCD_DRV(InitStruct->Drv)); + assert_parameters(IS_LCD_FRQ(InitStruct->FRQ)); + assert_parameters(IS_LCD_SWPR(InitStruct->SWPR)); + assert_parameters(IS_LCD_FBMODE(InitStruct->FBMODE)); + assert_parameters(IS_LCD_BKFILL(InitStruct->BKFILL)); + + tmp_reg1 = LCD->CTRL; + tmp_reg2 = LCD->CTRL2; + tmp_reg1 &= ~(LCD_CTRL_TYPE\ + |LCD_CTRL_DRV\ + |LCD_CTRL_FRQ); + tmp_reg1 |= (InitStruct->Type\ + |InitStruct->Drv\ + |InitStruct->FRQ); + tmp_reg2 &= ~(LCD_CTRL2_SWPR\ + |LCD_CTRL2_FBMODE\ + |LCD_CTRL2_BKFILL); + tmp_reg2 |= ((InitStruct->SWPR << 8)\ + |InitStruct->FBMODE\ + |InitStruct->BKFILL); + LCD->CTRL = tmp_reg1; + LCD->CTRL2 = tmp_reg2; +} + +/** + * @brief Fills each LCD_InitStruct member with its default value. + * @param LCD_InitStruct: pointer to an LCD_InitType structure which will be initialized. + * @retval None + */ +void LCD_StructInit(LCD_InitType *LCD_InitStruct) +{ + /*--------------- Reset LCD init structure parameters values ---------------*/ + /* Initialize the BKFILL member */ + LCD_InitStruct->BKFILL = LCD_BKFILL_0; + /* Initialize the Drv member */ + LCD_InitStruct->Drv = LCD_DRV_300; + /* Initialize the FBMODE member */ + LCD_InitStruct->FBMODE = LCD_FBMODE_BUFA; + /* Initialize the FRQ member */ + LCD_InitStruct->FRQ = LCD_FRQ_64H; + /* Initialize the SWPR member */ + LCD_InitStruct->SWPR = 0; + /* Initialize the Type member */ + LCD_InitStruct->Type = LCD_TYPE_4COM; +} + +/** + * @brief Initializes the LCD registers to their default reset values. + * @param None + * @retval None + */ +void LCD_DeInit(void) +{ + LCD->CTRL &= ~LCD_CTRL_EN; + + LCD->CTRL = LCD_CTRL_RSTValue; + LCD->CTRL2 = LCD_CTRL2_RSTValue; + LCD->SEGCTRL0 = LCD_SEGCTRL0_RSTValue; + LCD->SEGCTRL1 = LCD_SEGCTRL1_RSTValue; + LCD->SEGCTRL2 = LCD_SEGCTRL2_RSTValue; +} + +/** + * @brief Enables or disables LCD controller. + * @param IOInitType: LCD SEG and COM configuration. + SegCtrl0: + SegCtrl1: + 0~0xFFFFFFFF + SegCtrl2: + 0~0xFFFF + COMMode: + LCD_TYPE_4COM + LCD_TYPE_6COM + LCD_TYPE_8COM + NewState: + ENABLE + DISABLE + * @retval None + */ +void LCD_Cmd(LCD_IOInitType *IOInitType, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_LCD_TYPE(IOInitType->COMMode)); + + LCD->CTRL &= ~LCD_CTRL_TYPE; + LCD->CTRL |= IOInitType->COMMode; + + if (NewState == ENABLE) + { + /* Rising edge of LCD_CTRL_EN */ + LCD->CTRL &= ~LCD_CTRL_EN; + LCD->SEGCTRL0 = IOInitType->SegCtrl0; + LCD->SEGCTRL1 = IOInitType->SegCtrl1; + LCD->SEGCTRL2 = IOInitType->SegCtrl2; + + /* COMs' IO configuration : forbidden */ + *lcd_comio[0].GPIO |= lcd_comio[0].Pin; + *(lcd_comio[0].GPIO+1) &= ~lcd_comio[0].Pin; + *lcd_comio[1].GPIO |= lcd_comio[1].Pin; + *(lcd_comio[1].GPIO+1) &= ~lcd_comio[1].Pin; + *lcd_comio[2].GPIO |= lcd_comio[2].Pin; + *(lcd_comio[2].GPIO+1) &= ~lcd_comio[2].Pin; + *lcd_comio[3].GPIO |= lcd_comio[3].Pin; + *(lcd_comio[3].GPIO+1) &= ~lcd_comio[3].Pin; + if (IOInitType->COMMode == LCD_TYPE_6COM) + { + *lcd_comio[4].GPIO |= lcd_comio[4].Pin; + *(lcd_comio[4].GPIO+1) &= ~lcd_comio[4].Pin; + *lcd_comio[5].GPIO |= lcd_comio[5].Pin; + *(lcd_comio[5].GPIO+1) &= ~lcd_comio[5].Pin; + } + else if (IOInitType->COMMode == LCD_TYPE_8COM) + { + *lcd_comio[4].GPIO |= lcd_comio[4].Pin; + *(lcd_comio[4].GPIO+1) &= ~lcd_comio[4].Pin; + *lcd_comio[5].GPIO |= lcd_comio[5].Pin; + *(lcd_comio[5].GPIO+1) &= ~lcd_comio[5].Pin; + *lcd_comio[6].GPIO |= lcd_comio[6].Pin; + *(lcd_comio[6].GPIO+1) &= ~lcd_comio[6].Pin; + *lcd_comio[7].GPIO |= lcd_comio[7].Pin; + *(lcd_comio[7].GPIO+1) &= ~lcd_comio[7].Pin; + } + else + { + } + + /* Enable LCD */ + LCD->CTRL |= LCD_CTRL_EN; + } + else + { + /* Falling edge of LCD_CTRL_EN */ + LCD->CTRL |= LCD_CTRL_EN; + /* Disable LCD */ + LCD->CTRL &= ~LCD_CTRL_EN; + + LCD->SEGCTRL0 = IOInitType->SegCtrl0; + LCD->SEGCTRL1 = IOInitType->SegCtrl1; + LCD->SEGCTRL2 = IOInitType->SegCtrl2; + + /* COMs' IO configuration : ouput low */ + *(lcd_comio[0].GPIO+2) &= ~lcd_comio[0].Pin; + *lcd_comio[0].GPIO &= ~lcd_comio[0].Pin; + *(lcd_comio[1].GPIO+2) &= ~lcd_comio[1].Pin; + *lcd_comio[1].GPIO &= ~lcd_comio[1].Pin; + *(lcd_comio[2].GPIO+2) &= ~lcd_comio[2].Pin; + *lcd_comio[2].GPIO &= ~lcd_comio[2].Pin; + *(lcd_comio[3].GPIO+2) &= ~lcd_comio[3].Pin; + *lcd_comio[3].GPIO &= ~lcd_comio[3].Pin; + if (IOInitType->COMMode & 2UL) + { + *(lcd_comio[4].GPIO+2) &= ~lcd_comio[4].Pin; + *lcd_comio[4].GPIO &= ~lcd_comio[4].Pin; + *(lcd_comio[5].GPIO+2) &= ~lcd_comio[5].Pin; + *lcd_comio[5].GPIO &= ~lcd_comio[5].Pin; + } + if (IOInitType->COMMode & 4UL) + { + *(lcd_comio[6].GPIO+2) &= ~lcd_comio[6].Pin; + *lcd_comio[6].GPIO &= ~lcd_comio[6].Pin; + *(lcd_comio[7].GPIO+2) &= ~lcd_comio[7].Pin; + *lcd_comio[7].GPIO &= ~lcd_comio[7].Pin; + } + } +} + +/** + * @brief Configures LCD BIAS mode. + * @param BiasSelection: + LCD_BMODE_DIV3 + LCD_BMODE_DIV4 + * @retval None + */ +void LCD_BiasModeConfig(uint32_t BiasSelection) +{ + uint32_t tmp; + + assert_parameters(IS_LCD_BMODE(BiasSelection)); + + tmp = ANA->REG6; + tmp &= ~ANA_REG6_LCDBMODE; + tmp |= BiasSelection; + ANA->REG6 = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_misc.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_misc.c new file mode 100644 index 0000000000..44d29fc26b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_misc.c @@ -0,0 +1,255 @@ +/** + ****************************************************************************** + * @file lib_misc.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief MISC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_misc.h" + +/** + * @brief Gets MISC flag status. + * @param FlagMask: + MISC_FLAG_LOCKUP + MISC_FLAG_PIAC + MISC_FLAG_HIAC + MISC_FLAG_PERR + * @retval Flag status. + */ +uint8_t MISC_GetFlag(uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_MISC_FLAGR(FlagMask)); + + if (MISC1->SRAMINT&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears MISC flag status. + * @param FlagMask: can use the '|' operator + MISC_FLAG_LOCKUP + MISC_FLAG_PIAC + MISC_FLAG_HIAC + MISC_FLAG_PERR + * @retval None + */ +void MISC_ClearFlag(uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_MISC_FLAGC(FlagMask)); + + MISC1->SRAMINT = FlagMask; +} + +/** + * @brief Enables or disables MISC interrupt. + * @param INTMask: can use the '|' operator + MISC_INT_LOCK + MISC_INT_PIAC + MISC_INT_HIAC + MISC_INT_PERR + NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_MISC_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = MISC1->SRAMINIT; + if (NewState == ENABLE) + { + tmp |= INTMask; + } + else + { + tmp &= ~INTMask; + } + MISC1->SRAMINIT = tmp; +} + +/** + * @brief Enables or disables SRAM parity. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_SRAMParityCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC1->SRAMINIT |= MISC1_SRAMINIT_PEN; + } + else + { + MISC1->SRAMINIT &= ~MISC1_SRAMINIT_PEN; + } +} + +/** + * @brief Gets SRAM parity error address. + * @param None + * @retval parity error address. + */ +uint32_t MISC_GetSRAMPEAddr(void) +{ + uint32_t tmp; + + tmp = MISC1->PARERR; + tmp = tmp*4 + 0x20000000; + return tmp; +} + +/** + * @brief Gets APB error address. + * @param None + * @retval APB error address. + */ +uint32_t MISC_GetAPBErrAddr(void) +{ + uint32_t tmp; + + tmp = MISC1->PIADDR; + tmp = tmp + 0x40000000; + return tmp; +} + +/** + * @brief Gets AHB error address. + * @param None + * @retval AHB error address. + */ +uint32_t MISC_GetAHBErrAddr(void) +{ + return (MISC1->HIADDR); +} + +/** + * @brief Enables or disables UART transmit IR function. + * @param IRx: + MISC_IREN_TX0 + MISC_IREN_TX1 + MISC_IREN_TX2 + MISC_IREN_TX3 + MISC_IREN_TX4 + MISC_IREN_TX5 + NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_IRCmd(uint32_t IRx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_MISC_IREN(IRx)); + + tmp = MISC1->IREN; + if (NewState == ENABLE) + { + tmp |= IRx; + } + else + { + tmp &= ~IRx; + } + MISC1->IREN = tmp; +} + +/** + * @brief Configures SUART transmit IR duty. + * @param DutyHigh + The high pulse width will be (DUTYH + 1)*APBCLK period. + DutyLow + The low pulse width will be (DUTYL + 1)*APBCLK period. + * @retval None + */ +void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow) +{ + MISC1->DUTYH = DutyHigh; + MISC1->DUTYL = DutyLow; +} + +/** + * @brief Enables or disables Hardfault generation. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_HardFaultCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC1->IRQLAT &= ~MISC1_IRQLAT_NOHARDFAULT; + } + else + { + MISC1->IRQLAT |= MISC1_IRQLAT_NOHARDFAULT; + } +} + +/** + * @brief Enables or disables a system reset when the CM0 lockup happened. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_LockResetCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC1->IRQLAT |= MISC1_IRQLAT_LOCKRESET; + } + else + { + MISC1->IRQLAT &= ~MISC1_IRQLAT_LOCKRESET; + } +} + +/** + * @brief Configures IRQ latency. + * @param Latency:0~255 + * @retval None + */ +void MISC_IRQLATConfig(uint8_t Latency) +{ + uint32_t tmp; + + tmp = MISC1->IRQLAT; + tmp &= ~MISC1_IRQLAT_IRQLAT; + tmp |= Latency; + MISC1->IRQLAT = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_pmu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_pmu.c new file mode 100644 index 0000000000..0f766a41c5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_pmu.c @@ -0,0 +1,1214 @@ +/** + ****************************************************************************** + * @file lib_pmu.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief PMU library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_pmu.h" +#include "lib_gpio.h" +#include "lib_CodeRAM.h" +#include "lib_clk.h" +#include "lib_cortex.h" + +#define DSLEEPPASS_KEY 0xAA5555AA +#define DSLEEPEN_KEY 0x55AAAA55 + +/** + * @brief Enters deep-sleep mode. + * @param None + * @retval 1: Current mode is debug mode, function failed. + * 2: Enter deep-sleep mode failed. + */ +uint32_t PMU_EnterDSleepMode(void) +{ + uint32_t hclk; + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Enter deep sleep when WKU event is cleared */ + while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU) + { + } + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + PMU->DSLEEPPASS = DSLEEPPASS_KEY; + PMU->DSLEEPEN = DSLEEPEN_KEY; + + return 2; +} + +/** + * @brief Enters idle mode. + * @note Any interrupt generates to CPU will break idle mode. + * @param None + * @retval None + */ +void PMU_EnterIdleMode(void) +{ + /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + __WFI(); +} + +/** + * @brief Enters sleep mode. + * @param None + * @retval 1: Current mode is debug mode, function failed. + * 0: Quit sleep mode succeeded. + */ +uint32_t PMU_EnterSleepMode(void) +{ + uint32_t hclk; + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + __WFI(); + + return 0; +} + +/** + * @brief Enables or disables PMU interrupt. + * @param INTMask: can use the | operator + PMU_INT_IOAEN + PMU_INT_32K + PMU_INT_6M + NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + PMU->CONTROL |= INTMask; + } + else + { + PMU->CONTROL &= ~INTMask; + } +} + +/** + * @brief Gets PMU interrupt status. + * @param INTMask: + PMU_INTSTS_32K + PMU_INTSTS_6M + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INTFLAGR(INTMask)); + + if (PMU->STS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears PMU interrupt status. + * @param INTMask:specifies the flag to clear. + This parameter can be any combination of the following values + PMU_INTSTS_32K + PMU_INTSTS_6M + * @retval None + */ +void PMU_ClearINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INTFLAGC(INTMask)); + + PMU->STS = INTMask; +} + +/** + * @brief Gets Crystal status. + * @param Mask: + PMU_STS_32K + PMU_STS_6M + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetCrystalStatus(uint32_t Mask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_FLAG(Mask)); + + if (PMU->STS&Mask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Gest all IOA interrupt status. + * @param None + * @retval IOA's interrupt status + */ +uint16_t PMU_GetIOAAllINTStatus(void) +{ + return (GPIOA->IOAINTSTS); +} + +/** + * @brief Gest IOA interrupt status. + * @param INTMask: + GPIO_Pin_0 ~ GPIO_Pin_15 + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetIOAINTStatus(uint16_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(INTMask)); + + if (GPIOA->IOAINTSTS & INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears IOA interrupt status. + * @param INTMask: + This parameter can be any combination of the following values + GPIO_Pin_0 ~ GPIO_Pin_15 + * @retval None + */ +void PMU_ClearIOAINTStatus(uint16_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PIN(INTMask)); + + GPIOA->IOAINTSTS = INTMask; +} + +/** + * @brief Configures Wake-up pin functions. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + * @retval None + */ +void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event) +{ + uint32_t tmp; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + while ((IOAx >> position) != 0U) + { + /* Get current io position */ + iocurrent = IOAx & (0x01U << position); + + if (iocurrent) + { + /* Current IO Input configure*/ + GPIOA->OEN |= iocurrent; + GPIOA->IE |= iocurrent; + + tmp = GPIOA->IOAWKUEN; + tmp &= ~(3U << (2 * position)); + switch (Wakeup_Event) + { + /* Disable wake-up function */ + default: + case IOA_DISABLE: + break; + + /* wake-up function: Rising */ + case IOA_RISING: + GPIOA->DAT &= ~iocurrent; + tmp |= 1 << (2 * position); + break; + + /* wake-up function: falling */ + case IOA_FALLING: + GPIOA->DAT |= iocurrent; + tmp |= 1 << (2 * position); + break; + + /* wake-up function: high level */ + case IOA_HIGH: + GPIOA->DAT &= ~iocurrent; + tmp |= 2 << (2 * position); + break; + + /* wake-up function: low level */ + case IOA_LOW: + GPIOA->DAT |= iocurrent; + tmp |= 2 << (2 * position); + break; + + /* wake-up function: both edge */ + case IOA_EDGEBOTH: + tmp |= 3 << (2 * position); + break; + } + GPIOA->IOAWKUEN = tmp; + } + position++; + } +} + +/** + * @brief Enters deep-sleep mode with low-power configuration. + * + * @param InitStruct : pointer to PMU_LowPWRTypeDef + CMP1Power: + PMU_COMP1PWR_ON + PMU_COMP1PWR_OFF + CMP2Power: + PMU_COMP2PWR_ON + PMU_COMP2PWR_OFF + TADCPower: + PMU_TADCPWR_ON + PMU_TADCPWR_OFF + BGPPower: + PMU_BGPPWR_ON + PMU_BGPPWR_OFF + AVCCPower: + PMU_AVCCPWR_ON + PMU_AVCCPWR_OFF + VDCINDetector: + PMU_VDCINDET_ENABLE + PMU_VDCINDET_DISABLE + VDDDetector: + PMU_VDDDET_ENABLE + PMU_VDDDET_DISABLE + APBPeriphralDisable: + PMU_APB_ALL + PMU_APB_DMA + PMU_APB_I2C + PMU_APB_SPI1 + PMU_APB_UART0 + PMU_APB_UART1 + PMU_APB_UART2 + PMU_APB_UART3 + PMU_APB_UART4 + PMU_APB_UART5 + PMU_APB_ISO78160 + PMU_APB_ISO78161 + PMU_APB_TIMER + PMU_APB_MISC + PMU_APB_U32K0 + PMU_APB_U32K1 + PMU_APB_SPI2 + PMU_APB_SPI3 + AHBPeriphralDisable: + PMU_AHB_ALL + PMU_AHB_DMA + PMU_AHB_GPIO + PMU_AHB_LCD + PMU_AHB_CRYPT + + * @note This function performs the following: + Comparator 1 power control ON or OFF(optional) + Comparator 2 power control ON or OFF(optional) + Tiny ADC power control ON or OFF(optional) + Bandgap power control ON or OFF(optional) + AVCC power control ON or OFF(optional) + VDCIN detector control Disable or Enable(optional) + VDD detector control Disable or Enable(optional) + Disable AHB/APB periphral clock Modules(optional) + Disable AVCC output + Disable ADC + Disable resistance division for ADC input signal + Enable LCD + + If 5V power supply, AVCCPower should be ON, if 3.3V power supply, AVCCPower should be OFF. + + * @retval 1: Current MODE is debug mode, enter deep-sleep mode failed. + 2: VDCIN is not drop before enter deep-sleep mode or Failure to enter deep sleep mode. + + */ +uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct) +{ + uint32_t tmp; + uint32_t hclk; + + /* Check parameters */ + assert_parameters(IS_PMU_COMP1PWR(InitStruct->CMP1Power)); + assert_parameters(IS_PMU_COMP2PWR(InitStruct->CMP2Power)); + assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower)); + assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower)); + assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower)); + assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector)); + assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector)); + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCOEN; + + /* Disable ADC */ + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + + /* Disable resistor division for ADC input signal */ + ANA->ADCCTRL1 &= ~ANA_ADCCTRL1_RESDIV_CHx; + + /******** Comparator 1 power control ********/ + ANA->REG3 &= ~ANA_REG3_CMP1PDN; + ANA->REG3 |= InitStruct->CMP1Power; + + /******** Comparator 2 power control ********/ + ANA->REG3 &= ~ANA_REG3_CMP2PDN; + ANA->REG3 |= InitStruct->CMP2Power; + + /******** Tiny ADC power control ********/ + tmp = ANA->REGF; + tmp &= ~ANA_REGF_ADTPDN; + tmp |= InitStruct->TADCPower; + ANA->REGF = tmp; + + /******** BGP power control ********/ + ANA->REG3 &= ~ANA_REG3_BGPPD; + ANA->REG3 |= InitStruct->BGPPower; + + /******** AVCC power control ********/ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_AVCCLDOPD; + tmp |= InitStruct->AVCCPower; + ANA->REG8 = tmp; + + /******** LCD controller power control ********/ + /* LCD should be ENABLE */ + tmp = LCD->CTRL; + tmp |= LCD_CTRL_EN; + LCD->CTRL = tmp; + + tmp = ANA->REG7; + tmp |= BIT7; + ANA->REG7 = tmp; + + /******** VDCIN detector control ********/ + tmp = ANA->REGA; + tmp &= ~ANA_REGA_VDCINDETPD; + tmp |= InitStruct->VDCINDetector; + ANA->REGA = tmp; + + /******** VDD detector control *********/ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_VDDDETPD; + tmp |= InitStruct->VDDDetector; + ANA->REG9 = tmp; + + /******** AHB Periphral clock disable selection ********/ + tmp = MISC2->HCLKEN; + tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL); + MISC2->HCLKEN = tmp; + + /******** APB Periphral clock disable selection ********/ + tmp = MISC2->PCLKEN; + tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL); + MISC2->PCLKEN = tmp; + + if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE) + { + if (!(ANA->CMPOUT & ANA_CMPOUT_VDCINDROP)) + { + return 2; + } + } + // make sure WKU is 0 before entering deep-sleep mode + while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU); + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + /* Enter deep-sleep mode */ + PMU->DSLEEPPASS = DSLEEPPASS_KEY; + PMU->DSLEEPEN = DSLEEPEN_KEY; + + return 2; +} + +/** + * @brief Enters sleep mode with low-power configuration. + * + * @param InitStruct : pointer to PMU_LowPWRTypeDef + CMP1Power: + PMU_COMP1PWR_ON + PMU_COMP1PWR_OFF + CMP2Power: + PMU_COMP2PWR_ON + PMU_COMP2PWR_OFF + TADCPower: + PMU_TADCPWR_ON + PMU_TADCPWR_OFF + BGPPower: + PMU_BGPPWR_ON + PMU_BGPPWR_OFF + AVCCPower: + PMU_AVCCPWR_ON + PMU_AVCCPWR_OFF + VDCINDetector: + PMU_VDCINDET_ENABLE + PMU_VDCINDET_DISABLE + VDDDetector: + PMU_VDDDET_ENABLE + PMU_VDDDET_DISABLE + APBPeriphralDisable: + PMU_APB_ALL + PMU_APB_DMA + PMU_APB_I2C + PMU_APB_SPI1 + PMU_APB_SPI2 + PMU_APB_UART0 + PMU_APB_UART1 + PMU_APB_UART2 + PMU_APB_UART3 + PMU_APB_UART4 + PMU_APB_UART5 + PMU_APB_ISO78160 + PMU_APB_ISO78161 + PMU_APB_TIMER + PMU_APB_MISC + PMU_APB_U32K0 + PMU_APB_U32K1 + PMU_APB_SPI3 + AHBPeriphralDisable: + PMU_AHB_ALL + PMU_AHB_DMA + PMU_AHB_GPIO + PMU_AHB_LCD + PMU_AHB_CRYPT + + * @note This function performs the following: + Comparator 1 power control ON or OFF(optional) + Comparator 2 power control ON or OFF(optional) + Tiny ADC power control ON or OFF(optional) + Bandgap power control ON or OFF(optional) + AVCC power control ON or OFF(optional) + VDCIN detector control Disable or Enable(optional) + VDD detector control Disable or Enable(optional) + Disable AHB/APB periphral clock Modules(optional) + Disable AVCC output + Disable ADC + Disable resistance division for ADC input signal + Enable LCD + + If 5V power supply, AVCCPower should be ON, if 3.3V power supply, AVCCPower should be OFF. + + * @retval 2: VDCIN is not drop before enter sleep mode(failed). + 1: Current mode is debug mode, enter sleep mode failed. + 0: Quit from sleep mode success. +*/ +uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct) +{ + uint32_t tmp; + uint32_t hclk; + + /* Check parameters */ + assert_parameters(IS_PMU_COMP1PWR(InitStruct->CMP1Power)); + assert_parameters(IS_PMU_COMP2PWR(InitStruct->CMP2Power)); + assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower)); + assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower)); + assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower)); + assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector)); + assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector)); + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCOEN; + + /* Disable ADC */ + ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN; + + /* Disable resistor division for ADC input signal */ + ANA->ADCCTRL1 &= ~ANA_ADCCTRL1_RESDIV_CHx ; + + /******** Comparator 1 power control ********/ + ANA->REG3 &= ~ANA_REG3_CMP1PDN; + ANA->REG3 |= InitStruct->CMP1Power; + + /******** Comparator 2 power control ********/ + ANA->REG3 &= ~ANA_REG3_CMP2PDN; + ANA->REG3 |= InitStruct->CMP2Power; + + /******** Tiny ADC power control ********/ + tmp = ANA->REGF; + tmp &= ~ANA_REGF_ADTPDN; + tmp |= InitStruct->TADCPower; + ANA->REGF = tmp; + + /******** BGP power control ********/ + ANA->REG3 &= ~ANA_REG3_BGPPD; + ANA->REG3 |= InitStruct->BGPPower; + + /******** AVCC power control ********/ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_AVCCLDOPD; + tmp |= InitStruct->AVCCPower; + ANA->REG8 = tmp; + + /******** LCD controller power control ********/ + /* LCD should be ENABLE */ + tmp = LCD->CTRL; + tmp |= LCD_CTRL_EN; + LCD->CTRL = tmp; + + tmp = ANA->REG7; + tmp |= BIT7; + ANA->REG7 = tmp; + + /******** VDCIN detector control ********/ + tmp = ANA->REGA; + tmp &= ~ANA_REGA_VDCINDETPD; + tmp |= InitStruct->VDCINDetector; + ANA->REGA = tmp; + + /******** VDD detector control *********/ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_VDDDETPD; + tmp |= InitStruct->VDDDetector; + ANA->REG9 = tmp; + + /******** AHB Periphral clock disable selection ********/ + tmp = MISC2->HCLKEN; + tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL); + MISC2->HCLKEN = tmp; + + /******** APB Periphral clock disable selection ********/ + tmp = MISC2->PCLKEN; + tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL); + MISC2->PCLKEN = tmp; + + if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE) + { + if (!(ANA->CMPOUT & ANA_CMPOUT_VDCINDROP)) + { + return 2; + } + } + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return 0; +} + + +/** + * @brief Enter idle mode with flash deep standby. + * @param None + * @retval None + */ +#ifndef __GNUC__ +void PMU_EnterIdle_LowPower(void) +{ + uint32_t hclk; + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + PMU_EnterIdle_FlashDSTB(); +} +#endif + +/** + * @brief Configures IOA wake-up source about sleep mode. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + Priority: The preemption priority for the IRQn channel. + This parameter can be a value between 0 and 3. + * @retval + */ +void PMU_SleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + /* Disable PMU interrupt in NVIC */ + NVIC_DisableIRQ(PMU_IRQn); + /* Wake-up pins configuration */ + PMU_WakeUpPinConfig(IOAx, Wakeup_Event); + /* Clear interrupt flag */ + GPIOA->IOAINTSTS = IOAx; + /* Enable PMU interrupt */ + PMU->CONTROL |= PMU_CONTROL_INT_IOA_EN; + CORTEX_SetPriority_ClearPending_EnableIRQ(PMU_IRQn, Priority); +} + +/** + * @brief Configures RTC wake-up source about sleep mode. + * @param Wakeup_Event: + This parameter can be any combination of the following values + PMU_RTCEVT_ALARM + PMU_RTCEVT_WKUCNT + PMU_RTCEVT_MIDNIGHT + PMU_RTCEVT_WKUHOUR + PMU_RTCEVT_WKUMIN + PMU_RTCEVT_WKUSEC + PMU_RTCEVT_TIMEILLE + PMU_RTCEVT_ITVSITV + Priority: The preemption priority for the IRQn channel. + This parameter can be a value between 0 and 3. + * @retval + */ +void PMU_SleepWKUSRCConfig_RTC(uint32_t Wakeup_Event, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RTCEVT(Wakeup_Event)); + + /* Disable RTC interrupt in NVIC */ + NVIC_DisableIRQ(RTC_IRQn); + /* Clear interrupt flag */ + RTC->INTSTS = Wakeup_Event; + /* Enable RTC interrupt */ + RTC->INTEN |= Wakeup_Event; + CORTEX_SetPriority_ClearPending_EnableIRQ(RTC_IRQn, Priority); +} +/** + * @brief Configures IOA wake-up source about deep-sleep mode. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + * @retval + */ +void PMU_DeepSleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + /* Wake-up pins configuration */ + PMU_WakeUpPinConfig(IOAx, Wakeup_Event); + /* Clear interrupt flag */ + GPIOA->IOAINTSTS = IOAx; +} + +/** + * @brief Configures RTC wake-up source about deep-sleep mode. + * @param Wakeup_Event: + This parameter can be any combination of the following values + PMU_RTCEVT_ALARM + PMU_RTCEVT_WKUCNT + PMU_RTCEVT_MIDNIGHT + PMU_RTCEVT_WKUHOUR + PMU_RTCEVT_WKUMIN + PMU_RTCEVT_WKUSEC + PMU_RTCEVT_TIMEILLE + PMU_RTCEVT_ITVSITV + * @retval + */ +void PMU_DeepSleepWKUSRCConfig_RTC(uint32_t Wakeup_Event) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RTCEVT(Wakeup_Event)); + + /* Clear interrupt flag */ + RTC->INTSTS = Wakeup_Event; + /* Enable RTC interrupt */ + RTC->INTEN |= Wakeup_Event; +} + +/** + * @brief Configures the deep sleep behavior when VDD/VDCIN is not drop. + * @param VDCIN_PDNS: + PMU_VDCINPDNS_0 , can't enter deep-sleep mode when VDCIN is not drop + can wake-up mcu from deep-sleep, when VDCIN is not drop. + PMU_VDCINPDNS_1 , The condition for entering deep sleep mode is independent of VDCIN. + VDD_PDNS: + PMU_VDDPDNS_0 , can't enter deep-sleep mode when VDD is not drop(>Threshold) + can wake-up mcu from deep-sleep, when VDD is not drop. + PMU_VDDPDNS_1 , The condition for entering deep sleep mode is independent of VDD. + * @retval None + */ +void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_VDCINPDNS(VDCIN_PDNS)); + assert_parameters(IS_PMU_VDDPDNS(VDD_PDNS)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_PDNS | ANA_CTRL_PDNS2); + tmp |= (VDCIN_PDNS | VDD_PDNS); + + ANA->CTRL = tmp; +} + +/** + * @brief Enables or disables BGP power. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_BGPCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG3 &= ~ANA_REG3_BGPPD; + else + ANA->REG3 |= ANA_REG3_BGPPD; +} + +/** + * @brief Configures VDD alarm threshold voltage. + * @param CheckTHR: + PMU_VDDALARM_4_5V + PMU_VDDALARM_4_2V + PMU_VDDALARM_3_9V + PMU_VDDALARM_3_6V + PMU_VDDALARM_3_2V + PMU_VDDALARM_2_9V + PMU_VDDALARM_2_6V + PMU_VDDALARM_2_3V + CheckFrequency: + PMU_VDDALARM_CHKFRE_NOCHECK + PMU_VDDALARM_CHKFRE_30US + * @retval None + */ +void PMU_VDDAlarmConfig(uint32_t CheckTHR,uint32_t CheckFrequency) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_VDDALARM_THR(CheckTHR)); + assert_parameters(IS_PMU_VDDALARM_CHKFRE(CheckFrequency)); + + /* Configure CheckTHR */ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_VDDPVDSEL; + tmp |= CheckTHR; + ANA->REG8 = tmp; + + /* Configure CheckFrequency */ + tmp = ANA->CMPCTL; + tmp &= ~ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL; + tmp |= CheckFrequency; + ANA->CMPCTL = tmp; + + if (CheckFrequency == PMU_VDDALARM_CHKFRE_NOCHECK) + { + ANA->REG9 |= ANA_REG9_VDDDETPD; + } + else + { + ANA->REG9 &= ~ANA_REG9_VDDDETPD; + } +} + +/** + * @brief Gets VDD alarm status. + * @param None + * @retval POWALARM status + 0: Voltage of VDD is higher than threshold. + 1: Voltage of VDD is lower than threshold. + */ +uint8_t PMU_GetVDDAlarmStatus(void) +{ + if (ANA->CMPOUT & ANA_CMPOUT_VDDALARM) + return 1; + else + return 0; +} + +/** + * @brief Gets current MODE pin status. + * @param None + * @retval MODE pin status + * 0: Debug mode. + * 1: Normal mode. + */ +uint8_t PMU_GetModeStatus(void) +{ + if(PMU->STS & PMU_STS_MODE) + return 1; + else + return 0; +} + +/** + * @brief Enables or disables AVCC. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_AVCCCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG8 &= ~ANA_REG8_AVCCLDOPD; + else + ANA->REG8 |= ANA_REG8_AVCCLDOPD; +} + +/** + * @brief Enables or disables VDD33_O pin power. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_AVCCOutputCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + ANA->REGF &= ~ANA_REGF_AVCCOEN; + else + ANA->REGF |= ANA_REGF_AVCCOEN; +} + +/** + * @brief Enables or disables AVCC Low Voltage detector. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_AVCCLVDetectorCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG5 &= ~ANA_REG5_AVCCLVDETPD; + else + ANA->REG5 |= ANA_REG5_AVCCLVDETPD; +} + +/** + * @brief Gets AVCC low power status. + * @param None + * @retval low power status of AVCC + * 0: status not set, AVCC is higher than 2.5V. + * 1: status set, AVCC is lower than 2.5V. + */ +uint8_t PMU_GetAVCCLVStatus(void) +{ + if (ANA->CMPOUT & ANA_CMPOUT_AVCCLV) + return 1; + else + return 0; +} + +/** + * @brief Enables or disables VDCIN decector. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_VDCINDetectorCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REGA &= ~ANA_REGA_VDCINDETPD; + else + ANA->REGA |= ANA_REGA_VDCINDETPD; +} + +/** + * @brief Selects VDCIN hysteresis. + * @param HYSSEL: + PMU_VDCINHYSSEL_100MV + PMU_VDCINHYSSEL_200MV + * @retval None + */ +void PMU_VDCINHYSSEL(uint32_t HYSSEL) +{ + uint32_t tmp; + /* Check parameters */ + assert_parameters(IS_PMU_VDCIN_HYSSEL(HYSSEL)); + + tmp = ANA->REG7; + tmp &= ~ANA_REG7_VDCINHYSSEL; + tmp |= HYSSEL; + ANA->REG7 = tmp; + + +} + +/** + * @brief Gets VDCIN drop status. + * @param None + * @retval drop status of VDCIN + 0: status not set, VDCIN is not drop. + 1: status set, VDCIN is drop. + */ +uint8_t PMU_GetVDCINDropStatus(void) +{ + if (ANA->CMPOUT & ANA_CMPOUT_VDCINDROP) + return 1; + else + return 0; +} + +/** + * @brief Configures VDDALARM, VDCIN and AVCCDET de-bounce. + * @param DEBSel: + 0: No de-bounce. + 1: 2 RTCCLK de-bounce. + 2: 3 RTCCLK de-bounce. + 3: 4 RTCCLK de-bounce. + 4: 5 RTCCLK de-bounce. + ... + 255: 256 RTCCLK de-bounce. + * @retval None + */ +void PMU_PWRDEBSel(uint32_t DEBSel) +{ + uint32_t tmp; + /* Check parameters */ + assert_parameters(IS_PMU_PWR_DEBSEL(DEBSel)); + + tmp = ANA->CMPCTL; + tmp &= ~ANA_CMPCTL_PWR_DEB_SEL; + tmp |= (DEBSel << ANA_CMPCTL_PWR_DEB_SEL_Pos); + ANA->CMPCTL = tmp; +} + +/** + * @brief Discharges or not discharges the BAT battery. + * @param BATDisc: + PMU_BAT1 + PMU_BATRTC + NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_PMU_BATRTCDISC(BATDisc)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG6 |= BATDisc; + else + ANA->REG6 &= ~BATDisc; +} + + +/** + * @brief Gets power status. + * @param StatusMask: + PMU_PWRSTS_AVCCLV + PMU_PWRSTS_VDCINDROP + PMU_PWRSTS_VDDALARM + * @retval power status + * 1 status set + * 0 status not set + */ +uint8_t PMU_GetPowerStatus(uint32_t StatusMask) +{ + if (ANA->CMPOUT & StatusMask) + return 1; + else + return 0; +} + +/** + * @brief Gets reset source status. + * @param Mask: + PMU_RSTSRC_EXTRST + PMU_RSTSRC_PORST + PMU_RSTSRC_DPORST + PMU_RSTSRC_WDTRST + PMU_RSTSRC_SFTRST + PMU_RSTSRC_MODERST + * @retval 1: Reset status set + 0: Reset status reset + */ +uint8_t PMU_GetResetSource(uint32_t Mask) +{ + /* Check parameters */ + assert_parameters(PMU_RESETSRC(Mask)); + + if (PMU->STS & Mask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears reset source status. + * @param Mask: can use the '|' operator + PMU_RSTSRC_EXTRST + PMU_RSTSRC_PORST + PMU_RSTSRC_DPORST + PMU_RSTSRC_WDTRST + PMU_RSTSRC_SFTRST + PMU_RSTSRC_MODERST + PMU_RSTSRC_ALL + * @retval None + */ +void PMU_ClearResetSource(uint32_t Mask) +{ + /* Check parameters */ + assert_parameters(PMU_RESETSRC_CLR(Mask)); + + PMU->STS = Mask; +} + +/** + * @brief Gets all reset source status. + * @param None + * @retval All reset source status + */ +uint32_t PMU_GetAllResetSource(void) +{ + return (PMU->STS & PMU_RSTSRC_Msk); +} + +/** + * @brief Gets deep-sleep wakeup source status. + * @param Mask: + PMU_DSLEEPWKUSRC_MODE + PMU_DSLEEPWKUSRC_XTAL + PMU_DSLEEPWKUSRC_U32K + PMU_DSLEEPWKUSRC_ANA + PMU_DSLEEPWKUSRC_RTC + PMU_DSLEEPWKUSRC_IOA + * @retval 1: Wakeup status set + 0: Wakeup status reset + */ +uint8_t PMU_GetDSleepWKUSource(uint32_t Mask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_DSLEEPWKUSRC(Mask)); + + if (PMU->STS & Mask) + return 1; + else + return 0; +} + +/** + * @brief Gest deep-sleep wakeup source status. + * @param None + * @retval All deep-sleep wakeup source status + */ +uint32_t PMU_GetAllDSleepWKUSource(void) +{ + return (PMU->STS & PMU_DSLEEPWKUSRC_Msk); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_pwm.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_pwm.c new file mode 100644 index 0000000000..23f3f64c7b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_pwm.c @@ -0,0 +1,530 @@ +/** + ****************************************************************************** + * @file lib_pwm.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief PWM library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_pwm.h" + +/** + * @brief Initializes PWM timebase. + * @param PWMx: PWM0~PWM3 + InitStruct:PWM BASE configuration. + ClockDivision: + PWM_CLKDIV_2 + PWM_CLKDIV_4 + PWM_CLKDIV_8 + PWM_CLKDIV_16 + Mode: + PWM_MODE_STOP + PWM_MODE_UPCOUNT + PWM_MODE_CONTINUOUS + PWM_MODE_UPDOWN + ClockSource: + PWM_CLKSRC_APB + PWM_CLKSRC_APBD128 + * @retval None + */ +void PWM_BaseInit(PWM_Type *PWMx, PWM_BaseInitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CLKDIV(InitStruct->ClockDivision)); + assert_parameters(IS_PWM_CNTMODE(InitStruct->Mode)); + assert_parameters(IS_PWM_CLKSRC(InitStruct->ClockSource)); + + tmp = PWMx->CTL; + tmp &= ~(PWM_CTL_ID\ + |PWM_CTL_MC\ + |PWM_CTL_TSEL); + tmp |= (InitStruct->ClockDivision\ + |InitStruct->Mode\ + |InitStruct->ClockSource); + PWMx->CTL = tmp; +} + +/** + * @brief Fills each PWM_BaseInitType member with its default value. + * @param InitStruct: pointer to an PWM_BaseInitType structure which will be initialized. + * @retval None + */ +void PWM_BaseStructInit(PWM_BaseInitType *InitStruct) +{ + /*------------ Reset PWM base init structure parameters values ------------*/ + /* Initialize the ClockDivision member */ + InitStruct->ClockDivision = PWM_CLKDIV_2; + /* Initialize the ClockSource member */ + InitStruct->ClockSource = PWM_CLKSRC_APBD128; + /* Initialize the Mode member */ + InitStruct->Mode = PWM_MODE_STOP; +} + +/** + * @brief Fills each PWM_OCInitType member with its default value. + * @param OCInitType: pointer to an PWM_OCInitType structure which will be initialized. + * @retval None + */ +void PWM_OCStructInit(PWM_OCInitType *OCInitType) +{ + /*------- Reset PWM output channel init structure parameters values --------*/ + /* Initialize the Channel member */ + OCInitType->Channel = PWM_CHANNEL_0; + /* Initialize the OutMode member */ + OCInitType->OutMode = PWM_OUTMOD_CONST; + /* Initialize the Period member */ + OCInitType->Period = 0; +} + +/** + * @brief Initializes PWM channel output compare function. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OCInit(PWM_Type *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(OCInitType->Channel)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL[OCInitType->Channel]; + tmp &= ~(PWM_CCTL_CAP | PWM_CCTL_OUTMOD | PWM_CCTL_CCIFG | PWM_CCTL_COV); + tmp |= OCInitType->OutMode; + PWMx->CCTL[OCInitType->Channel] = tmp; + PWMx->CCR[OCInitType->Channel] = OCInitType->Period; +} + +/** + * @brief Fills each PWM_ICInitType member with its default value. + * @param ICInitType: pointer to a PWM_OCInitType structure which will be initialized. + * @retval None + */ +void PWM_ICStructInit(PWM_ICInitType *ICInitType) +{ + /*------- Reset PWM output channel init structure parameters values --------*/ + /* Initialize the Channel member */ + ICInitType->Channel = PWM_CHANNEL_0; + /* Initialize the CaptureMode member */ + ICInitType->CaptureMode = PWM_CM_DISABLE; +} + + +/** + * @brief Initializes PWM channel input capture function. + * @param PWMx: PWM0~PWM3 + ICInitType:PWM output compare configuration. + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + CaptureMode: + PWM_CM_DISABLE + PWM_CM_RISING + PWM_CM_FALLING + PWM_CM_BOTH + * @retval None + */ +void PWM_ICInit(PWM_Type *PWMx, PWM_ICInitType *ICInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(ICInitType->Channel)); + assert_parameters(IS_PWM_CAPMODE(ICInitType->CaptureMode)); + + tmp = PWMx->CCTL[ICInitType->Channel]; + tmp &= ~(PWM_CCTL_CM | PWM_CCTL_CAP | PWM_CCTL_CCIFG | PWM_CCTL_COV); + tmp |= (ICInitType->CaptureMode | PWM_CCTL_CAP); + PWMx->CCTL[ICInitType->Channel] = tmp; +} + +/** + * @brief Enables or disables PWM base interrupt. + * @param PWMx: PWM0~PWM3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_BaseINTConfig(PWM_Type *PWMx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = PWMx->CTL; + tmp &= ~(PWM_CTL_IE | PWM_CTL_IFG); + if (NewState == ENABLE) + { + tmp |= PWM_CTL_IE; + } + PWMx->CTL = tmp; +} + +/** + * @brief Gets PWM base interrupt status. + * @param PWMx: PWM0~PWM3 + * @retval interrupt status. + */ +uint8_t PWM_GetBaseINTStatus(PWM_Type *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + if (PWMx->CTL&PWM_CTL_IFG) + return 1; + else + return 0; +} + +/** + * @brief Clears PWM base interrupt status. + * @param PWMx: PWM0~PWM3 + * @retval None. + */ +void PWM_ClearBaseINTStatus(PWM_Type *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + PWMx->CTL |= PWM_CTL_IFG; +} + +/** + * @brief Enables or disables channel interrupt. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_ChannelINTConfig(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = PWMx->CCTL[Channel]; + tmp &= ~(PWM_CCTL_CCIE | PWM_CCTL_CCIFG | PWM_CCTL_COV); + if (NewState == ENABLE) + { + tmp |= PWM_CCTL_CCIE; + } + PWMx->CCTL[Channel] = tmp; +} + +/** + * @brief Gets channel interrupt status. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + IntMask: + PWM_INT_CCIFG + PWM_INT_COV + * @retval interrupt status + */ +uint8_t PWM_GetChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_PWM_INTFLAGR(IntMask)); + + if (PWMx->CCTL[Channel] & IntMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears channel interrupt status. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Int_Mask: + PWM_INT_CCIFG + PWM_INT_COV + * @retval None + */ +void PWM_ClearChannelINTStatus(PWM_Type *PWMx, uint32_t Channel, uint32_t IntMask) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_PWM_INTFLAGC(IntMask)); + + tmp = PWMx->CCTL[Channel]; + tmp &= ~PWM_INT_Msk; + tmp |= IntMask; + PWMx->CCTL[Channel] = tmp; +} + +/** + * @brief Clears PWM counter. + * @param PWMx: PWM0~PWM3 + * @retval None + */ +void PWM_ClearCounter(PWM_Type *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + PWMx->CTL |= PWM_CTL_CLR; +} + +/** + * @brief Configures PWM channel CCR value. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_CCRConfig(PWM_Type *PWMx, uint32_t Channel, uint16_t Period) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + PWMx->CCR[Channel] = Period; +} + +/** + * @brief Configures PWM output line. + * @param OutSelection: + PWM0_OUT0 + PWM0_OUT1 + PWM0_OUT2 + PWM1_OUT0 + PWM1_OUT1 + PWM1_OUT2 + PWM2_OUT0 + PWM2_OUT1 + PWM2_OUT2 + PWM3_OUT0 + PWM3_OUT1 + PWM3_OUT2 + OLine: can use the '|' operator + PWM_OLINE_0 + PWM_OLINE_1 + PWM_OLINE_2 + PWM_OLINE_3 + * @note PWM Single channel's output waveform can be output on multiple output lines. + * Multiple-line configuration can be performed by using the '|' operator. + * ex: PWM_OLineConfig(PWM0_OUT0, PWM_OLINE_0 | PWM_OLINE_2) + * PWM0 channel0 output by PWM0&PWM2's line. + * @retval None + */ +void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine) +{ + uint32_t tmp; + uint32_t position = 0; + + /* Check parameters */ + assert_parameters(IS_PWM_OUTLINE(OLine)); + assert_parameters(IS_PWM_OUTSEL(OutSelection)); + + tmp = PWM_SEL->O_SEL; + while ((OLine >> position) != 0UL) + { + if ((OLine >> position) & 1UL) + { + tmp &= ~(PWM_SEL_O_SEL_SEL0 << (position * 4)); + tmp |= (OutSelection << (position * 4)); + } + position++; + } + PWM_SEL->O_SEL = tmp; +} + +/** + * @brief Enables disables PWM output function. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_OutputCmd(PWM_Type *PWMx, uint32_t Channel, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = PWMx->CCTL[Channel]; + tmp &= ~(PWM_CCTL_CCIFG | PWM_CCTL_COV); + if (NewState == ENABLE) + { + tmp |= PWM_CCTL_OUTEN; + } + else + { + tmp &= ~PWM_CCTL_OUTEN; + } + PWMx->CCTL[Channel] = tmp; +} + +/** + * @brief Sets PWM channel output level. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Level: + PWM_LEVEL_HIGH + PWM_LEVEL_LOW + * @retval None + */ +void PWM_SetOutLevel(PWM_Type *PWMx, uint32_t Channel, uint32_t Level) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_PWM_OUTLVL(Level)); + + tmp = PWMx->CCTL[Channel]; + tmp &= ~(PWM_CCTL_OUT | PWM_CCTL_CCIFG | PWM_CCTL_COV); + tmp |= Level; + PWMx->CCTL[Channel] = tmp; +} + +/** + * @brief Configures PWM input line. + * @param InSelection: + PWM1_IN2 + PWM1_IN1 + PWM1_IN0 + PWM0_IN2 + PWM0_IN1 + PWM0_IN0 + PWM3_IN2 + PWM3_IN1 + PWM3_IN0 + PWM2_IN2 + PWM2_IN1 + PWM2_IN0 + ILine: + PWM_ILINE_0 + PWM_ILINE_1 + PWM_ILINE_2 + PWM_ILINE_3 + * @retval None + */ +void PWM_ILineConfig(uint32_t InSelection, uint32_t ILine) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_INLINE(ILine)); + assert_parameters(IS_PWM_INSEL(InSelection)); + + addr = &PWM_SEL->I_SEL01 + ((InSelection&0xF00)>>8); + tmp = *addr; + tmp &= ~( 3 << (InSelection&0xFF)); + tmp |= (ILine << (InSelection&0xFF)); + *addr = tmp; +} + +/** + * @brief Gets PWM channel SCCI value. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + * @retval INx¡¯s input value when the TAR is equal to CCRx + */ +uint8_t PWM_GetSCCI(PWM_Type *PWMx, uint32_t Channel) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + if (PWMx->CCTL[Channel] & PWM_CCTL_SCCI) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Gets PWM channel capture value. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + * @retval The value of CCRx. + */ +uint32_t PWM_GetCapture(PWM_Type *PWMx, uint32_t Channel) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + return PWMx->CCR[Channel]; +} + +/******************* (C) COPYRIGHT Vango Technologies, Inc *****END OF FILE****/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_rtc.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_rtc.c new file mode 100644 index 0000000000..3f2b3aec1c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_rtc.c @@ -0,0 +1,793 @@ +/** + ****************************************************************************** + * @file lib_rtc.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief RTC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_rtc.h" + +#define RTCPWD_KEY 0x5AA55AA5 +#define RTCCE_SETKEY 0xA55AA55B +#define RTCCE_CLRKEY 0xA55AA55A + +/** + * @brief Enables or disables RTC registers write protection. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_WriteProtection(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + /* Enable RTC Write-Protection */ + if (NewState != DISABLE) + { + RTC->PWD = RTCPWD_KEY; + RTC->CE = RTCCE_CLRKEY; + } + /* Disable RTC Write-Protection */ + else + { + RTC->PWD = RTCPWD_KEY; + RTC->CE = RTCCE_SETKEY; + } +} + +/** + * @brief Waits until the RTC registers (be W/R protected) are synchronized + * with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtection(DISABLE) before calling this function. + * Write-Operation process as follows: + * 1. RTC_WriteProtection(DISABLE); + * 2. RTC Registers write operation(only first write-operation be + * valid on the same register). + * 3. RTC_WriteProtection(ENABLE); + * 4. RTC_WaitForSynchro(); Wait until the RTC registers be + * synchronized by calling this function. + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + while (RTC->CE & RTC_CE_BSY) + { + } +} + +/** + * @brief Writes RTC registers(continuous/be write-protected). + * @param[in] StartAddr the start address of registers be written + * @param[in] wBuffer pointer to write + * @param[in] Len number of registers be written + * @retval None + */ +void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len) +{ + uint8_t cnt; + + /* Parameter check */ + assert_parameters(IS_RTC_REGOP_STARTADDR(StartAddr)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + for (cnt=0; cntLOAD */ + tmp = RTC->LOAD; + tmp += 1; + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read registers */ + for (cnt=0; cntYear)); + assert_parameters(IS_RTC_TIME_MONTH(sTime->Month)); + assert_parameters(IS_RTC_TIME_DATE(sTime->Date)); + assert_parameters(IS_RTC_TIME_WEEKDAY(sTime->WeekDay)); + assert_parameters(IS_RTC_TIME_HOURS(sTime->Hours)); + assert_parameters(IS_RTC_TIME_MINS(sTime->Minutes)); + assert_parameters(IS_RTC_TIME_SECS(sTime->Seconds)); + if (AccurateSel == RTC_ACCURATE) + assert_parameters(IS_RTC_TIME_SubSECS(sTime->SubSeconds)); + assert_parameters(IS_RTC_ACCURATESEL(AccurateSel)); + + subsec = sTime->SubSeconds; + subsec = subsec -(subsec>>8)*156 -((subsec&0xFF)>>4)*6; + sec = sTime->Seconds; + sec = sec - (sec>>4)*6; + subsec = sec * 32768 + subsec * 32768 / 1000; + + alarmctl = RTC->ALARMCTL; + if (AccurateSel == RTC_ACCURATE) + alarmctl |= RTC_ALARMCTL_TIME_CNT_EN; + else + alarmctl &= ~RTC_ALARMCTL_TIME_CNT_EN; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write RTC time registers */ + RTC->TIME = subsec; + RTC->SEC = sTime->Seconds; + RTC->MIN = sTime->Minutes; + RTC->HOUR = sTime->Hours; + RTC->DAY = sTime->Date; + RTC->WEEK = sTime->WeekDay; + RTC->MON = sTime->Month; + RTC->YEAR = sTime->Year; + RTC->ALARMCTL = alarmctl; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Gets RTC current time. + * @param[out] gTime: Pointer to Time structure + * @param[in] AccurateSel: + * RTC_ACCURATE + * RTC_INACCURATE + * @retval None +*/ +void RTC_GetTime(RTC_TimeTypeDef *gTime, uint32_t AccurateSel) +{ + __IO uint32_t dummy_data = 0; + uint32_t subsec,sec; + + /* Parameter check */ + assert_parameters(IS_RTC_ACCURATESEL(AccurateSel)); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Dummy read-operation to RTC->LOAD register */ + dummy_data = RTC->LOAD; + dummy_data += 1; + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read RTC time registers */ + gTime->Seconds = RTC->SEC; + gTime->Minutes = RTC->MIN; + gTime->Hours = RTC->HOUR; + gTime->Date = RTC->DAY; + gTime->WeekDay = RTC->WEEK; + gTime->Month = RTC->MON; + gTime->Year = RTC->YEAR; + subsec = RTC->TIME; + + if (AccurateSel == RTC_ACCURATE) + { + sec = subsec/32768; + sec = sec + (sec/10)*6; + gTime->Seconds = sec; + subsec = (subsec%32768)*1000/32768; + subsec = subsec + ((subsec%100)/10)*6 + (subsec/100)*156; + gTime->SubSeconds = subsec; + } + else + { + gTime->SubSeconds = 0; + } +} + +/** + * @brief Enables or disables the RTC Sub Seconds. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_SubSecondCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->ALARMCTL; + if (NewState == ENABLE) + { + tmp |= RTC_ALARMCTL_TIME_CNT_EN; + } + else + { + tmp &= ~RTC_ALARMCTL_TIME_CNT_EN; + } + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ALARMCTL = tmp; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Sets the RTC Alarm. + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * AccurateSel: + * RTC_ACCURATE + * RTC_INACCURATE + * @retval None + */ +void RTC_SetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel) +{ + uint32_t subsec,sec,alarmctl; + /* Parameter check */ + assert_parameters(IS_RTC_TIME_HOURS(RTC_AlarmStruct->AlarmHours)); + assert_parameters(IS_RTC_TIME_MINS(RTC_AlarmStruct->AlarmMinutes)); + assert_parameters(IS_RTC_TIME_SECS(RTC_AlarmStruct->AlarmSeconds)); + if (AccurateSel == RTC_ACCURATE) + assert_parameters(IS_RTC_TIME_SubSECS(RTC_AlarmStruct->AlarmSubSeconds)); + assert_parameters(IS_RTC_ACCURATESEL(AccurateSel)); + + subsec = RTC_AlarmStruct->AlarmSubSeconds; + subsec = subsec -(subsec>>8)*156 -((subsec&0xFF)>>4)*6; + sec = RTC_AlarmStruct->AlarmSeconds; + sec = sec - (sec>>4)*6; + subsec = sec * 32768 + subsec * 32768 / 1000; + + alarmctl = RTC->ALARMCTL; + if (AccurateSel == RTC_ACCURATE) + alarmctl &= ~RTC_ALARMCTL_ALARM_INACCURATE; + else + alarmctl |= RTC_ALARMCTL_ALARM_INACCURATE; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ALARMHOUR = RTC_AlarmStruct->AlarmHours; + RTC->ALARMMIN = RTC_AlarmStruct->AlarmMinutes; + RTC->ALARMSEC = RTC_AlarmStruct->AlarmSeconds; + RTC->ALARMTIME = subsec; + RTC->ALARMCTL = alarmctl; + /* Write RTC time registers */ + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Gets the RTC Alarm. + * @param[out] RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * @param[in] AccurateSel: + * RTC_ACCURATE + * RTC_INACCURATE + * @retval None + */ +void RTC_GetAlarm(RTC_AlarmTypeDef *RTC_AlarmStruct, uint32_t AccurateSel) +{ + uint32_t sec,subsec; + + /* Parameter check */ + assert_parameters(IS_RTC_ACCURATESEL(AccurateSel)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read RTC time registers */ + RTC_AlarmStruct->AlarmHours = RTC->ALARMHOUR; + RTC_AlarmStruct->AlarmMinutes = RTC->ALARMMIN; + RTC_AlarmStruct->AlarmSeconds = RTC->ALARMSEC; + subsec = RTC->ALARMTIME; + + if (AccurateSel == RTC_ACCURATE) + { + sec = subsec/32768; + sec = sec + (sec/10)*6; + RTC_AlarmStruct->AlarmSeconds = sec; + subsec = (subsec%32768)*1000/32768; + subsec = subsec + ((subsec%100)/10)*6 + (subsec/100)*156; + RTC_AlarmStruct->AlarmSubSeconds = subsec; + } + else + { + RTC_AlarmStruct->AlarmSubSeconds = 0; + } +} + +/** + * @brief Enables or disables the RTC Alarm. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_AlarmCmd(uint32_t NewState) +{ + uint32_t tmp; + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->ALARMCTL; + if (NewState == ENABLE) + { + tmp |= (RTC_ALARMCTL_ALARM_EN); + } + else + { + tmp &= ~(RTC_ALARMCTL_ALARM_EN); + } + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ALARMCTL = tmp; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Enables or disables the RTC alarm accurate. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_AlarmAccurateCmd(uint32_t NewState) +{ + uint32_t tmp = 0; + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->ALARMCTL; + if (NewState == ENABLE) + { + tmp &= ~RTC_ALARMCTL_ALARM_INACCURATE; + } + else + { + tmp |= RTC_ALARMCTL_ALARM_INACCURATE; + } + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ALARMCTL = tmp; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Enables or disables RTC interrupt. + * @param INTMask: can use the '|' operator + RTC_INT_ALARM + RTC_INT_CEILLE + RTC_INT_ACDONE + RTC_INT_WKUCNT + RTC_INT_MIDNIGHT + RTC_INT_WKUHOUR + RTC_INT_WKUMIN + RTC_INT_WKUSEC + RTC_INT_TIMEILLE + RTC_INT_ITVSITV + NewState: + ENABLE + DISABLE + * @retval None + */ +void RTC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + RTC->INTEN |= INTMask; + else + RTC->INTEN &= ~INTMask; +} + +/** + * @brief Gets RTC interrupt status. + * @param INTMask: + RTC_INTSTS_ALARM + RTC_INTSTS_CEILLE + RTC_INTSTS_WKUCNT + RTC_INTSTS_MIDNIGHT + RTC_INTSTS_WKUHOUR + RTC_INTSTS_WKUMIN + RTC_INTSTS_WKUSEC + RTC_INTSTS_TIMEILLE + RTC_INTSTS_ITVSITV + * @retval 1: status set + 0: status reset. + */ +uint8_t RTC_GetINTStatus(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INTFLAGR(FlagMask)); + + if (RTC->INTSTS&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears RTC interrupt status. + * @param INTMask: can use the '|' operator + RTC_INTSTS_ALARM + RTC_INTSTS_CEILLE + RTC_INTSTS_WKUCNT + RTC_INTSTS_MIDNIGHT + RTC_INTSTS_WKUHOUR + RTC_INTSTS_WKUMIN + RTC_INTSTS_WKUSEC + RTC_INTSTS_TIMEILLE + RTC_INTSTS_ITVSITV + * @retval None + */ +void RTC_ClearINTStatus(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INTFLAGC(FlagMask)); + + RTC->INTSTS = FlagMask; +} + +/* + * @brief Configures Multi-second wake up function. + * @param nPeriod: N seconds interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 sec error if the new WKUSEC number(parameter) is not equal + * to current WKUSEC number. If the new WKUSEC is equal to current WKUSEC, + * the first interrupt time may have 0~(WKUSEC +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUSecondsConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUSEC_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUSEC = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/* + * @brief Configures Multi-minute wake up function. + * @param nPeriod: N minute interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 min error if the new WKUMIN number(parameter) is not equal + * to current WKUMIN number. If the new WKUMIN is equal to current WKUMIN, + * the first interrupt time may have 0~(WKUMIN +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUMinutesConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUMIN_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUMIN = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/* + * @brief Configures Multi-hour wake up function. + * @param nPeriod: N hour interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 hour error if the new WKUHOUR number(parameter) is not equal + * to current WKUHOUR number. If the new WKUHOUR is equal to current WKUHOUR, + * the first interrupt time may have 0~(WKUHOUR +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUHoursConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUHOUR_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUHOUR = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Configures RTC counter wake up function. + * @param nClock: + CNTCLK: + RTC_WKUCNT_RTCCLK + RTC_WKUCNT_2048 + RTC_WKUCNT_512 + RTC_WKUCNT_128 + * @retval None + */ +void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUCNT_PERIOD(nClock)); + assert_parameters(IS_RTC_WKUCNT_CNTSEL(CNTCLK)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUCNT = (CNTCLK & RTC_WKUCNT_CNTSEL) | ((nClock & RTC_WKUCNT_WKUCNT) -1 ); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Configures RTC ITV wake up function. + * @param nType: + RTC_ITV_SEC + RTC_ITV_MIN + RTC_ITV_HOUR + RTC_ITV_DAY + RTC_ITV_500MS + RTC_ITV_250MS + RTC_ITV_125MS + RTC_ITV_62MS + * @retval None + */ +void RTC_WAKE_ITV(uint8_t nType) +{ + /* Parameter check */ + assert_parameters(IS_RTC_ITV(nType)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->SITV = 0; + RTC->ITV = nType; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Configures RTC SITV wake up function. + * @param nPeriod:1~64 + * @retval None + */ +void RTC_WAKE_SITV(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_SITV(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ITV = RTC_ITV_SITVSEC; + RTC->SITV = RTC_SITV_SITVEN | ((nPeriod - 1)&RTC_SITV_SITV); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Gets RTC wake-up counter value. + * @retval RTC wake-up counter value + */ +uint32_t RTC_GetWKUCounterValue(void) +{ + return RTC->WKUCNTR; +} + +/** + * @brief Configures RTC clock prescaler. + * @param[in] Prescaler: + * RTC_CLKDIV_1 + * RTC_CLKDIV_4 + * @retval None + */ +void RTC_PrescalerConfig(uint32_t Prescaler) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_CLKDIV(Prescaler)); + + tmp = RTC->PSCA; + tmp &= ~RTC_PSCA_PSCA; + tmp |= Prescaler; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->PSCA = tmp; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Configures RTC PLLDIV clock-source and frequency. + * @param Source: + RTC_PLLDIVSOURCE_PLLL + RTC_PLLDIVSOURCE_PCLK + nfrequency(HZ): the frequency of RTC PLLDIV output configuration. + * @note Ensure clocks be configured by calling function CLK_ClockConfig(), + * get correct PCLK frequency by calling function CLK_GetPCLKFreq(). + * @retval None + */ +void RTC_PLLDIVConfig(uint32_t DIVSource,uint32_t nfrequency) +{ + /* Parameter check */ + assert_parameters(IS_RTC_PLLDIVSOURCE(DIVSource)); + + if (DIVSource == RTC_PLLDIVSOURCE_PLLL) + { + RTC->CTL |= RTC_CTL_RTCPLLCLKSEL; + if (nfrequency == 0) + { + RTC->DIV = RTC_DIV_RTCDIV; + } + else + { + RTC->DIV = CLK_GetPLLLFreq()/2/nfrequency - 1; + } + } + else + { + RTC->CTL &= ~RTC_CTL_RTCPLLCLKSEL; + if (nfrequency == 0) + { + RTC->DIV = RTC_DIV_RTCDIV; + } + else + { + RTC->DIV = CLK_GetPCLKFreq()/2/nfrequency - 1; + } + } +} + +/** + * @brief Enables or disables RTC PLLDIV output function. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_PLLDIVOutputCmd(uint8_t NewState) +{ + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) RTC->CTL |= RTC_CTL_RTCPLLOE; + else RTC->CTL &= ~RTC_CTL_RTCPLLOE; +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_spi.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_spi.c new file mode 100644 index 0000000000..7f9387948c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_spi.c @@ -0,0 +1,429 @@ +/** + ****************************************************************************** + * @file lib_spi.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief SPI library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_spi.h" + +#define SPI_MISC_RSTValue (0UL) + +/** + * @brief Initializes SPI peripheral registers to their default reset values(Reset SPI FIFO when this function is called). + * @param SPIx:SPI1~SPI3 + * @retval None + */ +void SPI_DeviceInit(SPI_Type *SPIx) +{ + __IO uint32_t dummy_data = 0UL; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Disable SPI */ + SPIx->CTRL = 0; + /* SPI soft reset */ + SPIx->CTRL |= SPI_CTRL_RST; + SPIx->CTRL &= ~SPI_CTRL_RST; + /* Clear flag */ + dummy_data = SPIx->RXDAT; + dummy_data += 1; + SPIx->TXSTS = SPI_TXSTS_TXIF|SPI_TXSTS_DMATXDONE; + SPIx->RXSTS = SPI_RXSTS_RXIF; + /* write default values */ + SPIx->MISC = SPI_MISC_RSTValue; +} + +/** + * @brief Fills each SPI_InitType member with its default value. + * @param InitStruct: pointer to an SPI_InitType structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitType *InitStruct) +{ + /*--------------- Reset SPI init structure parameters values ---------------*/ + /* Initialize the ClockDivision member */ + InitStruct->ClockDivision = SPI_CLKDIV_2; + /* Initialize the CSNSoft member */ + InitStruct->CSNSoft = SPI_CSNSOFT_DISABLE; + /* Initialize the Mode member */ + InitStruct->Mode = SPI_MODE_MASTER; + /* Initialize the SPH member */ + InitStruct->SPH = SPI_SPH_0; + /* Initialize the SPO member */ + InitStruct->SPO = SPI_SPO_0; + /* Initialize the SWAP member */ + InitStruct->SWAP = SPI_SWAP_DISABLE; +} + +/** + * @brief Initializes SPI. + * @param SPIx:SPI1~SPI3 + InitStruct: SPI configuration. + Mode: + SPI_MODE_MASTER + SPI_MODE_SLAVE + SPH: + SPI_SPH_0 + SPI_SPH_1 + SPO: + SPI_SPO_0 + SPI_SPO_1 + ClockDivision: + SPI_CLKDIV_2 + SPI_CLKDIV_4 + SPI_CLKDIV_8 + SPI_CLKDIV_16 + SPI_CLKDIV_32 + SPI_CLKDIV_64 + SPI_CLKDIV_128 + CSNSoft: + SPI_CSNSOFT_ENABLE + SPI_CSNSOFT_DISABLE + SWAP: + SPI_SWAP_ENABLE + SPI_SWAP_DISABLE + * @retval None + */ +void SPI_Init(SPI_Type *SPIx, SPI_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_MODE(InitStruct->Mode)); + assert_parameters(IS_SPI_SPH(InitStruct->SPH)); + assert_parameters(IS_SPI_SPO(InitStruct->SPO)); + assert_parameters(IS_SPI_CLKDIV(InitStruct->ClockDivision)); + assert_parameters(IS_SPI_CSN(InitStruct->CSNSoft)); + assert_parameters(IS_SPI_SWAP(InitStruct->SWAP)); + + tmp = SPIx->CTRL; + tmp &= ~(SPI_CTRL_MOD\ + |SPI_CTRL_SCKPHA\ + |SPI_CTRL_SCKPOL\ + |SPI_CTRL_CSGPIO\ + |SPI_CTRL_SWAP\ + |SPI_CTRL_SCKSEL); + tmp |= (InitStruct->Mode\ + |InitStruct->SPH\ + |InitStruct->SPO\ + |InitStruct->CSNSoft\ + |InitStruct->SWAP\ + |InitStruct->ClockDivision); + SPIx->CTRL = tmp; +} + +/** + * @brief Enables or disables SPI. + * @param SPIx:SPI1~SPI3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_Cmd(SPI_Type *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + SPIx->CTRL |= SPI_CTRL_EN; + else + SPIx->CTRL &= ~SPI_CTRL_EN; +} + +/** + * @brief Enables or disables SPI interrupt. + * @param SPIx:SPI1~SPI3 + INTMask: can use the '|' operator + SPI_INT_TX + SPI_INT_RX + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_INTConfig(SPI_Type *SPIx, uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (INTMask & 0x80000000) + { + tmp = SPIx->TXSTS; + tmp &= ~SPI_TXSTS_TXIF; + if (NewState == ENABLE) + { + tmp |= (INTMask&0xFFFF); + SPIx->TXSTS = tmp; + } + else + { + tmp &= ~(INTMask&0xFFFF); + SPIx->TXSTS = tmp; + } + } + if (INTMask & 0x40000000) + { + tmp = SPIx->RXSTS; + tmp &= ~SPI_RXSTS_RXIF; + if (NewState == ENABLE) + { + tmp |= (INTMask&0xFFFF); + SPIx->RXSTS = tmp; + } + else + { + tmp &= ~(INTMask&0xFFFF); + SPIx->RXSTS = tmp; + } + } +} + +/** + * @brief Gets SPI status flag. + * @param SPIx:SPI1~SPI3 + Status: + SPI_STS_TXIF + SPI_STS_TXEMPTY + SPI_STS_TXFUR + SPI_STS_DMATXDONE + SPI_STS_RXIF + SPI_STS_RXFULL + SPI_STS_RXFOV + SPI_STS_BSY + SPI_STS_RFF + SPI_STS_RNE + SPI_STS_TNF + SPI_STS_TFE + * @retval Flag status. + */ +uint8_t SPI_GetStatus(SPI_Type *SPIx, uint32_t Status) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_STSR(Status)); + + if ((Status&0xE0000000) == 0x80000000) + { + if (Status&SPIx->TXSTS) + return 1; + else + return 0; + } + else if ((Status&0xE0000000) == 0x40000000) + { + if (Status&SPIx->RXSTS) + return 1; + else + return 0; + } + else + { + if (Status&SPIx->MISC) + return 1; + else + return 0; + } +} + +/** + * @brief Clears SPI status flag. + * @param SPIx:SPI1~SPI3 + Status: can use the '|' operator + SPI_STS_TXIF + SPI_STS_RXIF + SPI_STS_DMATXDONE + * @retval None + */ +void SPI_ClearStatus(SPI_Type *SPIx, uint32_t Status) +{ + uint32_t tmp = 0UL; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_STSC(Status)); + + if (Status & 0x80000000) + { + tmp = SPIx->TXSTS; + tmp &= ~(SPI_TXSTS_DMATXDONE | SPI_TXSTS_TXIF); + tmp |= (Status&0xFFFF); + SPIx->TXSTS = tmp; + } + if (Status & 0x40000000) + { + SPIx->RXSTS |= (Status&0xFFFF); + } +} + +/** + * @brief Loads send data register. + * @param SPIx:SPI1~SPI3 + ch: data write to send data register + * @retval None + */ +void SPI_SendData(SPI_Type *SPIx, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + SPIx->TXDAT = ch; +} + +/** + * @brief Reads receive data register. + * @param SPIx:SPI1~SPI3 + * @retval receive data value + */ +uint8_t SPI_ReceiveData(SPI_Type *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->RXDAT); +} + +/** + * @brief Configures transmit fifo level. + * @param SPIx:SPI1~SPI3 + FIFOLevel: + SPI_TXFLEV_0 + SPI_TXFLEV_1 + SPI_TXFLEV_2 + SPI_TXFLEV_3 + SPI_TXFLEV_4 + SPI_TXFLEV_5 + SPI_TXFLEV_6 + SPI_TXFLEV_7 + * @retval None + */ +void SPI_TransmitFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_TXFLEV(FIFOLevel)); + + tmp = SPIx->TXSTS; + tmp &= ~(SPI_TXSTS_TXFLEV | SPI_TXSTS_TXIF|SPI_TXSTS_DMATXDONE); + tmp |= FIFOLevel; + SPIx->TXSTS = tmp; +} + +/** + * @brief Configures receive fifo level. + * @param SPIx:SPI1~SPI3 + FIFOLevel: + SPI_RXFLEV_0 + SPI_RXFLEV_1 + SPI_RXFLEV_2 + SPI_RXFLEV_3 + SPI_RXFLEV_4 + SPI_RXFLEV_5 + SPI_RXFLEV_6 + SPI_RXFLEV_7 + * @retval None + */ +void SPI_ReceiveFIFOLevelConfig(SPI_Type *SPIx, uint32_t FIFOLevel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_RXFLEV(FIFOLevel)); + + tmp = SPIx->RXSTS; + tmp &= ~(SPI_RXSTS_RXFLEV | SPI_RXSTS_RXIF); + tmp |= FIFOLevel; + SPIx->RXSTS = tmp; +} + +/** + * @brief Gets transmit fifo level. + * @param SPIx:SPI1~SPI3 + * @retval Transmit fifo level. + */ +uint8_t SPI_GetTransmitFIFOLevel(SPI_Type *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->TXSTS & SPI_TXSTS_TXFFLAG); +} + +/** + * @brief Gets receive fifo level. + * @param SPIx:SPI1~SPI3 + * @retval Receive fifo level. + */ +uint8_t SPI_GetReceiveFIFOLevel(SPI_Type *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->RXSTS & SPI_RXSTS_RXFFLAG); +} + +/** + * @brief Enables or disables FIFO smart mode. + * @param SPIx:SPI1~SPI3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_SmartModeCmd(SPI_Type *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + SPIx->MISC |= SPI_MISC_SMART; + } + else + { + SPIx->MISC &= ~SPI_MISC_SMART; + } +} + +/** + * @brief Enables or disables FIFO over write mode. + * @param SPIx:SPI1~SPI3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_OverWriteModeCmd(SPI_Type *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + SPIx->MISC |= SPI_MISC_OVER; + } + else + { + SPIx->MISC &= ~SPI_MISC_OVER; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_tmr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_tmr.c new file mode 100644 index 0000000000..9c1f0e401c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_tmr.c @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file lib_tmr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Timer library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_tmr.h" + +#define TMR_CTRL_RSTValue (0UL) +#define TMR_VALUE_RSTValue (0UL) +#define TMR_RELOAD_RSTValue (0UL) + +/** + * @brief Initializes the timer peripheral registers to their default reset values. + * @param TMRx: + TMR0 ~ TMR3 + * @retval None + */ +void TMR_DeInit(TMR_Type *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + /* Disable timer */ + TMRx->CTRL &= ~TMR_CTRL_EN; + /* clear interrupt status */ + TMRx->INTSTS = TMR_INTSTS_INTSTS; + /* write default reset values */ + TMRx->CTRL = TMR_CTRL_RSTValue; + TMRx->RELOAD = TMR_RELOAD_RSTValue; + TMRx->VALUE = TMR_VALUE_RSTValue; +} + +/** + * @brief Initializes timer. + * @param TMRx: + TMR0 ~ TMR3 + InitStruct: Timer configuration. + ClockSource: + TMR_CLKSRC_INTERNAL + TMR_CLKSRC_EXTERNAL + EXTGT: + TMR_EXTGT_DISABLE + TMR_EXTGT_ENABLE + Period: the auto-reload value + * @retval None + */ +void TMR_Init(TMR_Type *TMRx, TMR_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_TMR_CLKSRC(InitStruct->ClockSource)); + assert_parameters(IS_TMR_EXTGT(InitStruct->EXTGT)); + + tmp = TMRx->CTRL; + tmp &= ~(TMR_CTRL_EXTCLK|TMR_CTRL_EXTEN); + tmp |= (InitStruct->ClockSource|InitStruct->EXTGT); + TMRx->CTRL = tmp; + TMRx->VALUE = InitStruct->Period; + TMRx->RELOAD = InitStruct->Period; +} + +/** + * @brief Fills each TMR_InitType member with its default value. + * @param InitStruct: pointer to an TMR_InitType structure which will be initialized. + * @retval None + */ +void TMR_StructInit(TMR_InitType *InitStruct) +{ + /*--------------- Reset TMR init structure parameters values ---------------*/ + /* Initialize the ClockSource member */ + InitStruct->ClockSource = TMR_CLKSRC_INTERNAL; + /* Initialize the EXTGT member */ + InitStruct->EXTGT = TMR_EXTGT_DISABLE; + /* Initialize the Period member */ + InitStruct->Period = 0; +} + +/** + * @brief Enables or disables timer interrupt. + * @param TMRx: + TMR0~TMR3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void TMR_INTConfig(TMR_Type *TMRx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + TMRx->CTRL |= TMR_CTRL_INTEN; + } + else + { + TMRx->CTRL &= ~TMR_CTRL_INTEN; + } +} + +/** + * @brief Gets timer interrupt status. + * @param TMRx: + TMR0~TMR3 + * @retval Interrupt status. + */ +uint8_t TMR_GetINTStatus(TMR_Type *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + if (TMRx->INTSTS & TMR_INTSTS_INTSTS) + return 1; + else + return 0; +} + +/** + * @brief Clears timer interrupt status bit. + * @param TMRx: + TMR0~TMR3 + * @retval None. + */ +void TMR_ClearINTStatus(TMR_Type *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + TMRx->INTSTS = TMR_INTSTS_INTSTS; +} + +/** + * @brief Enables or disables timer. + * @param TMRx: + TMR0~TMR3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void TMR_Cmd(TMR_Type *TMRx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + TMRx->CTRL |= TMR_CTRL_EN; + else + TMRx->CTRL &= ~TMR_CTRL_EN; +} + +/** + * @brief Gets timer current value. + * @param TMRx: + TMR0~TMR3 + * @retval timer value. + */ +uint32_t TMR_GetCurrentValue(TMR_Type *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + return (TMRx->VALUE); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_u32k.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_u32k.c new file mode 100644 index 0000000000..825e144d77 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_u32k.c @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file lib_u32k.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief UART 32K library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_u32k.h" + +#define U32K_STS_Msk (0x7UL) +#define U32K_CTRL0_RSTValue (0UL) +#define U32K_CTRL1_RSTValue (0UL) +#define U32K_PHASE_RSTValue (0x4B00UL) + +/** + * @brief Initializes the U32Kx peripheral registers to their default reset values. + * @param U32Kx: U32K0~U32K1 + * @retval None + */ +void U32K_DeInit(U32K_Type *U32Kx) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + + /* Disable U32K */ + U32Kx->CTRL0 &= ~U32K_CTRL0_EN; + /* clear interrupt status */ + U32Kx->STS = U32K_STS_Msk; + /* write default reset values */ + U32Kx->CTRL0 = U32K_CTRL0_RSTValue; + U32Kx->CTRL1 = U32K_CTRL1_RSTValue; + U32Kx->BAUDDIV = U32K_PHASE_RSTValue; +} + +/** + * @brief Initializes U32K. + * @param U32Kx: + U32K0~U32K1 + InitStruct: U32K configuration + Debsel: + U32K_DEBSEL_0 + U32K_DEBSEL_1 + U32K_DEBSEL_2 + U32K_DEBSEL_3 + Parity: + U32K_PARITY_EVEN + U32K_PARITY_ODD + U32K_PARITY_0 + U32K_PARITY_1 + U32K_PARITY_NONE + FirstBit: + U32K_FIRSTBIT_LSB + U32K_FIRSTBIT_MSB + AutoCal: + U32K_AUTOCAL_ON + U32K_AUTOCAL_OFF + LineSel: + U32K_LINE_RX0 + U32K_LINE_RX1 + U32K_LINE_RX2 + U32K_LINE_RX3 + Baudrate: Baudrate value, 300UL ~ 14400UL + * @retval None + */ +void U32K_Init(U32K_Type *U32Kx, U32K_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_DEBSEL(InitStruct->Debsel)); + assert_parameters(IS_U32K_PARITY(InitStruct->Parity)); + assert_parameters(IS_U32K_FIRSTBIT(InitStruct->FirstBit)); + assert_parameters(IS_U32K_AUTOCAL(InitStruct->AutoCal)); + assert_parameters(IS_U32K_LINE(InitStruct->LineSel)); + assert_parameters(IS_U32K_BAUDRATE(InitStruct->Baudrate)); + + tmp_reg1 = U32Kx->CTRL0; + tmp_reg1 &= ~(U32K_CTRL0_DEBSEL\ + |U32K_CTRL0_PMODE\ + |U32K_CTRL0_MSB\ + |U32K_CTRL0_ACOFF); + tmp_reg1 |= (InitStruct->Debsel\ + |InitStruct->Parity\ + |InitStruct->FirstBit\ + |InitStruct->AutoCal); + U32Kx->CTRL0 = tmp_reg1; + if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz + U32Kx->BAUDDIV = 65536*InitStruct->Baudrate/32768; + else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz + U32Kx->BAUDDIV = 65536*InitStruct->Baudrate/8192; + else + assert_parameters(0); + + tmp_reg2 = U32Kx->CTRL1; + tmp_reg2 &= ~(U32K_CTRL1_RXSEL); + tmp_reg2 |= (InitStruct->LineSel); + U32Kx->CTRL1 = tmp_reg2; +} + +/** + * @brief Fills each U32K_InitType member with its default value. + * @param InitStruct: pointer to an U32K_InitType structure which will be initialized. + * @retval None + */ +void U32K_StructInit(U32K_InitType *InitStruct) +{ + /*-------------- Reset U32K init structure parameters values ---------------*/ + /* Initialize the AutoCal member */ + InitStruct->AutoCal = U32K_AUTOCAL_ON; + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the Debsel member */ + InitStruct->Debsel = U32K_DEBSEL_0; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = U32K_FIRSTBIT_LSB; + /* Initialize the LineSel member */ + InitStruct->LineSel = U32K_LINE_RX0; + /* Initialize the Parity member */ + InitStruct->Parity = U32K_PARITY_NONE; +} + +/** + * @brief Enables or disables U32K interrupt. + * @param U32Kx: + U32K0~U32K1 + INTMask: can use the '|' operator + U32K_INT_RXOV + U32K_INT_RXPE + U32K_INT_RX + NewState: + ENABLE + DISABLE + * @retval None + */ +void U32K_INTConfig(U32K_Type *U32Kx, uint32_t INTMask, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = U32Kx->CTRL1; + tmp &= ~INTMask; + if (NewState == ENABLE) + { + tmp |= INTMask; + } + U32Kx->CTRL1 = tmp; +} + +/** + * @brief Gets interrupt flag status. + * @param U32Kx: + U32K0~U32K1 + INTMask: + U32K_INTSTS_RXOV + U32K_INTSTS_RXPE + U32K_INTSTS_RX + * @retval Flag status + */ +uint8_t U32K_GetINTStatus(U32K_Type *U32Kx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INTFLAGR(INTMask)); + + if (U32Kx->STS&INTMask) + return 1; + else + return 0; +} + +/** + * @brief Clears flag status. + * @param U32Kx: + U32K0~U32K1 + INTMask: can use the '|' operator + U32K_INTSTS_RXOV + U32K_INTSTS_RXPE + U32K_INTSTS_RX + * @retval None + */ +void U32K_ClearINTStatus(U32K_Type *U32Kx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INTFLAGC(INTMask)); + + U32Kx->STS = INTMask; +} + +/** + * @brief Reads receive data register. + * @param U32Kx: + U32K0~U32K1 + * @retval Receive data value + */ +uint8_t U32K_ReceiveData(U32K_Type *U32Kx) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + + return (U32Kx->DATA); +} + +/** + * @brief Configures U32K baudrate. + * @param U32Kx: U32K0~U32K1 + BaudRate: Baudrate value + * @retval None + */ +void U32K_BaudrateConfig(U32K_Type *U32Kx, uint32_t BaudRate) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_BAUDRATE(BaudRate)); + + if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz + U32Kx->BAUDDIV = 65536*BaudRate/32768; + else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz + U32Kx->BAUDDIV = 65536*BaudRate/8192; + else + assert_parameters(0); +} + +/** + * @brief Enables or disables U32K controlller. + * @param U32Kx: + U32K0~U32K1 + NewState: + ENABLE + DISABLE + * @retval None + */ +void U32K_Cmd(U32K_Type *U32Kx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = U32Kx->CTRL0; + tmp &= ~(U32K_CTRL0_EN); + if (NewState == ENABLE) + { + tmp |= U32K_CTRL0_EN; + } + U32Kx->CTRL0 = tmp; +} + +/** + * @brief Configures U32K receive line. + * @param U32Kx: + U32K0~U32K1 + Line: + U32K_LINE_RX0 + U32K_LINE_RX1 + U32K_LINE_RX2 + U32K_LINE_RX3 + * @retval None + */ +void U32K_LineConfig(U32K_Type *U32Kx, uint32_t Line) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_LINE(Line)); + + tmp = U32Kx->CTRL1; + tmp &= ~U32K_CTRL1_RXSEL_Msk; + tmp |= Line; + + U32Kx->CTRL1 = tmp; +} + +/** + * @brief Configures Wake-up mode. + * @param U32Kx: + U32K0~U32K1 + WKUMode: + U32K_WKUMOD_RX + U32K_WKUMOD_PC + * @retval None + */ +void U32K_WKUModeConfig(U32K_Type *U32Kx, uint32_t WKUMode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_WKUMODE(WKUMode)); + + tmp = U32Kx->CTRL0; + tmp &= ~U32K_CTRL0_WKUMODE_Msk; + tmp |= WKUMode; + U32Kx->CTRL0 = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_uart.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_uart.c new file mode 100644 index 0000000000..3af83facdc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_uart.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file lib_uart.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief UART library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_uart.h" +#include "lib_clk.h" + +#define UART_STATE_RCMsk (0xBCUL) +#define UART_INTSTS_RCMsk (0x3FUL) +#define UART_BAUDDIV_RSTValue (0UL) +#define UART_CTRL_RSTValue (0UL) +#define UART_CTRL2_RSTValue (0UL) + +/** + * @brief Iinitializes the UARTx peripheral registers to their default reset + values. + * @param UARTx: UART0~UART5 + * @retval None + */ +void UART_DeInit(UART_Type *UARTx) +{ + __IO uint32_t dummy_data = 0UL; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + /* read data, clear RXFULL flag */ + dummy_data = UARTx->DATA; + dummy_data += 1; + + UARTx->INTSTS = UART_INTSTS_RCMsk; + UARTx->STATE = UART_STATE_RCMsk; + UARTx->BAUDDIV = UART_BAUDDIV_RSTValue; + UARTx->CTRL2 = UART_CTRL2_RSTValue; + UARTx->CTRL = UART_CTRL_RSTValue; +} + +/** + * @brief Iinitializes UART. + * @param UARTx: UART0~UART5 + InitStruct:UART configuration. + Mode: (between UART_MODE_RX and UART_MODE_TX, can use the '|' operator) + UART_MODE_RX + UART_MODE_TX + UART_MODE_OFF + Parity: + UART_PARITY_EVEN + UART_PARITY_ODD + UART_PARITY_0 + UART_PARITY_1 + UART_PARITY_NONE + FirstBit: + UART_FIRSTBIT_LSB + UART_FIRSTBIT_MSB + Baudrate: Baudrate value, 300UL ~ 819200UL + * @retval None + */ +void UART_Init(UART_Type *UARTx, UART_InitType *InitStruct) +{ + uint32_t pclk; + uint32_t div; + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_MODE(InitStruct->Mode)); + assert_parameters(IS_UART_PARITY(InitStruct->Parity)); + assert_parameters(IS_UART_FIRSTBIT(InitStruct->FirstBit)); + assert_parameters(IS_UART_BAUDRATE(InitStruct->Baudrate)); + + tmp_reg1 = UARTx->CTRL; + tmp_reg1 &= ~(UART_CTRL_RXEN_Msk\ + |UART_CTRL_TXEN_Msk); + tmp_reg1 |= (InitStruct->Mode); + + tmp_reg2 = UARTx->CTRL2; + tmp_reg2 &= ~(UART_CTRL2_MSB_Msk \ + |UART_CTRL2_PMODE_Msk); + tmp_reg2 |= (InitStruct->Parity\ + |InitStruct->FirstBit); + UARTx->CTRL2 = tmp_reg2; + + pclk = CLK_GetPCLKFreq(); + div = pclk/InitStruct->Baudrate; + + if ((pclk%InitStruct->Baudrate) > (InitStruct->Baudrate/2)) + { + div++; + } + + UARTx->BAUDDIV = div; + UARTx->CTRL = tmp_reg1; +} + +/** + * @brief Fills each UART_InitType member with its default value. + * @param InitStruct: pointer to an UART_InitType structure which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitType *InitStruct) +{ + /*-------------- Reset UART init structure parameters values ---------------*/ + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = UART_FIRSTBIT_LSB; + /* Initialize the Mode member */ + InitStruct->Mode = UART_MODE_OFF; + /* Initialize the Parity member */ + InitStruct->Parity = UART_PARITY_NONE; +} + +/** + * @brief Gets peripheral flag. + * @param UARTx: UART0~UART5 + FlagMask: flag to get. + --UART_FLAG_DMATXDONE + --UART_FLAG_RXPARITY + --UART_FLAG_TXDONE + --UART_FLAG_RXPE + --UART_FLAG_RXOV + --UART_FLAG_TXOV + --UART_FLAG_RXFULL + * @retval 1:flag set + 0:flag reset + */ +uint8_t UART_GetFlag(UART_Type *UARTx, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_FLAGR(FlagMask)); + + if (UARTx->STATE&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears peripheral flag. + * @param UARTx: UART0~UART5 + FlagMask: status to clear, can use the '|' operator. + --UART_FLAG_DMATXDONE + --UART_FLAG_TXDONE + --UART_FLAG_RXPE + --UART_FLAG_RXOV + --UART_FLAG_TXOV + * @retval None + */ +void UART_ClearFlag(UART_Type *UARTx, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_FLAGC(FlagMask)); + + UARTx->STATE = FlagMask; +} + +/** + * @brief Enables or disables the specified UART interrupts. + * @param UARTx: UART0~UART5 + INTMask: can use the '|' operator. + --UART_INT_TXDONE + --UART_INT_RXPE + --UART_INT_RXOV + --UART_INT_TXOV + --UART_INT_RX + NewState:New status of interrupt mask. + * @retval None + */ +void UART_INTConfig(UART_Type *UARTx, uint32_t INTMask, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->CTRL |= INTMask; + } + else + { + UARTx->CTRL &= ~INTMask; + } +} + +/** + * @brief Gets interrupt status. + * @param UARTx: UART0~UART5 + INTMask: status to get. + --UART_INTSTS_TXDONE + --UART_INTSTS_RXPE + --UART_INTSTS_RXOV + --UART_INTSTS_TXOV + --UART_INTSTS_RX + * @retval 1:status set + 0:status reset + */ +uint8_t UART_GetINTStatus(UART_Type *UARTx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INTFLAGR(INTMask)); + + if (UARTx->INTSTS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clears interrupt status. + * @param UARTx: UART0~UART5 + INTMask: status to clear, can use the '|' operator. + --UART_INTSTS_TXDONE + --UART_INTSTS_RXPE + --UART_INTSTS_RXOV + --UART_INTSTS_TXOV + --UART_INTSTS_RX + * @retval None + */ +void UART_ClearINTStatus(UART_Type *UARTx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INTFLAGC(INTMask)); + + UARTx->INTSTS = INTMask; +} + +/** + * @brief Loads send data register. + * @param UARTx: UART0~USART5 + ch: data to send. + * @retval None + */ +void UART_SendData(UART_Type *UARTx, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + UARTx->DATA = ch; +} + +/** + * @brief Reads receive data register. + * @param UARTx: UART0~UART5 + * @retval The received data. + */ +uint8_t UART_ReceiveData(UART_Type *UARTx) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + return UARTx->DATA; +} + +/** + * @brief Configures UART baudrate. + * @param UARTx: UART0~UART5 + BaudRate: Baudrate value + * @retval None + */ +void UART_BaudrateConfig(UART_Type *UARTx, uint32_t BaudRate) +{ + uint32_t pclk; + uint32_t div; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_BAUDRATE(BaudRate)); + + pclk = CLK_GetPCLKFreq(); + div = pclk/BaudRate; + if ((pclk%BaudRate) > (BaudRate/2)) + { + div++; + } + + UARTx->BAUDDIV = div; +} + +/** + * @brief Enables or disables UART Transmitter/Receiver. + * @param UARTx: UART0~UART5 + Mode: + UART_MODE_RX + UART_MODE_TX + NewState: + ENABLE + DISABLE + * @retval None + */ +void UART_Cmd(UART_Type *UARTx, uint32_t Mode, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_MODE(Mode)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->CTRL |= Mode; + } + else + { + UARTx->CTRL &= ~Mode; + } +} + +/** + * @brief Gets UART configure information. + * @param[in] UARTx: UART0~UART5 + * @param[out] ConfigInfo: The pointer of UART configuration. + * @retval None + */ +void UART_GetConfigINFO(UART_Type *UARTx, UART_ConfigINFOType *ConfigInfo) +{ + uint32_t tmp1, tmp2, tmp3; + uint32_t pclk; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + tmp1 = UARTx->CTRL; + tmp2 = UARTx->BAUDDIV; + pclk = CLK_GetPCLKFreq(); + tmp3 = UARTx->CTRL2; + + /* Mode_Transmit */ + if (tmp1 & UART_CTRL_TXEN_Msk) + ConfigInfo->Mode_Transmit = 1; + else + ConfigInfo->Mode_Transmit = 0; + + /* Mode_Receive */ + if (tmp1 & UART_CTRL_RXEN_Msk) + ConfigInfo->Mode_Receive = 1; + else + ConfigInfo->Mode_Receive = 0; + + /* Baudrate */ + ConfigInfo->Baudrate = pclk / tmp2; + + /* LSB/MSB */ + if (tmp3 & UART_CTRL2_MSB_Msk) + ConfigInfo->FirstBit = 1; + else + ConfigInfo->FirstBit = 0; + + /* Parity */ + ConfigInfo->Parity = (tmp3 & UART_CTRL2_PMODE) >> UART_CTRL2_PMODE_Pos; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_version.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_version.c new file mode 100644 index 0000000000..2c723f6262 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_version.c @@ -0,0 +1,25 @@ +/** +******************************************************************************* + * @file lib_version.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Version library. +*******************************************************************************/ +#include "lib_version.h" + +#define Target_DriveVersion DRIVER_VERSION(1, 1) + +/** + * @brief Gets Target driver's current version. + * @param None + * @retval Version value + * Bit[15:8] : Major version + * Bit[7:0] : Minor version + */ +uint16_t Target_GetDriveVersion(void) +{ + return (Target_DriveVersion); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_wdt.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_wdt.c new file mode 100644 index 0000000000..00e47707be --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Libraries/Lib_Driver/src/lib_wdt.c @@ -0,0 +1,88 @@ +/** + ****************************************************************************** + * @file lib_wdt.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief WDT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_wdt.h" + +#define WDTPASS_KEY 0xAA5555AA +#define WDTCLR_KEY 0x55AAAA55 + +/** + * @brief Enables WDT timer. + * @param None + * @retval None + */ +void WDT_Enable(void) +{ + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN |= PMU_WDTEN_WDTEN; + + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN |= PMU_WDTEN_WDTEN; +} + +/** + * @brief Disables WDT timer. + * @param None + * @retval None + */ +void WDT_Disable(void) +{ + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN &= ~PMU_WDTEN_WDTEN; + + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN &= ~PMU_WDTEN_WDTEN; +} + +/** + * @brief Clears WDT counter. + * @param None + * @retval None + */ +void WDT_Clear(void) +{ + PMU->WDTCLR = WDTCLR_KEY; +} + +/** + * @brief Configures WDT counting period. + * @param counting period: + WDT_2_SECS + WDT_4_SECS + WDT_8_SECS + WDT_16_SECS + * @retval None + */ +void WDT_SetPeriod(uint32_t period) +{ + uint32_t tmp; + + assert_parameters(IS_WDT_PERIOD(period)); + + tmp = PMU->WDTEN; + tmp &= ~PMU_WDTEN_WDTSEL; + tmp |= period; + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN = tmp; +} + +/** + * @brief Gets WDT counter value. + * @param None + * @retval current counter value. + */ +uint16_t WDT_GetCounterValue(void) +{ + return (PMU->WDTCLR & PMU_WDTCLR_WDTCNT); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/startup_target.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/.cproject b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/.cproject new file mode 100644 index 0000000000..729d189d6e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/.cproject @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/.project b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/.project new file mode 100644 index 0000000000..15dc954977 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/.project @@ -0,0 +1,183 @@ + + + template + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Startup_System/startup_target.S + 1 + PARENT-1-PROJECT_LOC/startup_target.S + + + Startup_System/system_target.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/system_target.c + + + User/lib_conf.h + 1 + PARENT-2-PROJECT_LOC/Inc/lib_conf.h + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/Src/main.c + + + User/target_isr.c + 1 + PARENT-2-PROJECT_LOC/Src/target_isr.c + + + User/v_stdio.c + 1 + PARENT-2-PROJECT_LOC/Src/v_stdio.c + + + StdDrivers/Device/lib_CodeRAM.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_CodeRAM.c + + + StdDrivers/Device/lib_LoadNVR.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_LoadNVR.c + + + StdDrivers/Device/lib_cortex.c + 1 + PARENT-5-PROJECT_LOC/Libraries/CMSIS/device/lib_cortex.c + + + StdDrivers/Drivers/lib_adc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc.c + + + StdDrivers/Drivers/lib_adc_tiny.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_adc_tiny.c + + + StdDrivers/Drivers/lib_ana.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_ana.c + + + StdDrivers/Drivers/lib_clk.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_clk.c + + + StdDrivers/Drivers/lib_cmp.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_cmp.c + + + StdDrivers/Drivers/lib_crypt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_crypt.c + + + StdDrivers/Drivers/lib_dma.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_dma.c + + + StdDrivers/Drivers/lib_flash.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_flash.c + + + StdDrivers/Drivers/lib_gpio.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_gpio.c + + + StdDrivers/Drivers/lib_i2c.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_i2c.c + + + StdDrivers/Drivers/lib_iso7816.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_iso7816.c + + + StdDrivers/Drivers/lib_lcd.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_lcd.c + + + StdDrivers/Drivers/lib_misc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_misc.c + + + StdDrivers/Drivers/lib_pmu.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pmu.c + + + StdDrivers/Drivers/lib_pwm.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_pwm.c + + + StdDrivers/Drivers/lib_rtc.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_rtc.c + + + StdDrivers/Drivers/lib_spi.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_spi.c + + + StdDrivers/Drivers/lib_tmr.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_tmr.c + + + StdDrivers/Drivers/lib_u32k.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_u32k.c + + + StdDrivers/Drivers/lib_uart.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_uart.c + + + StdDrivers/Drivers/lib_version.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_version.c + + + StdDrivers/Drivers/lib_wdt.c + 1 + PARENT-5-PROJECT_LOC/Libraries/Lib_Driver/src/lib_wdt.c + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/Target_FLASH.ld b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/Target_FLASH.ld new file mode 100644 index 0000000000..0febb1b7dc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/ECLIPSE/template/Target_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 512Byte FLASH, 64KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-10-28 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20010000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* VMA, Virtual Memory Address*/ + /* LMA, Load Memeory Address, address that the section stores, and TO BE LOAD to VMA before it is executed or accessed */ + + .ram_exec : + { + . = ALIGN(4); + KEEP( *(.ram_exec)) + . = ALIGN(4); + } > RAM AT> FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/board.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/board.c new file mode 100644 index 0000000000..55d92f951f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/board.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-07-24 Tanek the first version + * 2018-11-12 Ernest Chen modify copyright + */ + +#include +#include +#include + +#define _SCB_BASE (0xE000E010UL) +#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0)) +#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4)) +#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8)) +#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC)) +#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL)) + +// Updates the variable SystemCoreClock and must be called +// whenever the core clock is changed during program execution. +extern void SystemCoreClockUpdate(void); + +// Holds the system core clock, which is the system clock +// frequency supplied to the SysTick timer and the processor +// core clock. +extern uint32_t SystemCoreClock; + +static uint32_t _SysTick_Config(rt_uint32_t ticks) +{ + if ((ticks - 1) > 0xFFFFFF) + { + return 1; + } + + _SYSTICK_LOAD = ticks - 1; + _SYSTICK_PRI = 0xFF; + _SYSTICK_VAL = 0; + _SYSTICK_CTRL = 0x07; + + return 0; +} + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +#define RT_HEAP_SIZE 1024 +static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4) +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +/** + * This function will initial your board. + */ +void rt_hw_board_init() +{ + /* System Clock Update */ + SystemCoreClockUpdate(); + + /* System Tick Configuration */ + _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_dirent.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_dirent.h new file mode 100644 index 0000000000..c3a19878ec --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_dirent.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef LIBC_DIRENT_H__ +#define LIBC_DIRENT_H__ + +#define DT_UNKNOWN 0x00 +#define DT_REG 0x01 +#define DT_DIR 0x02 + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_errno.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_errno.h new file mode 100644 index 0000000000..0f3bc7635a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_errno.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-11-12 Bernard The first version + */ + +#ifndef LIBC_ERRNO_H__ +#define LIBC_ERRNO_H__ + +#include + +#if defined(RT_USING_NEWLIB) || defined(_WIN32) +/* use errno.h file in toolchains */ +#include +#endif + +#if defined(__CC_ARM) +/* +defined in armcc/errno.h + +#define EDOM 1 +#define ERANGE 2 +#define EILSEQ 4 +#define ESIGNUM 3 +#define EINVAL 5 +#define ENOMEM 6 +*/ +#define ERROR_BASE_NO 7 + +#elif defined(__IAR_SYSTEMS_ICC__) +/* defined in iar/errno.h +#define EDOM 33 +#define ERANGE 34 +#define EFPOS 35 +#define EILSEQ 36 +*/ +#define ERROR_BASE_NO 36 + +#else + +#define ERROR_BASE_NO 0 +#endif + +#if !defined(RT_USING_NEWLIB) && !defined(_WIN32) + +#define EPERM (ERROR_BASE_NO + 1) +#define ENOENT (ERROR_BASE_NO + 2) +#define ESRCH (ERROR_BASE_NO + 3) +#define EINTR (ERROR_BASE_NO + 4) +#define EIO (ERROR_BASE_NO + 5) +#define ENXIO (ERROR_BASE_NO + 6) +#define E2BIG (ERROR_BASE_NO + 7) +#define ENOEXEC (ERROR_BASE_NO + 8) +#define EBADF (ERROR_BASE_NO + 9) +#define ECHILD (ERROR_BASE_NO + 10) +#define EAGAIN (ERROR_BASE_NO + 11) + +#ifndef ENOMEM +#define ENOMEM (ERROR_BASE_NO + 12) +#endif + +#define EACCES (ERROR_BASE_NO + 13) +#define EFAULT (ERROR_BASE_NO + 14) +#define ENOTBLK (ERROR_BASE_NO + 15) +#define EBUSY (ERROR_BASE_NO + 16) +#define EEXIST (ERROR_BASE_NO + 17) +#define EXDEV (ERROR_BASE_NO + 18) +#define ENODEV (ERROR_BASE_NO + 19) +#define ENOTDIR (ERROR_BASE_NO + 20) +#define EISDIR (ERROR_BASE_NO + 21) + +#ifndef EINVAL +#define EINVAL (ERROR_BASE_NO + 22) +#endif + +#define ENFILE (ERROR_BASE_NO + 23) +#define EMFILE (ERROR_BASE_NO + 24) +#define ENOTTY (ERROR_BASE_NO + 25) +#define ETXTBSY (ERROR_BASE_NO + 26) +#define EFBIG (ERROR_BASE_NO + 27) +#define ENOSPC (ERROR_BASE_NO + 28) +#define ESPIPE (ERROR_BASE_NO + 29) +#define EROFS (ERROR_BASE_NO + 30) +#define EMLINK (ERROR_BASE_NO + 31) +#define EPIPE (ERROR_BASE_NO + 32) + +#ifndef EDOM +#define EDOM (ERROR_BASE_NO + 33) +#endif + +#ifndef ERANGE +#define ERANGE (ERROR_BASE_NO + 34) +#endif + +#define EDEADLK (ERROR_BASE_NO + 35) +#define ENAMETOOLONG (ERROR_BASE_NO + 36) +#define ENOLCK (ERROR_BASE_NO + 37) +#define ENOSYS (ERROR_BASE_NO + 38) +#define ENOTEMPTY (ERROR_BASE_NO + 39) +#define ELOOP (ERROR_BASE_NO + 40) +#define EWOULDBLOCK EAGAIN +#define ENOMSG (ERROR_BASE_NO + 42) +#define EIDRM (ERROR_BASE_NO + 43) +#define ECHRNG (ERROR_BASE_NO + 44) +#define EL2NSYNC (ERROR_BASE_NO + 45) +#define EL3HLT (ERROR_BASE_NO + 46) +#define EL3RST (ERROR_BASE_NO + 47) +#define ELNRNG (ERROR_BASE_NO + 48) +#define EUNATCH (ERROR_BASE_NO + 49) +#define ENOCSI (ERROR_BASE_NO + 50) +#define EL2HLT (ERROR_BASE_NO + 51) +#define EBADE (ERROR_BASE_NO + 52) +#define EBADR (ERROR_BASE_NO + 53) +#define EXFULL (ERROR_BASE_NO + 54) +#define ENOANO (ERROR_BASE_NO + 55) +#define EBADRQC (ERROR_BASE_NO + 56) +#define EBADSLT (ERROR_BASE_NO + 57) +#define EDEADLOCK EDEADLK +#define EBFONT (ERROR_BASE_NO + 59) +#define ENOSTR (ERROR_BASE_NO + 60) +#define ENODATA (ERROR_BASE_NO + 61) +#define ETIME (ERROR_BASE_NO + 62) +#define ENOSR (ERROR_BASE_NO + 63) +#define ENONET (ERROR_BASE_NO + 64) +#define ENOPKG (ERROR_BASE_NO + 65) +#define EREMOTE (ERROR_BASE_NO + 66) +#define ENOLINK (ERROR_BASE_NO + 67) +#define EADV (ERROR_BASE_NO + 68) +#define ESRMNT (ERROR_BASE_NO + 69) +#define ECOMM (ERROR_BASE_NO + 70) +#define EPROTO (ERROR_BASE_NO + 71) +#define EMULTIHOP (ERROR_BASE_NO + 72) +#define EDOTDOT (ERROR_BASE_NO + 73) +#define EBADMSG (ERROR_BASE_NO + 74) +#define EOVERFLOW (ERROR_BASE_NO + 75) +#define ENOTUNIQ (ERROR_BASE_NO + 76) +#define EBADFD (ERROR_BASE_NO + 77) +#define EREMCHG (ERROR_BASE_NO + 78) +#define ELIBACC (ERROR_BASE_NO + 79) +#define ELIBBAD (ERROR_BASE_NO + 80) +#define ELIBSCN (ERROR_BASE_NO + 81) +#define ELIBMAX (ERROR_BASE_NO + 82) +#define ELIBEXEC (ERROR_BASE_NO + 83) + +#ifndef EILSEQ +#define EILSEQ (ERROR_BASE_NO + 84) +#endif + +#define ERESTART (ERROR_BASE_NO + 85) +#define ESTRPIPE (ERROR_BASE_NO + 86) +#define EUSERS (ERROR_BASE_NO + 87) +#define ENOTSOCK (ERROR_BASE_NO + 88) +#define EDESTADDRREQ (ERROR_BASE_NO + 89) +#define EMSGSIZE (ERROR_BASE_NO + 90) +#define EPROTOTYPE (ERROR_BASE_NO + 91) +#define ENOPROTOOPT (ERROR_BASE_NO + 92) +#define EPROTONOSUPPORT (ERROR_BASE_NO + 93) +#define ESOCKTNOSUPPORT (ERROR_BASE_NO + 94) +#define EOPNOTSUPP (ERROR_BASE_NO + 95) +#define ENOTSUP EOPNOTSUPP +#define EPFNOSUPPORT (ERROR_BASE_NO + 96) +#define EAFNOSUPPORT (ERROR_BASE_NO + 97) +#define EADDRINUSE (ERROR_BASE_NO + 98) +#define EADDRNOTAVAIL (ERROR_BASE_NO + 99) +#define ENETDOWN (ERROR_BASE_NO + 100) +#define ENETUNREACH (ERROR_BASE_NO + 101) +#define ENETRESET (ERROR_BASE_NO + 102) +#define ECONNABORTED (ERROR_BASE_NO + 103) +#define ECONNRESET (ERROR_BASE_NO + 104) +#define ENOBUFS (ERROR_BASE_NO + 105) +#define EISCONN (ERROR_BASE_NO + 106) +#define ENOTCONN (ERROR_BASE_NO + 107) +#define ESHUTDOWN (ERROR_BASE_NO + 108) +#define ETOOMANYREFS (ERROR_BASE_NO + 109) +#define ETIMEDOUT (ERROR_BASE_NO + 110) +#define ECONNREFUSED (ERROR_BASE_NO + 111) +#define EHOSTDOWN (ERROR_BASE_NO + 112) +#define EHOSTUNREACH (ERROR_BASE_NO + 113) +#define EALREADY (ERROR_BASE_NO + 114) +#define EINPROGRESS (ERROR_BASE_NO + 115) +#define ESTALE (ERROR_BASE_NO + 116) +#define EUCLEAN (ERROR_BASE_NO + 117) +#define ENOTNAM (ERROR_BASE_NO + 118) +#define ENAVAIL (ERROR_BASE_NO + 119) +#define EISNAM (ERROR_BASE_NO + 120) +#define EREMOTEIO (ERROR_BASE_NO + 121) +#define EDQUOT (ERROR_BASE_NO + 122) +#define ENOMEDIUM (ERROR_BASE_NO + 123) +#define EMEDIUMTYPE (ERROR_BASE_NO + 124) +#define ECANCELED (ERROR_BASE_NO + 125) +#define ENOKEY (ERROR_BASE_NO + 126) +#define EKEYEXPIRED (ERROR_BASE_NO + 127) +#define EKEYREVOKED (ERROR_BASE_NO + 128) +#define EKEYREJECTED (ERROR_BASE_NO + 129) +#define EOWNERDEAD (ERROR_BASE_NO + 130) +#define ENOTRECOVERABLE (ERROR_BASE_NO + 131) +#define ERFKILL (ERROR_BASE_NO + 132) +#define EHWPOISON (ERROR_BASE_NO + 133) + +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_fcntl.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_fcntl.h new file mode 100644 index 0000000000..1b7c69b1f4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_fcntl.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * File : libc_fcntl.h + * + * Change Logs: + * Date Author Notes + * 2018-02-07 Bernard Add O_DIRECTORY definition in NEWLIB mode. + * 2018-02-09 Bernard Add O_BINARY definition + */ + +#ifndef LIBC_FCNTL_H__ +#define LIBC_FCNTL_H__ + +#if defined(RT_USING_NEWLIB) || defined(_WIN32) +#include + +#ifndef O_NONBLOCK +#define O_NONBLOCK 0x4000 +#endif + +#if defined(_WIN32) +#define O_ACCMODE (_O_RDONLY | _O_WRONLY | _O_RDWR) +#endif + +#ifndef F_GETFL +#define F_GETFL 3 +#endif +#ifndef F_SETFL +#define F_SETFL 4 +#endif + +#ifndef O_DIRECTORY +#define O_DIRECTORY 0x200000 +#endif + +#ifndef O_BINARY +#ifdef _O_BINARY +#define O_BINARY _O_BINARY +#else +#define O_BINARY 0 +#endif +#endif + +#else +#define O_RDONLY 00 +#define O_WRONLY 01 +#define O_RDWR 02 + +#define O_CREAT 0100 +#define O_EXCL 0200 +#define O_NOCTTY 0400 +#define O_TRUNC 01000 +#define O_APPEND 02000 +#define O_NONBLOCK 04000 +#define O_DSYNC 010000 +#define O_SYNC 04010000 +#define O_RSYNC 04010000 +#define O_BINARY 0100000 +#define O_DIRECTORY 0200000 +#define O_NOFOLLOW 0400000 +#define O_CLOEXEC 02000000 + +#define O_ASYNC 020000 +#define O_DIRECT 040000 +#define O_LARGEFILE 0100000 +#define O_NOATIME 01000000 +#define O_PATH 010000000 +#define O_TMPFILE 020200000 +#define O_NDELAY O_NONBLOCK + +#define O_SEARCH O_PATH +#define O_EXEC O_PATH + +#define O_ACCMODE (03|O_SEARCH) + +#define F_DUPFD 0 +#define F_GETFD 1 +#define F_SETFD 2 +#define F_GETFL 3 +#define F_SETFL 4 + +#define F_SETOWN 8 +#define F_GETOWN 9 +#define F_SETSIG 10 +#define F_GETSIG 11 + +#define F_GETLK 12 +#define F_SETLK 13 +#define F_SETLKW 14 + +#define F_SETOWN_EX 15 +#define F_GETOWN_EX 16 + +#define F_GETOWNER_UIDS 17 +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_fdset.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_fdset.h new file mode 100644 index 0000000000..ecd965cd22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_fdset.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * File : libc_errno.h + * + * Change Logs: + * Date Author Notes + * 2017-10-30 Bernard The first version + */ + +#ifndef LIBC_FDSET_H__ +#define LIBC_FDSET_H__ + +#include + +#if defined(RT_USING_NEWLIB) || defined(_WIN32) +#include +#if defined(HAVE_SYS_SELECT_H) +#include +#endif + +#else + +#ifdef SAL_USING_POSIX + +#ifdef FD_SETSIZE +#undef FD_SETSIZE +#endif + +#define FD_SETSIZE DFS_FD_MAX +#endif + +# ifndef FD_SETSIZE +# define FD_SETSIZE 32 +# endif + +# define NBBY 8 /* number of bits in a byte */ + +typedef long fd_mask; +# define NFDBITS (sizeof (fd_mask) * NBBY) /* bits per mask */ +# ifndef howmany +# define howmany(x,y) (((x)+((y)-1))/(y)) +# endif + +/* We use a macro for fd_set so that including Sockets.h afterwards + can work. */ +typedef struct _types_fd_set { + fd_mask fds_bits[howmany(FD_SETSIZE, NFDBITS)]; +} _types_fd_set; + +#define fd_set _types_fd_set + +# define FD_SET(n, p) ((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS))) +# define FD_CLR(n, p) ((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS))) +# define FD_ISSET(n, p) ((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS))) +# define FD_ZERO(p) memset((void*)(p), 0, sizeof(*(p))) + +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_ioctl.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_ioctl.h new file mode 100644 index 0000000000..ef5a5257a8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_ioctl.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * File : libc_ioctl.h + * + * Change Logs: + * Date Author Notes + * 2017-01-21 Bernard the first version + */ + +#ifndef LIBC_IOCTL_H__ +#define LIBC_IOCTL_H__ + +#define _IOC(a,b,c,d) ( ((a)<<30) | ((b)<<8) | (c) | ((d)<<16) ) +#define _IOC_NONE 0U +#define _IOC_WRITE 1U +#define _IOC_READ 2U + +#ifndef _WIN32 +#define _IO(a,b) _IOC(_IOC_NONE,(a),(b),0) +#define _IOW(a,b,c) _IOC(_IOC_WRITE,(a),(b),sizeof(c)) +#define _IOR(a,b,c) _IOC(_IOC_READ,(a),(b),sizeof(c)) +#define _IOWR(a,b,c) _IOC(_IOC_READ|_IOC_WRITE,(a),(b),sizeof(c)) + +#define FIONREAD _IOR('f', 127, int) /* get # bytes to read */ +#define FIONBIO _IOW('f', 126, int) /* set/clear non-blocking i/o */ +#define FIONWRITE _IOR('f', 121, int) /* get # bytes outstanding + * in send queue. */ +#endif + +#define TCGETS 0x5401 +#define TCSETS 0x5402 +#define TCSETSW 0x5403 +#define TCSETSF 0x5404 +#define TCGETA 0x5405 +#define TCSETA 0x5406 +#define TCSETAW 0x5407 +#define TCSETAF 0x5408 +#define TCSBRK 0x5409 +#define TCXONC 0x540A +#define TCFLSH 0x540B +#define TIOCEXCL 0x540C +#define TIOCNXCL 0x540D +#define TIOCSCTTY 0x540E +#define TIOCGPGRP 0x540F +#define TIOCSPGRP 0x5410 +#define TIOCOUTQ 0x5411 +#define TIOCSTI 0x5412 +#define TIOCGWINSZ 0x5413 +#define TIOCSWINSZ 0x5414 +#define TIOCMGET 0x5415 +#define TIOCMBIS 0x5416 +#define TIOCMBIC 0x5417 +#define TIOCMSET 0x5418 +#define TIOCGSOFTCAR 0x5419 +#define TIOCSSOFTCAR 0x541A +// #define FIONREAD 0x541B +#define TIOCINQ FIONREAD +#define TIOCLINUX 0x541C +#define TIOCCONS 0x541D +#define TIOCGSERIAL 0x541E +#define TIOCSSERIAL 0x541F +#define TIOCPKT 0x5420 +// #define FIONBIO 0x5421 +#define TIOCNOTTY 0x5422 +#define TIOCSETD 0x5423 +#define TIOCGETD 0x5424 +#define TCSBRKP 0x5425 +#define TIOCSBRK 0x5427 +#define TIOCCBRK 0x5428 +#define TIOCGSID 0x5429 +#define TIOCGRS485 0x542E +#define TIOCSRS485 0x542F +#define TIOCGPTN 0x80045430 +#define TIOCSPTLCK 0x40045431 +#define TIOCGDEV 0x80045432 +#define TCGETX 0x5432 +#define TCSETX 0x5433 +#define TCSETXF 0x5434 +#define TCSETXW 0x5435 +#define TIOCSIG 0x40045436 +#define TIOCVHANGUP 0x5437 +#define TIOCGPKT 0x80045438 +#define TIOCGPTLCK 0x80045439 +#define TIOCGEXCL 0x80045440 + +#define FIONCLEX 0x5450 +#define FIOCLEX 0x5451 + +#ifndef _WIN32 +#define FIOASYNC 0x5452 +#endif + +#define TIOCSERCONFIG 0x5453 +#define TIOCSERGWILD 0x5454 +#define TIOCSERSWILD 0x5455 +#define TIOCGLCKTRMIOS 0x5456 +#define TIOCSLCKTRMIOS 0x5457 +#define TIOCSERGSTRUCT 0x5458 +#define TIOCSERGETLSR 0x5459 +#define TIOCSERGETMULTI 0x545A +#define TIOCSERSETMULTI 0x545B + +#define TIOCMIWAIT 0x545C +#define TIOCGICOUNT 0x545D +#define FIOQSIZE 0x5460 + +#define TIOCPKT_DATA 0 +#define TIOCPKT_FLUSHREAD 1 +#define TIOCPKT_FLUSHWRITE 2 +#define TIOCPKT_STOP 4 +#define TIOCPKT_START 8 +#define TIOCPKT_NOSTOP 16 +#define TIOCPKT_DOSTOP 32 +#define TIOCPKT_IOCTL 64 + +#define TIOCSER_TEMT 0x01 + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +#define N_TTY 0 +#define N_SLIP 1 +#define N_MOUSE 2 +#define N_PPP 3 +#define N_STRIP 4 +#define N_AX25 5 +#define N_X25 6 +#define N_6PACK 7 +#define N_MASC 8 +#define N_R3964 9 +#define N_PROFIBUS_FDL 10 +#define N_IRDA 11 +#define N_SMSBLOCK 12 +#define N_HDLC 13 +#define N_SYNC_PPP 14 +#define N_HCI 15 + +#define FIOSETOWN 0x8901 +#define SIOCSPGRP 0x8902 +#define FIOGETOWN 0x8903 +#define SIOCGPGRP 0x8904 +// #define SIOCATMARK 0x8905 +#define SIOCGSTAMP 0x8906 +#define SIOCGSTAMPNS 0x8907 + +#define SIOCADDRT 0x890B +#define SIOCDELRT 0x890C +#define SIOCRTMSG 0x890D + +#define SIOCGIFNAME 0x8910 +#define SIOCSIFLINK 0x8911 +#define SIOCGIFCONF 0x8912 +#define SIOCGIFFLAGS 0x8913 +#define SIOCSIFFLAGS 0x8914 +#define SIOCGIFADDR 0x8915 +#define SIOCSIFADDR 0x8916 +#define SIOCGIFDSTADDR 0x8917 +#define SIOCSIFDSTADDR 0x8918 +#define SIOCGIFBRDADDR 0x8919 +#define SIOCSIFBRDADDR 0x891a +#define SIOCGIFNETMASK 0x891b +#define SIOCSIFNETMASK 0x891c +#define SIOCGIFMETRIC 0x891d +#define SIOCSIFMETRIC 0x891e +#define SIOCGIFMEM 0x891f +#define SIOCSIFMEM 0x8920 +#define SIOCGIFMTU 0x8921 +#define SIOCSIFMTU 0x8922 +#define SIOCSIFNAME 0x8923 +#define SIOCSIFHWADDR 0x8924 +#define SIOCGIFENCAP 0x8925 +#define SIOCSIFENCAP 0x8926 +#define SIOCGIFHWADDR 0x8927 +#define SIOCGIFSLAVE 0x8929 +#define SIOCSIFSLAVE 0x8930 +#define SIOCADDMULTI 0x8931 +#define SIOCDELMULTI 0x8932 +#define SIOCGIFINDEX 0x8933 +#define SIOGIFINDEX SIOCGIFINDEX +#define SIOCSIFPFLAGS 0x8934 +#define SIOCGIFPFLAGS 0x8935 +#define SIOCDIFADDR 0x8936 +#define SIOCSIFHWBROADCAST 0x8937 +#define SIOCGIFCOUNT 0x8938 + +#define SIOCGIFBR 0x8940 +#define SIOCSIFBR 0x8941 + +#define SIOCGIFTXQLEN 0x8942 +#define SIOCSIFTXQLEN 0x8943 + +#define SIOCDARP 0x8953 +#define SIOCGARP 0x8954 +#define SIOCSARP 0x8955 + +#define SIOCDRARP 0x8960 +#define SIOCGRARP 0x8961 +#define SIOCSRARP 0x8962 + +#define SIOCGIFMAP 0x8970 +#define SIOCSIFMAP 0x8971 + +#define SIOCADDDLCI 0x8980 +#define SIOCDELDLCI 0x8981 + +#define SIOCDEVPRIVATE 0x89F0 +#define SIOCPROTOPRIVATE 0x89E0 + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_signal.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_signal.h new file mode 100644 index 0000000000..71f8de125d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_signal.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-12 Bernard The first version + */ + +#ifndef LIBC_SIGNAL_H__ +#define LIBC_SIGNAL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef HAVE_CCONFIG_H +#include +#endif + +#ifndef HAVE_SIGVAL +/* Signal Generation and Delivery, P1003.1b-1993, p. 63 + NOTE: P1003.1c/D10, p. 34 adds sigev_notify_function and + sigev_notify_attributes to the sigevent structure. */ + +union sigval +{ + int sival_int; /* Integer signal value */ + void *sival_ptr; /* Pointer signal value */ +}; +#endif + +#ifndef HAVE_SIGEVENT +struct sigevent +{ + int sigev_notify; /* Notification type */ + int sigev_signo; /* Signal number */ + union sigval sigev_value; /* Signal value */ + void (*sigev_notify_function)( union sigval ); + /* Notification function */ + void *sigev_notify_attributes; /* Notification Attributes, really pthread_attr_t */ +}; +#endif + +#ifndef HAVE_SIGINFO +struct siginfo +{ + rt_uint16_t si_signo; + rt_uint16_t si_code; + + union sigval si_value; +}; +typedef struct siginfo siginfo_t; +#endif + +#define SI_USER 0x01 /* Signal sent by kill(). */ +#define SI_QUEUE 0x02 /* Signal sent by sigqueue(). */ +#define SI_TIMER 0x03 /* Signal generated by expiration of a + timer set by timer_settime(). */ +#define SI_ASYNCIO 0x04 /* Signal generated by completion of an + asynchronous I/O request. */ +#define SI_MESGQ 0x05 /* Signal generated by arrival of a + message on an empty message queue. */ + +#ifdef RT_USING_NEWLIB +#include +#endif + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +#include +typedef unsigned long sigset_t; + +#define SIGHUP 1 +/* #define SIGINT 2 */ +#define SIGQUIT 3 +/* #define SIGILL 4 */ +#define SIGTRAP 5 +/* #define SIGABRT 6 */ +#define SIGEMT 7 +/* #define SIGFPE 8 */ +#define SIGKILL 9 +#define SIGBUS 10 +/* #define SIGSEGV 11 */ +#define SIGSYS 12 +#define SIGPIPE 13 +#define SIGALRM 14 +/* #define SIGTERM 15 */ +#define SIGURG 16 +#define SIGSTOP 17 +#define SIGTSTP 18 +#define SIGCONT 19 +#define SIGCHLD 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGPOLL 23 +#define SIGWINCH 24 +/* #define SIGUSR1 25 */ +/* #define SIGUSR2 26 */ +#define SIGRTMIN 27 +#define SIGRTMAX 31 +#define NSIG 32 + +#define SIG_SETMASK 0 /* set mask with sigprocmask() */ +#define SIG_BLOCK 1 /* set of signals to block */ +#define SIG_UNBLOCK 2 /* set of signals to, well, unblock */ + +typedef void (*_sig_func_ptr)(int); + +struct sigaction +{ + _sig_func_ptr sa_handler; + sigset_t sa_mask; + int sa_flags; +}; + +#define sigaddset(what,sig) (*(what) |= (1<<(sig)), 0) +#define sigdelset(what,sig) (*(what) &= ~(1<<(sig)), 0) +#define sigemptyset(what) (*(what) = 0, 0) +#define sigfillset(what) (*(what) = ~(0), 0) +#define sigismember(what,sig) (((*(what)) & (1<<(sig))) != 0) + +int sigprocmask (int how, const sigset_t *set, sigset_t *oset); +int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact); + +#elif defined(__IAR_SYSTEMS_ICC__) +#include +typedef unsigned long sigset_t; + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +/* #define SIGABRT 6 */ +#define SIGEMT 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGBUS 10 +#define SIGSEGV 11 +#define SIGSYS 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGURG 16 +#define SIGSTOP 17 +#define SIGTSTP 18 +#define SIGCONT 19 +#define SIGCHLD 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGPOLL 23 +#define SIGWINCH 24 +#define SIGUSR1 25 +#define SIGUSR2 26 +#define SIGRTMIN 27 +#define SIGRTMAX 31 +#define NSIG 32 + +#define SIG_SETMASK 0 /* set mask with sigprocmask() */ +#define SIG_BLOCK 1 /* set of signals to block */ +#define SIG_UNBLOCK 2 /* set of signals to, well, unblock */ + +typedef void (*_sig_func_ptr)(int); + +struct sigaction +{ + _sig_func_ptr sa_handler; + sigset_t sa_mask; + int sa_flags; +}; + +#define sigaddset(what,sig) (*(what) |= (1<<(sig)), 0) +#define sigdelset(what,sig) (*(what) &= ~(1<<(sig)), 0) +#define sigemptyset(what) (*(what) = 0, 0) +#define sigfillset(what) (*(what) = ~(0), 0) +#define sigismember(what,sig) (((*(what)) & (1<<(sig))) != 0) + +int sigprocmask (int how, const sigset_t *set, sigset_t *oset); +int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_stat.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_stat.h new file mode 100644 index 0000000000..9079d1ef15 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/libc/libc_stat.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef LIBC_STAT_H__ +#define LIBC_STAT_H__ + +#include + +#if defined(RT_USING_NEWLIB) +/* use header file of newlib */ +#include + +#elif defined(_WIN32) +#include + +#define S_IRWXU 00700 +#define S_IRUSR 00400 +#define S_IWUSR 00200 +#define S_IXUSR 00100 + +#define S_IRWXG 00070 +#define S_IRGRP 00040 +#define S_IWGRP 00020 +#define S_IXGRP 00010 + +#define S_IRWXO 00007 +#define S_IROTH 00004 +#define S_IWOTH 00002 +#define S_IXOTH 00001 + +#define S_IFSOCK 0140000 +#define S_IFLNK 0120000 +#define S_IFBLK 0060000 +#define S_IFIFO 0010000 +#define S_ISUID 0004000 +#define S_ISGID 0002000 +#define S_ISVTX 0001000 + +#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR) + +#else +#define S_IFMT 00170000 +#define S_IFSOCK 0140000 +#define S_IFLNK 0120000 +#define S_IFREG 0100000 +#define S_IFBLK 0060000 +#define S_IFDIR 0040000 +#define S_IFCHR 0020000 +#define S_IFIFO 0010000 +#define S_ISUID 0004000 +#define S_ISGID 0002000 +#define S_ISVTX 0001000 + +#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK) +#define S_ISREG(m) (((m) & S_IFMT) == S_IFREG) +#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR) +#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR) +#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK) +#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO) +#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK) + +#define S_IRWXU 00700 +#define S_IRUSR 00400 +#define S_IWUSR 00200 +#define S_IXUSR 00100 + +#define S_IRWXG 00070 +#define S_IRGRP 00040 +#define S_IWGRP 00020 +#define S_IXGRP 00010 + +#define S_IRWXO 00007 +#define S_IROTH 00004 +#define S_IWOTH 00002 +#define S_IXOTH 00001 + +/* stat structure */ +#include +#include + +struct stat +{ + struct rt_device *st_dev; + uint16_t st_ino; + uint16_t st_mode; + uint16_t st_nlink; + uint16_t st_uid; + uint16_t st_gid; + struct rt_device *st_rdev; + uint32_t st_size; + time_t st_atime; + long st_spare1; + time_t st_mtime; + long st_spare2; + time_t st_ctime; + long st_spare3; + uint32_t st_blksize; + uint32_t st_blocks; + long st_spare4[2]; +}; + +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdbg.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdbg.h new file mode 100644 index 0000000000..a2dfbd9697 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdbg.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2016-11-12 Bernard The first version + * 2018-05-25 armink Add simple API, such as LOG_D, LOG_E + */ + +/* + * The macro definitions for debug + * + * These macros are defined in static. If you want to use debug macro, you can + * use as following code: + * + * In your C/C++ file, enable/disable DEBUG_ENABLE macro, and then include this + * header file. + * + * #define DBG_TAG "MOD_TAG" + * #define DBG_LVL DBG_INFO + * #include // must after of DBG_LVL, DBG_TAG or other options + * + * Then in your C/C++ file, you can use LOG_X macro to print out logs: + * LOG_D("this is a debug log!"); + * LOG_E("this is a error log!"); + */ + +#ifndef RT_DBG_H__ +#define RT_DBG_H__ + +#include + +/* the debug log will force enable when RT_DEBUG macro is defined */ +#if defined(RT_DEBUG) && !defined(DBG_ENABLE) +#define DBG_ENABLE +#endif + +/* it will force output color log when RT_DEBUG_COLOR macro is defined */ +#if defined(RT_DEBUG_COLOR) && !defined(DBG_COLOR) +#define DBG_COLOR +#endif + +#if defined(RT_USING_ULOG) +/* using ulog compatible with rtdbg */ +#include +#else + +/* DEBUG level */ +#define DBG_ERROR 0 +#define DBG_WARNING 1 +#define DBG_INFO 2 +#define DBG_LOG 3 + +#ifdef DBG_TAG +#ifndef DBG_SECTION_NAME +#define DBG_SECTION_NAME DBG_TAG +#endif +#else +/* compatible with old version */ +#ifndef DBG_SECTION_NAME +#define DBG_SECTION_NAME "DBG" +#endif +#endif /* DBG_TAG */ + +#ifdef DBG_ENABLE + +#ifdef DBG_LVL +#ifndef DBG_LEVEL +#define DBG_LEVEL DBG_LVL +#endif +#else +/* compatible with old version */ +#ifndef DBG_LEVEL +#define DBG_LEVEL DBG_WARNING +#endif +#endif /* DBG_LVL */ + +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ +#ifdef DBG_COLOR +#define _DBG_COLOR(n) rt_kprintf("\033["#n"m") +#define _DBG_LOG_HDR(lvl_name, color_n) \ + rt_kprintf("\033["#color_n"m["lvl_name"/"DBG_SECTION_NAME"] ") +#define _DBG_LOG_X_END \ + rt_kprintf("\033[0m\n") +#else +#define _DBG_COLOR(n) +#define _DBG_LOG_HDR(lvl_name, color_n) \ + rt_kprintf("["lvl_name"/"DBG_SECTION_NAME"] ") +#define _DBG_LOG_X_END \ + rt_kprintf("\n") +#endif /* DBG_COLOR */ + +/* + * static debug routine + * NOTE: This is a NOT RECOMMENDED API. Please using LOG_X API. + * It will be DISCARDED later. Because it will take up more resources. + */ +#define dbg_log(level, fmt, ...) \ + if ((level) <= DBG_LEVEL) \ + { \ + switch(level) \ + { \ + case DBG_ERROR: _DBG_LOG_HDR("E", 31); break; \ + case DBG_WARNING: _DBG_LOG_HDR("W", 33); break; \ + case DBG_INFO: _DBG_LOG_HDR("I", 32); break; \ + case DBG_LOG: _DBG_LOG_HDR("D", 0); break; \ + default: break; \ + } \ + rt_kprintf(fmt, ##__VA_ARGS__); \ + _DBG_COLOR(0); \ + } + +#define dbg_here \ + if ((DBG_LEVEL) <= DBG_LOG){ \ + rt_kprintf(DBG_SECTION_NAME " Here %s:%d\n", \ + __FUNCTION__, __LINE__); \ + } + +#define dbg_log_line(lvl, color_n, fmt, ...) \ + do \ + { \ + _DBG_LOG_HDR(lvl, color_n); \ + rt_kprintf(fmt, ##__VA_ARGS__); \ + _DBG_LOG_X_END; \ + } \ + while (0) + +#define dbg_raw(...) rt_kprintf(__VA_ARGS__); + +#else +#define dbg_log(level, fmt, ...) +#define dbg_here +#define dbg_enter +#define dbg_exit +#define dbg_log_line(lvl, color_n, fmt, ...) +#define dbg_raw(...) +#endif /* DBG_ENABLE */ + +#if (DBG_LEVEL >= DBG_LOG) +#define LOG_D(fmt, ...) dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define LOG_D(...) +#endif + +#if (DBG_LEVEL >= DBG_INFO) +#define LOG_I(fmt, ...) dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define LOG_I(...) +#endif + +#if (DBG_LEVEL >= DBG_WARNING) +#define LOG_W(fmt, ...) dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define LOG_W(...) +#endif + +#if (DBG_LEVEL >= DBG_ERROR) +#define LOG_E(fmt, ...) dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define LOG_E(...) +#endif + +#define LOG_RAW(...) dbg_raw(__VA_ARGS__) + +#endif /* defined(RT_USING_ULOG) && define(DBG_ENABLE) */ + +#endif /* RT_DBG_H__ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdebug.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdebug.h new file mode 100644 index 0000000000..b66cd6fc69 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdebug.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RTDEBUG_H__ +#define __RTDEBUG_H__ + +#include + +/* settings depend check */ +#ifdef RT_USING_POSIX +#if !defined(RT_USING_DFS) || !defined(RT_USING_DFS_DEVFS) +#error "POSIX poll/select, stdin need file system(RT_USING_DFS) and device file system(RT_USING_DFS_DEVFS)" +#endif + +#if !defined(RT_USING_LIBC) +#error "POSIX layer need standard C library(RT_USING_LIBC)" +#endif + +#endif + +#ifdef RT_USING_POSIX_TERMIOS +#if !defined(RT_USING_POSIX) +#error "termios need POSIX layer(RT_USING_POSIX)" +#endif +#endif + +/* Using this macro to control all kernel debug features. */ +#ifdef RT_DEBUG + +/* Turn on some of these (set to non-zero) to debug kernel */ +#ifndef RT_DEBUG_MEM +#define RT_DEBUG_MEM 0 +#endif + +#ifndef RT_DEBUG_MEMHEAP +#define RT_DEBUG_MEMHEAP 0 +#endif + +#ifndef RT_DEBUG_MODULE +#define RT_DEBUG_MODULE 0 +#endif + +#ifndef RT_DEBUG_SCHEDULER +#define RT_DEBUG_SCHEDULER 0 +#endif + +#ifndef RT_DEBUG_SLAB +#define RT_DEBUG_SLAB 0 +#endif + +#ifndef RT_DEBUG_THREAD +#define RT_DEBUG_THREAD 0 +#endif + +#ifndef RT_DEBUG_TIMER +#define RT_DEBUG_TIMER 0 +#endif + +#ifndef RT_DEBUG_IRQ +#define RT_DEBUG_IRQ 0 +#endif + +#ifndef RT_DEBUG_IPC +#define RT_DEBUG_IPC 0 +#endif + +#ifndef RT_DEBUG_INIT +#define RT_DEBUG_INIT 0 +#endif + +/* Turn on this to enable context check */ +#ifndef RT_DEBUG_CONTEXT_CHECK +#define RT_DEBUG_CONTEXT_CHECK 1 +#endif + +#define RT_DEBUG_LOG(type, message) \ +do \ +{ \ + if (type) \ + rt_kprintf message; \ +} \ +while (0) + +#define RT_ASSERT(EX) \ +if (!(EX)) \ +{ \ + rt_assert_handler(#EX, __FUNCTION__, __LINE__); \ +} + +/* Macro to check current context */ +#if RT_DEBUG_CONTEXT_CHECK +#define RT_DEBUG_NOT_IN_INTERRUPT \ +do \ +{ \ + rt_base_t level; \ + level = rt_hw_interrupt_disable(); \ + if (rt_interrupt_get_nest() != 0) \ + { \ + rt_kprintf("Function[%s] shall not be used in ISR\n", __FUNCTION__); \ + RT_ASSERT(0) \ + } \ + rt_hw_interrupt_enable(level); \ +} \ +while (0) + +/* "In thread context" means: + * 1) the scheduler has been started + * 2) not in interrupt context. + */ +#define RT_DEBUG_IN_THREAD_CONTEXT \ +do \ +{ \ + rt_base_t level; \ + level = rt_hw_interrupt_disable(); \ + if (rt_thread_self() == RT_NULL) \ + { \ + rt_kprintf("Function[%s] shall not be used before scheduler start\n", \ + __FUNCTION__); \ + RT_ASSERT(0) \ + } \ + RT_DEBUG_NOT_IN_INTERRUPT; \ + rt_hw_interrupt_enable(level); \ +} \ +while (0) +#else +#define RT_DEBUG_NOT_IN_INTERRUPT +#define RT_DEBUG_IN_THREAD_CONTEXT +#endif + +#else /* RT_DEBUG */ + +#define RT_ASSERT(EX) +#define RT_DEBUG_LOG(type, message) +#define RT_DEBUG_NOT_IN_INTERRUPT +#define RT_DEBUG_IN_THREAD_CONTEXT + +#endif /* RT_DEBUG */ + +#endif /* __RTDEBUG_H__ */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdef.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdef.h new file mode 100644 index 0000000000..91a8a470de --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtdef.h @@ -0,0 +1,1048 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2007-01-10 Bernard the first version + * 2008-07-12 Bernard remove all rt_int8, rt_uint32_t etc typedef + * 2010-10-26 yi.qiu add module support + * 2010-11-10 Bernard add cleanup callback function in thread exit. + * 2011-05-09 Bernard use builtin va_arg in GCC 4.x + * 2012-11-16 Bernard change RT_NULL from ((void*)0) to 0. + * 2012-12-29 Bernard change the RT_USING_MEMPOOL location and add + * RT_USING_MEMHEAP condition. + * 2012-12-30 Bernard add more control command for graphic. + * 2013-01-09 Bernard change version number. + * 2015-02-01 Bernard change version number to v2.1.0 + * 2017-08-31 Bernard change version number to v3.0.0 + * 2017-11-30 Bernard change version number to v3.0.1 + * 2017-12-27 Bernard change version number to v3.0.2 + * 2018-02-24 Bernard change version number to v3.0.3 + * 2018-04-25 Bernard change version number to v3.0.4 + * 2018-05-31 Bernard change version number to v3.1.0 + * 2018-09-04 Bernard change version number to v3.1.1 + * 2018-09-14 Bernard apply Apache License v2.0 to RT-Thread Kernel + * 2018-12-28 armink change version number to v3.1.2 + * 2019-03-14 armink change version number to v3.1.3 + */ + +#ifndef __RT_DEF_H__ +#define __RT_DEF_H__ + +/* include rtconfig header to import configuration */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup BasicDef + */ + +/*@{*/ + +/* RT-Thread version information */ +#define RT_VERSION 3L /**< major version number */ +#define RT_SUBVERSION 1L /**< minor version number */ +#define RT_REVISION 3L /**< revise version number */ + +/* RT-Thread version */ +#define RTTHREAD_VERSION ((RT_VERSION * 10000) + \ + (RT_SUBVERSION * 100) + RT_REVISION) + +/* RT-Thread basic data type definitions */ +#ifndef RT_USING_ARCH_DATA_TYPE +typedef signed char rt_int8_t; /**< 8bit integer type */ +typedef signed short rt_int16_t; /**< 16bit integer type */ +typedef signed long rt_int32_t; /**< 32bit integer type */ +typedef signed long long rt_int64_t; /**< 64bit integer type */ +typedef unsigned char rt_uint8_t; /**< 8bit unsigned integer type */ +typedef unsigned short rt_uint16_t; /**< 16bit unsigned integer type */ +typedef unsigned long rt_uint32_t; /**< 32bit unsigned integer type */ +typedef unsigned long long rt_uint64_t; /**< 64bit unsigned integer type */ +#endif +typedef int rt_bool_t; /**< boolean type */ + +/* 32bit CPU */ +typedef long rt_base_t; /**< Nbit CPU related date type */ +typedef unsigned long rt_ubase_t; /**< Nbit unsigned CPU related data type */ + +typedef rt_base_t rt_err_t; /**< Type for error number */ +typedef rt_uint32_t rt_time_t; /**< Type for time stamp */ +typedef rt_uint32_t rt_tick_t; /**< Type for tick count */ +typedef rt_base_t rt_flag_t; /**< Type for flags */ +typedef rt_ubase_t rt_size_t; /**< Type for size number */ +typedef rt_ubase_t rt_dev_t; /**< Type for device */ +typedef rt_base_t rt_off_t; /**< Type for offset */ + +/* boolean type definitions */ +#define RT_TRUE 1 /**< boolean true */ +#define RT_FALSE 0 /**< boolean fails */ + +/**@}*/ + +/* maximum value of base type */ +#define RT_UINT8_MAX 0xff /**< Maxium number of UINT8 */ +#define RT_UINT16_MAX 0xffff /**< Maxium number of UINT16 */ +#define RT_UINT32_MAX 0xffffffff /**< Maxium number of UINT32 */ +#define RT_TICK_MAX RT_UINT32_MAX /**< Maxium number of tick */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __CLANG_ARM +#endif + +/* Compiler Related Definitions */ +#if defined(__CC_ARM) || defined(__CLANG_ARM) /* ARM Compiler */ + #include + #define SECTION(x) __attribute__((section(x))) + #define RT_UNUSED __attribute__((unused)) + #define RT_USED __attribute__((used)) + #define ALIGN(n) __attribute__((aligned(n))) + + #define RT_WEAK __attribute__((weak)) + #define rt_inline static __inline + /* module compiling */ + #ifdef RT_USING_MODULE + #define RTT_API __declspec(dllimport) + #else + #define RTT_API __declspec(dllexport) + #endif + +#elif defined (__IAR_SYSTEMS_ICC__) /* for IAR Compiler */ + #include + #define SECTION(x) @ x + #define RT_UNUSED + #define RT_USED __root + #define PRAGMA(x) _Pragma(#x) + #define ALIGN(n) PRAGMA(data_alignment=n) + #define RT_WEAK __weak + #define rt_inline static inline + #define RTT_API + +#elif defined (__GNUC__) /* GNU GCC Compiler */ + #ifdef RT_USING_NEWLIB + #include + #else + /* the version of GNU GCC must be greater than 4.x */ + typedef __builtin_va_list __gnuc_va_list; + typedef __gnuc_va_list va_list; + #define va_start(v,l) __builtin_va_start(v,l) + #define va_end(v) __builtin_va_end(v) + #define va_arg(v,l) __builtin_va_arg(v,l) + #endif + + #define SECTION(x) __attribute__((section(x))) + #define RT_UNUSED __attribute__((unused)) + #define RT_USED __attribute__((used)) + #define ALIGN(n) __attribute__((aligned(n))) + #define RT_WEAK __attribute__((weak)) + #define rt_inline static __inline + #define RTT_API +#elif defined (__ADSPBLACKFIN__) /* for VisualDSP++ Compiler */ + #include + #define SECTION(x) __attribute__((section(x))) + #define RT_UNUSED __attribute__((unused)) + #define RT_USED __attribute__((used)) + #define ALIGN(n) __attribute__((aligned(n))) + #define RT_WEAK __attribute__((weak)) + #define rt_inline static inline + #define RTT_API +#elif defined (_MSC_VER) + #include + #define SECTION(x) + #define RT_UNUSED + #define RT_USED + #define ALIGN(n) __declspec(align(n)) + #define RT_WEAK + #define rt_inline static __inline + #define RTT_API +#elif defined (__TI_COMPILER_VERSION__) + #include + /* The way that TI compiler set section is different from other(at least + * GCC and MDK) compilers. See ARM Optimizing C/C++ Compiler 5.9.3 for more + * details. */ + #define SECTION(x) + #define RT_UNUSED + #define RT_USED + #define PRAGMA(x) _Pragma(#x) + #define ALIGN(n) + #define RT_WEAK + #define rt_inline static inline + #define RTT_API +#else + #error not supported tool chain +#endif + +/* initialization export */ +#ifdef RT_USING_COMPONENTS_INIT +typedef int (*init_fn_t)(void); +#ifdef _MSC_VER /* we do not support MS VC++ compiler */ + #define INIT_EXPORT(fn, level) +#else + #if RT_DEBUG_INIT + struct rt_init_desc + { + const char* fn_name; + const init_fn_t fn; + }; + #define INIT_EXPORT(fn, level) \ + const char __rti_##fn##_name[] = #fn; \ + RT_USED const struct rt_init_desc __rt_init_desc_##fn SECTION(".rti_fn."level) = \ + { __rti_##fn##_name, fn}; + #else + #define INIT_EXPORT(fn, level) \ + RT_USED const init_fn_t __rt_init_##fn SECTION(".rti_fn."level) = fn + #endif +#endif +#else +#define INIT_EXPORT(fn, level) +#endif + +/* board init routines will be called in board_init() function */ +#define INIT_BOARD_EXPORT(fn) INIT_EXPORT(fn, "1") + +/* pre/device/component/env/app init routines will be called in init_thread */ +/* components pre-initialization (pure software initilization) */ +#define INIT_PREV_EXPORT(fn) INIT_EXPORT(fn, "2") +/* device initialization */ +#define INIT_DEVICE_EXPORT(fn) INIT_EXPORT(fn, "3") +/* components initialization (dfs, lwip, ...) */ +#define INIT_COMPONENT_EXPORT(fn) INIT_EXPORT(fn, "4") +/* environment initialization (mount disk, ...) */ +#define INIT_ENV_EXPORT(fn) INIT_EXPORT(fn, "5") +/* appliation initialization (rtgui application etc ...) */ +#define INIT_APP_EXPORT(fn) INIT_EXPORT(fn, "6") + +#if !defined(RT_USING_FINSH) +/* define these to empty, even if not include finsh.h file */ +#define FINSH_FUNCTION_EXPORT(name, desc) +#define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc) +#define FINSH_VAR_EXPORT(name, type, desc) + +#define MSH_CMD_EXPORT(command, desc) +#define MSH_CMD_EXPORT_ALIAS(command, alias, desc) +#elif !defined(FINSH_USING_SYMTAB) +#define FINSH_FUNCTION_EXPORT_CMD(name, cmd, desc) +#endif + +/* event length */ +#define RT_EVENT_LENGTH 32 + +/* memory management option */ +#define RT_MM_PAGE_SIZE 4096 +#define RT_MM_PAGE_MASK (RT_MM_PAGE_SIZE - 1) +#define RT_MM_PAGE_BITS 12 + +/* kernel malloc definitions */ +#ifndef RT_KERNEL_MALLOC +#define RT_KERNEL_MALLOC(sz) rt_malloc(sz) +#endif + +#ifndef RT_KERNEL_FREE +#define RT_KERNEL_FREE(ptr) rt_free(ptr) +#endif + +#ifndef RT_KERNEL_REALLOC +#define RT_KERNEL_REALLOC(ptr, size) rt_realloc(ptr, size) +#endif + +/** + * @addtogroup Error + */ + +/**@{*/ + +/* RT-Thread error code definitions */ +#define RT_EOK 0 /**< There is no error */ +#define RT_ERROR 1 /**< A generic error happens */ +#define RT_ETIMEOUT 2 /**< Timed out */ +#define RT_EFULL 3 /**< The resource is full */ +#define RT_EEMPTY 4 /**< The resource is empty */ +#define RT_ENOMEM 5 /**< No memory */ +#define RT_ENOSYS 6 /**< No system */ +#define RT_EBUSY 7 /**< Busy */ +#define RT_EIO 8 /**< IO error */ +#define RT_EINTR 9 /**< Interrupted system call */ +#define RT_EINVAL 10 /**< Invalid argument */ + +/**@}*/ + +/** + * @ingroup BasicDef + * + * @def RT_ALIGN(size, align) + * Return the most contiguous size aligned at specified width. RT_ALIGN(13, 4) + * would return 16. + */ +#define RT_ALIGN(size, align) (((size) + (align) - 1) & ~((align) - 1)) + +/** + * @ingroup BasicDef + * + * @def RT_ALIGN_DOWN(size, align) + * Return the down number of aligned at specified width. RT_ALIGN_DOWN(13, 4) + * would return 12. + */ +#define RT_ALIGN_DOWN(size, align) ((size) & ~((align) - 1)) + +/** + * @ingroup BasicDef + * + * @def RT_NULL + * Similar as the \c NULL in C library. + */ +#define RT_NULL (0) + +/** + * Double List structure + */ +struct rt_list_node +{ + struct rt_list_node *next; /**< point to next node. */ + struct rt_list_node *prev; /**< point to prev node. */ +}; +typedef struct rt_list_node rt_list_t; /**< Type for lists. */ + +/** + * Single List structure + */ +struct rt_slist_node +{ + struct rt_slist_node *next; /**< point to next node. */ +}; +typedef struct rt_slist_node rt_slist_t; /**< Type for single list. */ + +/** + * @addtogroup KernelObject + */ + +/**@{*/ + +/* + * kernel object macros + */ +#define RT_OBJECT_FLAG_MODULE 0x80 /**< is module object. */ + +/** + * Base structure of Kernel object + */ +struct rt_object +{ + char name[RT_NAME_MAX]; /**< name of kernel object */ + rt_uint8_t type; /**< type of kernel object */ + rt_uint8_t flag; /**< flag of kernel object */ + +#ifdef RT_USING_MODULE + void *module_id; /**< id of application module */ +#endif + rt_list_t list; /**< list node of kernel object */ +}; +typedef struct rt_object *rt_object_t; /**< Type for kernel objects. */ + +/** + * The object type can be one of the follows with specific + * macros enabled: + * - Thread + * - Semaphore + * - Mutex + * - Event + * - MailBox + * - MessageQueue + * - MemHeap + * - MemPool + * - Device + * - Timer + * - Module + * - Unknown + * - Static + */ +enum rt_object_class_type +{ + RT_Object_Class_Null = 0, /**< The object is not used. */ + RT_Object_Class_Thread, /**< The object is a thread. */ + RT_Object_Class_Semaphore, /**< The object is a semaphore. */ + RT_Object_Class_Mutex, /**< The object is a mutex. */ + RT_Object_Class_Event, /**< The object is a event. */ + RT_Object_Class_MailBox, /**< The object is a mail box. */ + RT_Object_Class_MessageQueue, /**< The object is a message queue. */ + RT_Object_Class_MemHeap, /**< The object is a memory heap */ + RT_Object_Class_MemPool, /**< The object is a memory pool. */ + RT_Object_Class_Device, /**< The object is a device */ + RT_Object_Class_Timer, /**< The object is a timer. */ + RT_Object_Class_Module, /**< The object is a module. */ + RT_Object_Class_Unknown, /**< The object is unknown. */ + RT_Object_Class_Static = 0x80 /**< The object is a static object. */ +}; + +/** + * The information of the kernel object + */ +struct rt_object_information +{ + enum rt_object_class_type type; /**< object class type */ + rt_list_t object_list; /**< object list */ + rt_size_t object_size; /**< object size */ +}; + +/** + * The hook function call macro + */ +#ifdef RT_USING_HOOK +#define RT_OBJECT_HOOK_CALL(func, argv) \ + do { if ((func) != RT_NULL) func argv; } while (0) +#else +#define RT_OBJECT_HOOK_CALL(func, argv) +#endif + +/**@}*/ + +/** + * @addtogroup Clock + */ + +/**@{*/ + +/** + * clock & timer macros + */ +#define RT_TIMER_FLAG_DEACTIVATED 0x0 /**< timer is deactive */ +#define RT_TIMER_FLAG_ACTIVATED 0x1 /**< timer is active */ +#define RT_TIMER_FLAG_ONE_SHOT 0x0 /**< one shot timer */ +#define RT_TIMER_FLAG_PERIODIC 0x2 /**< periodic timer */ + +#define RT_TIMER_FLAG_HARD_TIMER 0x0 /**< hard timer,the timer's callback function will be called in tick isr. */ +#define RT_TIMER_FLAG_SOFT_TIMER 0x4 /**< soft timer,the timer's callback function will be called in timer thread. */ + +#define RT_TIMER_CTRL_SET_TIME 0x0 /**< set timer control command */ +#define RT_TIMER_CTRL_GET_TIME 0x1 /**< get timer control command */ +#define RT_TIMER_CTRL_SET_ONESHOT 0x2 /**< change timer to one shot */ +#define RT_TIMER_CTRL_SET_PERIODIC 0x3 /**< change timer to periodic */ + +#ifndef RT_TIMER_SKIP_LIST_LEVEL +#define RT_TIMER_SKIP_LIST_LEVEL 1 +#endif + +/* 1 or 3 */ +#ifndef RT_TIMER_SKIP_LIST_MASK +#define RT_TIMER_SKIP_LIST_MASK 0x3 +#endif + +/** + * timer structure + */ +struct rt_timer +{ + struct rt_object parent; /**< inherit from rt_object */ + + rt_list_t row[RT_TIMER_SKIP_LIST_LEVEL]; + + void (*timeout_func)(void *parameter); /**< timeout function */ + void *parameter; /**< timeout function's parameter */ + + rt_tick_t init_tick; /**< timer timeout tick */ + rt_tick_t timeout_tick; /**< timeout tick */ +}; +typedef struct rt_timer *rt_timer_t; + +/**@}*/ + +/** + * @addtogroup Signal + */ +#ifdef RT_USING_SIGNALS +#include +typedef unsigned long rt_sigset_t; +typedef void (*rt_sighandler_t)(int signo); +typedef siginfo_t rt_siginfo_t; + +#define RT_SIG_MAX 32 +#endif +/**@}*/ + +/** + * @addtogroup Thread + */ + +/**@{*/ + +/* + * Thread + */ + +/* + * thread state definitions + */ +#define RT_THREAD_INIT 0x00 /**< Initialized status */ +#define RT_THREAD_READY 0x01 /**< Ready status */ +#define RT_THREAD_SUSPEND 0x02 /**< Suspend status */ +#define RT_THREAD_RUNNING 0x03 /**< Running status */ +#define RT_THREAD_BLOCK RT_THREAD_SUSPEND /**< Blocked status */ +#define RT_THREAD_CLOSE 0x04 /**< Closed status */ +#define RT_THREAD_STAT_MASK 0x0f + +#define RT_THREAD_STAT_SIGNAL 0x10 /**< task hold signals */ +#define RT_THREAD_STAT_SIGNAL_READY (RT_THREAD_STAT_SIGNAL | RT_THREAD_READY) +#define RT_THREAD_STAT_SIGNAL_WAIT 0x20 /**< task is waiting for signals */ +#define RT_THREAD_STAT_SIGNAL_PENDING 0x40 /**< signals is held and it has not been procressed */ +#define RT_THREAD_STAT_SIGNAL_MASK 0xf0 + +/** + * thread control command definitions + */ +#define RT_THREAD_CTRL_STARTUP 0x00 /**< Startup thread. */ +#define RT_THREAD_CTRL_CLOSE 0x01 /**< Close thread. */ +#define RT_THREAD_CTRL_CHANGE_PRIORITY 0x02 /**< Change thread priority. */ +#define RT_THREAD_CTRL_INFO 0x03 /**< Get thread information. */ + +/** + * Thread structure + */ +struct rt_thread +{ + /* rt object */ + char name[RT_NAME_MAX]; /**< the name of thread */ + rt_uint8_t type; /**< type of object */ + rt_uint8_t flags; /**< thread's flags */ + +#ifdef RT_USING_MODULE + void *module_id; /**< id of application module */ +#endif + + rt_list_t list; /**< the object list */ + rt_list_t tlist; /**< the thread list */ + + /* stack point and entry */ + void *sp; /**< stack point */ + void *entry; /**< entry */ + void *parameter; /**< parameter */ + void *stack_addr; /**< stack address */ + rt_uint32_t stack_size; /**< stack size */ + + /* error code */ + rt_err_t error; /**< error code */ + + rt_uint8_t stat; /**< thread status */ + + /* priority */ + rt_uint8_t current_priority; /**< current priority */ + rt_uint8_t init_priority; /**< initialized priority */ +#if RT_THREAD_PRIORITY_MAX > 32 + rt_uint8_t number; + rt_uint8_t high_mask; +#endif + rt_uint32_t number_mask; + +#if defined(RT_USING_EVENT) + /* thread event */ + rt_uint32_t event_set; + rt_uint8_t event_info; +#endif + +#if defined(RT_USING_SIGNALS) + rt_sigset_t sig_pending; /**< the pending signals */ + rt_sigset_t sig_mask; /**< the mask bits of signal */ + + void *sig_ret; /**< the return stack pointer from signal */ + rt_sighandler_t *sig_vectors; /**< vectors of signal handler */ + void *si_list; /**< the signal infor list */ +#endif + + rt_ubase_t init_tick; /**< thread's initialized tick */ + rt_ubase_t remaining_tick; /**< remaining tick */ + + struct rt_timer thread_timer; /**< built-in thread timer */ + + void (*cleanup)(struct rt_thread *tid); /**< cleanup function when thread exit */ + + /* light weight process if present */ +#ifdef RT_USING_LWP + void *lwp; +#endif + + rt_uint32_t user_data; /**< private user data beyond this thread */ +}; +typedef struct rt_thread *rt_thread_t; + +/**@}*/ + +/** + * @addtogroup IPC + */ + +/**@{*/ + +/** + * IPC flags and control command definitions + */ +#define RT_IPC_FLAG_FIFO 0x00 /**< FIFOed IPC. @ref IPC. */ +#define RT_IPC_FLAG_PRIO 0x01 /**< PRIOed IPC. @ref IPC. */ + +#define RT_IPC_CMD_UNKNOWN 0x00 /**< unknown IPC command */ +#define RT_IPC_CMD_RESET 0x01 /**< reset IPC object */ + +#define RT_WAITING_FOREVER -1 /**< Block forever until get resource. */ +#define RT_WAITING_NO 0 /**< Non-block. */ + +/** + * Base structure of IPC object + */ +struct rt_ipc_object +{ + struct rt_object parent; /**< inherit from rt_object */ + + rt_list_t suspend_thread; /**< threads pended on this resource */ +}; + +#ifdef RT_USING_SEMAPHORE +/** + * Semaphore structure + */ +struct rt_semaphore +{ + struct rt_ipc_object parent; /**< inherit from ipc_object */ + + rt_uint16_t value; /**< value of semaphore. */ + rt_uint16_t reserved; /**< reserved field */ +}; +typedef struct rt_semaphore *rt_sem_t; +#endif + +#ifdef RT_USING_MUTEX +/** + * Mutual exclusion (mutex) structure + */ +struct rt_mutex +{ + struct rt_ipc_object parent; /**< inherit from ipc_object */ + + rt_uint16_t value; /**< value of mutex */ + + rt_uint8_t original_priority; /**< priority of last thread hold the mutex */ + rt_uint8_t hold; /**< numbers of thread hold the mutex */ + + struct rt_thread *owner; /**< current owner of mutex */ +}; +typedef struct rt_mutex *rt_mutex_t; +#endif + +#ifdef RT_USING_EVENT +/** + * flag defintions in event + */ +#define RT_EVENT_FLAG_AND 0x01 /**< logic and */ +#define RT_EVENT_FLAG_OR 0x02 /**< logic or */ +#define RT_EVENT_FLAG_CLEAR 0x04 /**< clear flag */ + +/* + * event structure + */ +struct rt_event +{ + struct rt_ipc_object parent; /**< inherit from ipc_object */ + + rt_uint32_t set; /**< event set */ +}; +typedef struct rt_event *rt_event_t; +#endif + +#ifdef RT_USING_MAILBOX +/** + * mailbox structure + */ +struct rt_mailbox +{ + struct rt_ipc_object parent; /**< inherit from ipc_object */ + + rt_uint32_t *msg_pool; /**< start address of message buffer */ + + rt_uint16_t size; /**< size of message pool */ + + rt_uint16_t entry; /**< index of messages in msg_pool */ + rt_uint16_t in_offset; /**< input offset of the message buffer */ + rt_uint16_t out_offset; /**< output offset of the message buffer */ + + rt_list_t suspend_sender_thread; /**< sender thread suspended on this mailbox */ +}; +typedef struct rt_mailbox *rt_mailbox_t; +#endif + +#ifdef RT_USING_MESSAGEQUEUE +/** + * message queue structure + */ +struct rt_messagequeue +{ + struct rt_ipc_object parent; /**< inherit from ipc_object */ + + void *msg_pool; /**< start address of message queue */ + + rt_uint16_t msg_size; /**< message size of each message */ + rt_uint16_t max_msgs; /**< max number of messages */ + + rt_uint16_t entry; /**< index of messages in the queue */ + + void *msg_queue_head; /**< list head */ + void *msg_queue_tail; /**< list tail */ + void *msg_queue_free; /**< pointer indicated the free node of queue */ +}; +typedef struct rt_messagequeue *rt_mq_t; +#endif + +/**@}*/ + +/** + * @addtogroup MM + */ + +/**@{*/ + +/* + * memory management + * heap & partition + */ + +#ifdef RT_USING_MEMHEAP +/** + * memory item on the heap + */ +struct rt_memheap_item +{ + rt_uint32_t magic; /**< magic number for memheap */ + struct rt_memheap *pool_ptr; /**< point of pool */ + + struct rt_memheap_item *next; /**< next memheap item */ + struct rt_memheap_item *prev; /**< prev memheap item */ + + struct rt_memheap_item *next_free; /**< next free memheap item */ + struct rt_memheap_item *prev_free; /**< prev free memheap item */ +}; + +/** + * Base structure of memory heap object + */ +struct rt_memheap +{ + struct rt_object parent; /**< inherit from rt_object */ + + void *start_addr; /**< pool start address and size */ + + rt_uint32_t pool_size; /**< pool size */ + rt_uint32_t available_size; /**< available size */ + rt_uint32_t max_used_size; /**< maximum allocated size */ + + struct rt_memheap_item *block_list; /**< used block list */ + + struct rt_memheap_item *free_list; /**< free block list */ + struct rt_memheap_item free_header; /**< free block list header */ + + struct rt_semaphore lock; /**< semaphore lock */ +}; +#endif + +#ifdef RT_USING_MEMPOOL +/** + * Base structure of Memory pool object + */ +struct rt_mempool +{ + struct rt_object parent; /**< inherit from rt_object */ + + void *start_address; /**< memory pool start */ + rt_size_t size; /**< size of memory pool */ + + rt_size_t block_size; /**< size of memory blocks */ + rt_uint8_t *block_list; /**< memory blocks list */ + + rt_size_t block_total_count; /**< numbers of memory block */ + rt_size_t block_free_count; /**< numbers of free memory block */ + + rt_list_t suspend_thread; /**< threads pended on this resource */ + rt_size_t suspend_thread_count; /**< numbers of thread pended on this resource */ +}; +typedef struct rt_mempool *rt_mp_t; +#endif + +/**@}*/ + +#ifdef RT_USING_DEVICE +/** + * @addtogroup Device + */ + +/**@{*/ + +/** + * device (I/O) class type + */ +enum rt_device_class_type +{ + RT_Device_Class_Char = 0, /**< character device */ + RT_Device_Class_Block, /**< block device */ + RT_Device_Class_NetIf, /**< net interface */ + RT_Device_Class_MTD, /**< memory device */ + RT_Device_Class_CAN, /**< CAN device */ + RT_Device_Class_RTC, /**< RTC device */ + RT_Device_Class_Sound, /**< Sound device */ + RT_Device_Class_Graphic, /**< Graphic device */ + RT_Device_Class_I2CBUS, /**< I2C bus device */ + RT_Device_Class_USBDevice, /**< USB slave device */ + RT_Device_Class_USBHost, /**< USB host bus */ + RT_Device_Class_SPIBUS, /**< SPI bus device */ + RT_Device_Class_SPIDevice, /**< SPI device */ + RT_Device_Class_SDIO, /**< SDIO bus device */ + RT_Device_Class_PM, /**< PM pseudo device */ + RT_Device_Class_Pipe, /**< Pipe device */ + RT_Device_Class_Portal, /**< Portal device */ + RT_Device_Class_Timer, /**< Timer device */ + RT_Device_Class_Miscellaneous, /**< Miscellaneous device */ + RT_Device_Class_Sensor, /**< Sensor device */ + RT_Device_Class_Unknown /**< unknown device */ +}; + +/** + * device flags defitions + */ +#define RT_DEVICE_FLAG_DEACTIVATE 0x000 /**< device is not not initialized */ + +#define RT_DEVICE_FLAG_RDONLY 0x001 /**< read only */ +#define RT_DEVICE_FLAG_WRONLY 0x002 /**< write only */ +#define RT_DEVICE_FLAG_RDWR 0x003 /**< read and write */ + +#define RT_DEVICE_FLAG_REMOVABLE 0x004 /**< removable device */ +#define RT_DEVICE_FLAG_STANDALONE 0x008 /**< standalone device */ +#define RT_DEVICE_FLAG_ACTIVATED 0x010 /**< device is activated */ +#define RT_DEVICE_FLAG_SUSPENDED 0x020 /**< device is suspended */ +#define RT_DEVICE_FLAG_STREAM 0x040 /**< stream mode */ + +#define RT_DEVICE_FLAG_INT_RX 0x100 /**< INT mode on Rx */ +#define RT_DEVICE_FLAG_DMA_RX 0x200 /**< DMA mode on Rx */ +#define RT_DEVICE_FLAG_INT_TX 0x400 /**< INT mode on Tx */ +#define RT_DEVICE_FLAG_DMA_TX 0x800 /**< DMA mode on Tx */ + +#define RT_DEVICE_OFLAG_CLOSE 0x000 /**< device is closed */ +#define RT_DEVICE_OFLAG_RDONLY 0x001 /**< read only access */ +#define RT_DEVICE_OFLAG_WRONLY 0x002 /**< write only access */ +#define RT_DEVICE_OFLAG_RDWR 0x003 /**< read and write */ +#define RT_DEVICE_OFLAG_OPEN 0x008 /**< device is opened */ +#define RT_DEVICE_OFLAG_MASK 0xf0f /**< mask of open flag */ + +/** + * general device commands + */ +#define RT_DEVICE_CTRL_RESUME 0x01 /**< resume device */ +#define RT_DEVICE_CTRL_SUSPEND 0x02 /**< suspend device */ +#define RT_DEVICE_CTRL_CONFIG 0x03 /**< configure device */ + +#define RT_DEVICE_CTRL_SET_INT 0x10 /**< set interrupt */ +#define RT_DEVICE_CTRL_CLR_INT 0x11 /**< clear interrupt */ +#define RT_DEVICE_CTRL_GET_INT 0x12 /**< get interrupt status */ + +/** + * special device commands + */ +#define RT_DEVICE_CTRL_CHAR_STREAM 0x10 /**< stream mode on char device */ +#define RT_DEVICE_CTRL_BLK_GETGEOME 0x10 /**< get geometry information */ +#define RT_DEVICE_CTRL_BLK_SYNC 0x11 /**< flush data to block device */ +#define RT_DEVICE_CTRL_BLK_ERASE 0x12 /**< erase block on block device */ +#define RT_DEVICE_CTRL_BLK_AUTOREFRESH 0x13 /**< block device : enter/exit auto refresh mode */ +#define RT_DEVICE_CTRL_NETIF_GETMAC 0x10 /**< get mac address */ +#define RT_DEVICE_CTRL_MTD_FORMAT 0x10 /**< format a MTD device */ +#define RT_DEVICE_CTRL_RTC_GET_TIME 0x10 /**< get time */ +#define RT_DEVICE_CTRL_RTC_SET_TIME 0x11 /**< set time */ +#define RT_DEVICE_CTRL_RTC_GET_ALARM 0x12 /**< get alarm */ +#define RT_DEVICE_CTRL_RTC_SET_ALARM 0x13 /**< set alarm */ + +typedef struct rt_device *rt_device_t; +/** + * operations set for device object + */ +struct rt_device_ops +{ + /* common device interface */ + rt_err_t (*init) (rt_device_t dev); + rt_err_t (*open) (rt_device_t dev, rt_uint16_t oflag); + rt_err_t (*close) (rt_device_t dev); + rt_size_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); + rt_size_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); + rt_err_t (*control)(rt_device_t dev, int cmd, void *args); +}; + +/** + * WaitQueue structure + */ +struct rt_wqueue +{ + rt_uint32_t flag; + rt_list_t waiting_list; +}; +typedef struct rt_wqueue rt_wqueue_t; + +/** + * Device structure + */ +struct rt_device +{ + struct rt_object parent; /**< inherit from rt_object */ + + enum rt_device_class_type type; /**< device type */ + rt_uint16_t flag; /**< device flag */ + rt_uint16_t open_flag; /**< device open flag */ + + rt_uint8_t ref_count; /**< reference count */ + rt_uint8_t device_id; /**< 0 - 255 */ + + /* device call back */ + rt_err_t (*rx_indicate)(rt_device_t dev, rt_size_t size); + rt_err_t (*tx_complete)(rt_device_t dev, void *buffer); + +#ifdef RT_USING_DEVICE_OPS + const struct rt_device_ops *ops; +#else + /* common device interface */ + rt_err_t (*init) (rt_device_t dev); + rt_err_t (*open) (rt_device_t dev, rt_uint16_t oflag); + rt_err_t (*close) (rt_device_t dev); + rt_size_t (*read) (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); + rt_size_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); + rt_err_t (*control)(rt_device_t dev, int cmd, void *args); +#endif + +#if defined(RT_USING_POSIX) + const struct dfs_file_ops *fops; + struct rt_wqueue wait_queue; +#endif + + void *user_data; /**< device private data */ +}; + +/** + * block device geometry structure + */ +struct rt_device_blk_geometry +{ + rt_uint32_t sector_count; /**< count of sectors */ + rt_uint32_t bytes_per_sector; /**< number of bytes per sector */ + rt_uint32_t block_size; /**< number of bytes to erase one block */ +}; + +/** + * sector arrange struct on block device + */ +struct rt_device_blk_sectors +{ + rt_uint32_t sector_begin; /**< begin sector */ + rt_uint32_t sector_end; /**< end sector */ +}; + +/** + * cursor control command + */ +#define RT_DEVICE_CTRL_CURSOR_SET_POSITION 0x10 +#define RT_DEVICE_CTRL_CURSOR_SET_TYPE 0x11 + +/** + * graphic device control command + */ +#define RTGRAPHIC_CTRL_RECT_UPDATE 0 +#define RTGRAPHIC_CTRL_POWERON 1 +#define RTGRAPHIC_CTRL_POWEROFF 2 +#define RTGRAPHIC_CTRL_GET_INFO 3 +#define RTGRAPHIC_CTRL_SET_MODE 4 +#define RTGRAPHIC_CTRL_GET_EXT 5 + +/* graphic deice */ +enum +{ + RTGRAPHIC_PIXEL_FORMAT_MONO = 0, + RTGRAPHIC_PIXEL_FORMAT_GRAY4, + RTGRAPHIC_PIXEL_FORMAT_GRAY16, + RTGRAPHIC_PIXEL_FORMAT_RGB332, + RTGRAPHIC_PIXEL_FORMAT_RGB444, + RTGRAPHIC_PIXEL_FORMAT_RGB565, + RTGRAPHIC_PIXEL_FORMAT_RGB565P, + RTGRAPHIC_PIXEL_FORMAT_BGR565 = RTGRAPHIC_PIXEL_FORMAT_RGB565P, + RTGRAPHIC_PIXEL_FORMAT_RGB666, + RTGRAPHIC_PIXEL_FORMAT_RGB888, + RTGRAPHIC_PIXEL_FORMAT_ARGB888, + RTGRAPHIC_PIXEL_FORMAT_ABGR888, + RTGRAPHIC_PIXEL_FORMAT_ARGB565, + RTGRAPHIC_PIXEL_FORMAT_ALPHA, + RTGRAPHIC_PIXEL_FORMAT_COLOR, +}; + +/** + * build a pixel position according to (x, y) coordinates. + */ +#define RTGRAPHIC_PIXEL_POSITION(x, y) ((x << 16) | y) + +/** + * graphic device information structure + */ +struct rt_device_graphic_info +{ + rt_uint8_t pixel_format; /**< graphic format */ + rt_uint8_t bits_per_pixel; /**< bits per pixel */ + rt_uint16_t reserved; /**< reserved field */ + + rt_uint16_t width; /**< width of graphic device */ + rt_uint16_t height; /**< height of graphic device */ + + rt_uint8_t *framebuffer; /**< frame buffer */ +}; + +/** + * rectangle information structure + */ +struct rt_device_rect_info +{ + rt_uint16_t x; /**< x coordinate */ + rt_uint16_t y; /**< y coordinate */ + rt_uint16_t width; /**< width */ + rt_uint16_t height; /**< height */ +}; + +/** + * graphic operations + */ +struct rt_device_graphic_ops +{ + void (*set_pixel) (const char *pixel, int x, int y); + void (*get_pixel) (char *pixel, int x, int y); + + void (*draw_hline)(const char *pixel, int x1, int x2, int y); + void (*draw_vline)(const char *pixel, int x, int y1, int y2); + + void (*blit_line) (const char *pixel, int x, int y, rt_size_t size); +}; +#define rt_graphix_ops(device) ((struct rt_device_graphic_ops *)(device->user_data)) + +/**@}*/ +#endif + +/* definitions for libc */ +#if defined (RT_USING_MINILIBC) || (RT_USING_LIBC) +/* definitions for libc */ +#include "rtlibc.h" +#endif + +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus +/* RT-Thread definitions for C++ */ +namespace rtthread { + +enum TICK_WAIT { + WAIT_NONE = 0, + WAIT_FOREVER = -1, +}; + +} + +#endif /* end of __cplusplus */ + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rthw.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rthw.h new file mode 100644 index 0000000000..3e74df0f22 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rthw.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-18 Bernard the first version + * 2006-04-25 Bernard add rt_hw_context_switch_interrupt declaration + * 2006-09-24 Bernard add rt_hw_context_switch_to declaration + * 2012-12-29 Bernard add rt_hw_exception_install declaration + * 2017-10-17 Hichard add some micros + */ + +#ifndef __RT_HW_H__ +#define __RT_HW_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Some macros define + */ +#ifndef HWREG32 +#define HWREG32(x) (*((volatile rt_uint32_t *)(x))) +#endif +#ifndef HWREG16 +#define HWREG16(x) (*((volatile rt_uint16_t *)(x))) +#endif +#ifndef HWREG8 +#define HWREG8(x) (*((volatile rt_uint8_t *)(x))) +#endif + +#ifndef RT_CPU_CACHE_LINE_SZ +#define RT_CPU_CACHE_LINE_SZ 32 +#endif + +enum RT_HW_CACHE_OPS +{ + RT_HW_CACHE_FLUSH = 0x01, + RT_HW_CACHE_INVALIDATE = 0x02, +}; + +/* + * CPU interfaces + */ +void rt_hw_cpu_icache_enable(void); +void rt_hw_cpu_icache_disable(void); +rt_base_t rt_hw_cpu_icache_status(void); +void rt_hw_cpu_icache_ops(int ops, void* addr, int size); + +void rt_hw_cpu_dcache_enable(void); +void rt_hw_cpu_dcache_disable(void); +rt_base_t rt_hw_cpu_dcache_status(void); +void rt_hw_cpu_dcache_ops(int ops, void* addr, int size); + +void rt_hw_cpu_reset(void); +void rt_hw_cpu_shutdown(void); + +rt_uint8_t *rt_hw_stack_init(void *entry, + void *parameter, + rt_uint8_t *stack_addr, + void *exit); + +/* + * Interrupt handler definition + */ +typedef void (*rt_isr_handler_t)(int vector, void *param); + +struct rt_irq_desc +{ + rt_isr_handler_t handler; + void *param; + +#ifdef RT_USING_INTERRUPT_INFO + char name[RT_NAME_MAX]; + rt_uint32_t counter; +#endif +}; + +/* + * Interrupt interfaces + */ +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); +rt_isr_handler_t rt_hw_interrupt_install(int vector, + rt_isr_handler_t handler, + void *param, + const char *name); + +rt_base_t rt_hw_interrupt_disable(void); +void rt_hw_interrupt_enable(rt_base_t level); + +/* + * Context interfaces + */ +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to); +void rt_hw_context_switch_to(rt_uint32_t to); +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to); + +void rt_hw_console_output(const char *str); + +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry); +void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size); + +/* + * Exception interfaces + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)); + +/* + * delay interfaces + */ +void rt_hw_us_delay(rt_uint32_t us); + +#define RT_DEFINE_SPINLOCK(x) +#define RT_DECLARE_SPINLOCK(x) rt_ubase_t x + +#define rt_hw_spin_lock(lock) *(lock) = rt_hw_interrupt_disable() +#define rt_hw_spin_unlock(lock) rt_hw_interrupt_enable(*(lock)) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtlibc.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtlibc.h new file mode 100644 index 0000000000..b3a548beb1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtlibc.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-01-21 Bernard the first version + */ + +#ifndef RTLIBC_H__ +#define RTLIBC_H__ + +/* definitions for libc if toolchain has no these definitions */ +#include "libc/libc_stat.h" +#include "libc/libc_errno.h" + +#include "libc/libc_fcntl.h" +#include "libc/libc_ioctl.h" +#include "libc/libc_dirent.h" +#include "libc/libc_signal.h" +#include "libc/libc_fdset.h" + +#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined(__IAR_SYSTEMS_ICC__) +typedef signed long off_t; +typedef int mode_t; +#endif + +#if defined(__MINGW32__) || defined(_WIN32) +typedef signed long off_t; +typedef int mode_t; +#endif + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtm.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtm.h new file mode 100644 index 0000000000..7e07a2239c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtm.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RTM_H__ +#define __RTM_H__ + +#include +#include + +#ifdef RT_USING_MODULE +struct rt_module_symtab +{ + void *addr; + const char *name; +}; + +#if defined(_MSC_VER) +#pragma section("RTMSymTab$f",read) +#define RTM_EXPORT(symbol) \ +__declspec(allocate("RTMSymTab$f"))const char __rtmsym_##symbol##_name[] = "__vs_rtm_"#symbol; +#pragma comment(linker, "/merge:RTMSymTab=mytext") + +#elif defined(__MINGW32__) +#define RTM_EXPORT(symbol) + +#else +#define RTM_EXPORT(symbol) \ +const char __rtmsym_##symbol##_name[] SECTION(".rodata.name") = #symbol; \ +const struct rt_module_symtab __rtmsym_##symbol SECTION("RTMSymTab")= \ +{ \ + (void *)&symbol, \ + __rtmsym_##symbol##_name \ +}; +#endif + +#else +#define RTM_EXPORT(symbol) +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtservice.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtservice.h new file mode 100644 index 0000000000..81d6c71f17 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtservice.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-16 Bernard the first version + * 2006-09-07 Bernard move the kservice APIs to rtthread.h + * 2007-06-27 Bernard fix the rt_list_remove bug + * 2012-03-22 Bernard rename kservice.h to rtservice.h + * 2017-11-15 JasonJia Modify rt_slist_foreach to rt_slist_for_each_entry. + * Make code cleanup. + */ + +#ifndef __RT_SERVICE_H__ +#define __RT_SERVICE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup KernelService + */ + +/**@{*/ + +/** + * rt_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define rt_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + + +/** + * @brief initialize a list object + */ +#define RT_LIST_OBJECT_INIT(object) { &(object), &(object) } + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +rt_inline void rt_list_init(rt_list_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +rt_inline void rt_list_insert_after(rt_list_t *l, rt_list_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +rt_inline void rt_list_insert_before(rt_list_t *l, rt_list_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +rt_inline void rt_list_remove(rt_list_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +rt_inline int rt_list_isempty(const rt_list_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +rt_inline unsigned int rt_list_len(const rt_list_t *l) +{ + unsigned int len = 0; + const rt_list_t *p = l; + while (p->next != l) + { + p = p->next; + len ++; + } + + return len; +} + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define rt_list_entry(node, type, member) \ + rt_container_of(node, type, member) + +/** + * rt_list_for_each - iterate over a list + * @pos: the rt_list_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define rt_list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * rt_list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the rt_list_t * to use as a loop cursor. + * @n: another rt_list_t * to use as temporary storage + * @head: the head for your list. + */ +#define rt_list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * rt_list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define rt_list_for_each_entry(pos, head, member) \ + for (pos = rt_list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = rt_list_entry(pos->member.next, typeof(*pos), member)) + +/** + * rt_list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define rt_list_for_each_entry_safe(pos, n, head, member) \ + for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ + n = rt_list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) + +/** + * rt_list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define rt_list_first_entry(ptr, type, member) \ + rt_list_entry((ptr)->next, type, member) + +#define RT_SLIST_OBJECT_INIT(object) { RT_NULL } + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +rt_inline void rt_slist_init(rt_slist_t *l) +{ + l->next = RT_NULL; +} + +rt_inline void rt_slist_append(rt_slist_t *l, rt_slist_t *n) +{ + struct rt_slist_node *node; + + node = l; + while (node->next) node = node->next; + + /* append the node to the tail */ + node->next = n; + n->next = RT_NULL; +} + +rt_inline void rt_slist_insert(rt_slist_t *l, rt_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +rt_inline unsigned int rt_slist_len(const rt_slist_t *l) +{ + unsigned int len = 0; + const rt_slist_t *list = l->next; + while (list != RT_NULL) + { + list = list->next; + len ++; + } + + return len; +} + +rt_inline rt_slist_t *rt_slist_remove(rt_slist_t *l, rt_slist_t *n) +{ + /* remove slist head */ + struct rt_slist_node *node = l; + while (node->next && node->next != n) node = node->next; + + /* remove node */ + if (node->next != (rt_slist_t *)0) node->next = node->next->next; + + return l; +} + +rt_inline rt_slist_t *rt_slist_first(rt_slist_t *l) +{ + return l->next; +} + +rt_inline rt_slist_t *rt_slist_tail(rt_slist_t *l) +{ + while (l->next) l = l->next; + + return l; +} + +rt_inline rt_slist_t *rt_slist_next(rt_slist_t *n) +{ + return n->next; +} + +rt_inline int rt_slist_isempty(rt_slist_t *l) +{ + return l->next == RT_NULL; +} + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define rt_slist_entry(node, type, member) \ + rt_container_of(node, type, member) + +/** + * rt_slist_for_each - iterate over a single list + * @pos: the rt_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define rt_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != RT_NULL; pos = pos->next) + +/** + * rt_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define rt_slist_for_each_entry(pos, head, member) \ + for (pos = rt_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (RT_NULL); \ + pos = rt_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * rt_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define rt_slist_first_entry(ptr, type, member) \ + rt_slist_entry((ptr)->next, type, member) + +/** + * rt_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define rt_slist_tail_entry(ptr, type, member) \ + rt_slist_entry(rt_slist_tail(ptr), type, member) + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtthread.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtthread.h new file mode 100644 index 0000000000..bfe41a3e32 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/include/rtthread.h @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-18 Bernard the first version + * 2006-04-26 Bernard add semaphore APIs + * 2006-08-10 Bernard add version information + * 2007-01-28 Bernard rename RT_OBJECT_Class_Static to RT_Object_Class_Static + * 2007-03-03 Bernard clean up the definitions to rtdef.h + * 2010-04-11 yi.qiu add module feature + * 2013-06-24 Bernard add rt_kprintf re-define when not use RT_USING_CONSOLE. + * 2016-08-09 ArdaFu add new thread and interrupt hook. + */ + +#ifndef __RT_THREAD_H__ +#define __RT_THREAD_H__ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup KernelObject + */ + +/**@{*/ + +/* + * kernel object interface + */ +void rt_system_object_init(void); +struct rt_object_information * +rt_object_get_information(enum rt_object_class_type type); +void rt_object_init(struct rt_object *object, + enum rt_object_class_type type, + const char *name); +void rt_object_detach(rt_object_t object); +rt_object_t rt_object_allocate(enum rt_object_class_type type, + const char *name); +void rt_object_delete(rt_object_t object); +rt_bool_t rt_object_is_systemobject(rt_object_t object); +rt_uint8_t rt_object_get_type(rt_object_t object); +rt_object_t rt_object_find(const char *name, rt_uint8_t type); + +#ifdef RT_USING_HOOK +void rt_object_attach_sethook(void (*hook)(struct rt_object *object)); +void rt_object_detach_sethook(void (*hook)(struct rt_object *object)); +void rt_object_trytake_sethook(void (*hook)(struct rt_object *object)); +void rt_object_take_sethook(void (*hook)(struct rt_object *object)); +void rt_object_put_sethook(void (*hook)(struct rt_object *object)); +#endif + +/**@}*/ + +/** + * @addtogroup Clock + */ + +/**@{*/ + +/* + * clock & timer interface + */ +void rt_system_tick_init(void); +rt_tick_t rt_tick_get(void); +void rt_tick_set(rt_tick_t tick); +void rt_tick_increase(void); +rt_tick_t rt_tick_from_millisecond(rt_int32_t ms); + +void rt_system_timer_init(void); +void rt_system_timer_thread_init(void); + +void rt_timer_init(rt_timer_t timer, + const char *name, + void (*timeout)(void *parameter), + void *parameter, + rt_tick_t time, + rt_uint8_t flag); +rt_err_t rt_timer_detach(rt_timer_t timer); +rt_timer_t rt_timer_create(const char *name, + void (*timeout)(void *parameter), + void *parameter, + rt_tick_t time, + rt_uint8_t flag); +rt_err_t rt_timer_delete(rt_timer_t timer); +rt_err_t rt_timer_start(rt_timer_t timer); +rt_err_t rt_timer_stop(rt_timer_t timer); +rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg); + +rt_tick_t rt_timer_next_timeout_tick(void); +void rt_timer_check(void); + +#ifdef RT_USING_HOOK +void rt_timer_enter_sethook(void (*hook)(struct rt_timer *timer)); +void rt_timer_exit_sethook(void (*hook)(struct rt_timer *timer)); +#endif + +/**@}*/ + +/** + * @addtogroup Thread + */ + +/**@{*/ + +/* + * thread interface + */ +rt_err_t rt_thread_init(struct rt_thread *thread, + const char *name, + void (*entry)(void *parameter), + void *parameter, + void *stack_start, + rt_uint32_t stack_size, + rt_uint8_t priority, + rt_uint32_t tick); +rt_err_t rt_thread_detach(rt_thread_t thread); +rt_thread_t rt_thread_create(const char *name, + void (*entry)(void *parameter), + void *parameter, + rt_uint32_t stack_size, + rt_uint8_t priority, + rt_uint32_t tick); +rt_thread_t rt_thread_self(void); +rt_thread_t rt_thread_find(char *name); +rt_err_t rt_thread_startup(rt_thread_t thread); +rt_err_t rt_thread_delete(rt_thread_t thread); + +rt_err_t rt_thread_yield(void); +rt_err_t rt_thread_delay(rt_tick_t tick); +rt_err_t rt_thread_mdelay(rt_int32_t ms); +rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg); +rt_err_t rt_thread_suspend(rt_thread_t thread); +rt_err_t rt_thread_resume(rt_thread_t thread); +void rt_thread_timeout(void *parameter); + +#ifdef RT_USING_SIGNALS +void rt_thread_alloc_sig(rt_thread_t tid); +void rt_thread_free_sig(rt_thread_t tid); +int rt_thread_kill(rt_thread_t tid, int sig); +#endif + +#ifdef RT_USING_HOOK +void rt_thread_suspend_sethook(void (*hook)(rt_thread_t thread)); +void rt_thread_resume_sethook (void (*hook)(rt_thread_t thread)); +void rt_thread_inited_sethook (void (*hook)(rt_thread_t thread)); +#endif + +/* + * idle thread interface + */ +void rt_thread_idle_init(void); +#if defined(RT_USING_HOOK) || defined(RT_USING_IDLE_HOOK) +rt_err_t rt_thread_idle_sethook(void (*hook)(void)); +rt_err_t rt_thread_idle_delhook(void (*hook)(void)); +#endif +void rt_thread_idle_excute(void); +rt_thread_t rt_thread_idle_gethandler(void); + +/* + * schedule service + */ +void rt_system_scheduler_init(void); +void rt_system_scheduler_start(void); + +void rt_schedule(void); +void rt_schedule_insert_thread(struct rt_thread *thread); +void rt_schedule_remove_thread(struct rt_thread *thread); + +void rt_enter_critical(void); +void rt_exit_critical(void); +rt_uint16_t rt_critical_level(void); + +#ifdef RT_USING_HOOK +void rt_scheduler_sethook(void (*hook)(rt_thread_t from, rt_thread_t to)); +#endif + +/**@}*/ + +/** + * @addtogroup Signals + * @{ + */ +#ifdef RT_USING_SIGNALS +void rt_signal_mask(int signo); +void rt_signal_unmask(int signo); +rt_sighandler_t rt_signal_install(int signo, rt_sighandler_t handler); +int rt_signal_wait(const rt_sigset_t *set, rt_siginfo_t *si, rt_int32_t timeout); + +int rt_system_signal_init(void); +#endif +/*@}*/ + +/** + * @addtogroup MM + */ + +/**@{*/ + +/* + * memory management interface + */ +#ifdef RT_USING_MEMPOOL +/* + * memory pool interface + */ +rt_err_t rt_mp_init(struct rt_mempool *mp, + const char *name, + void *start, + rt_size_t size, + rt_size_t block_size); +rt_err_t rt_mp_detach(struct rt_mempool *mp); +rt_mp_t rt_mp_create(const char *name, + rt_size_t block_count, + rt_size_t block_size); +rt_err_t rt_mp_delete(rt_mp_t mp); + +void *rt_mp_alloc(rt_mp_t mp, rt_int32_t time); +void rt_mp_free(void *block); + +#ifdef RT_USING_HOOK +void rt_mp_alloc_sethook(void (*hook)(struct rt_mempool *mp, void *block)); +void rt_mp_free_sethook(void (*hook)(struct rt_mempool *mp, void *block)); +#endif + +#endif + +#ifdef RT_USING_HEAP +/* + * heap memory interface + */ +void rt_system_heap_init(void *begin_addr, void *end_addr); + +void *rt_malloc(rt_size_t nbytes); +void rt_free(void *ptr); +void *rt_realloc(void *ptr, rt_size_t nbytes); +void *rt_calloc(rt_size_t count, rt_size_t size); +void *rt_malloc_align(rt_size_t size, rt_size_t align); +void rt_free_align(void *ptr); + +void rt_memory_info(rt_uint32_t *total, + rt_uint32_t *used, + rt_uint32_t *max_used); + +#ifdef RT_USING_SLAB +void *rt_page_alloc(rt_size_t npages); +void rt_page_free(void *addr, rt_size_t npages); +#endif + +#ifdef RT_USING_HOOK +void rt_malloc_sethook(void (*hook)(void *ptr, rt_size_t size)); +void rt_free_sethook(void (*hook)(void *ptr)); +#endif + +#endif + +#ifdef RT_USING_MEMHEAP +/** + * memory heap object interface + */ +rt_err_t rt_memheap_init(struct rt_memheap *memheap, + const char *name, + void *start_addr, + rt_size_t size); +rt_err_t rt_memheap_detach(struct rt_memheap *heap); +void *rt_memheap_alloc(struct rt_memheap *heap, rt_size_t size); +void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize); +void rt_memheap_free(void *ptr); +#endif + +/**@}*/ + +/** + * @addtogroup IPC + */ + +/**@{*/ + +#ifdef RT_USING_SEMAPHORE +/* + * semaphore interface + */ +rt_err_t rt_sem_init(rt_sem_t sem, + const char *name, + rt_uint32_t value, + rt_uint8_t flag); +rt_err_t rt_sem_detach(rt_sem_t sem); +rt_sem_t rt_sem_create(const char *name, rt_uint32_t value, rt_uint8_t flag); +rt_err_t rt_sem_delete(rt_sem_t sem); + +rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time); +rt_err_t rt_sem_trytake(rt_sem_t sem); +rt_err_t rt_sem_release(rt_sem_t sem); +rt_err_t rt_sem_control(rt_sem_t sem, int cmd, void *arg); +#endif + +#ifdef RT_USING_MUTEX +/* + * mutex interface + */ +rt_err_t rt_mutex_init(rt_mutex_t mutex, const char *name, rt_uint8_t flag); +rt_err_t rt_mutex_detach(rt_mutex_t mutex); +rt_mutex_t rt_mutex_create(const char *name, rt_uint8_t flag); +rt_err_t rt_mutex_delete(rt_mutex_t mutex); + +rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time); +rt_err_t rt_mutex_release(rt_mutex_t mutex); +rt_err_t rt_mutex_control(rt_mutex_t mutex, int cmd, void *arg); +#endif + +#ifdef RT_USING_EVENT +/* + * event interface + */ +rt_err_t rt_event_init(rt_event_t event, const char *name, rt_uint8_t flag); +rt_err_t rt_event_detach(rt_event_t event); +rt_event_t rt_event_create(const char *name, rt_uint8_t flag); +rt_err_t rt_event_delete(rt_event_t event); + +rt_err_t rt_event_send(rt_event_t event, rt_uint32_t set); +rt_err_t rt_event_recv(rt_event_t event, + rt_uint32_t set, + rt_uint8_t opt, + rt_int32_t timeout, + rt_uint32_t *recved); +rt_err_t rt_event_control(rt_event_t event, int cmd, void *arg); +#endif + +#ifdef RT_USING_MAILBOX +/* + * mailbox interface + */ +rt_err_t rt_mb_init(rt_mailbox_t mb, + const char *name, + void *msgpool, + rt_size_t size, + rt_uint8_t flag); +rt_err_t rt_mb_detach(rt_mailbox_t mb); +rt_mailbox_t rt_mb_create(const char *name, rt_size_t size, rt_uint8_t flag); +rt_err_t rt_mb_delete(rt_mailbox_t mb); + +rt_err_t rt_mb_send(rt_mailbox_t mb, rt_uint32_t value); +rt_err_t rt_mb_send_wait(rt_mailbox_t mb, + rt_uint32_t value, + rt_int32_t timeout); +rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_uint32_t *value, rt_int32_t timeout); +rt_err_t rt_mb_control(rt_mailbox_t mb, int cmd, void *arg); +#endif + +#ifdef RT_USING_MESSAGEQUEUE +/* + * message queue interface + */ +rt_err_t rt_mq_init(rt_mq_t mq, + const char *name, + void *msgpool, + rt_size_t msg_size, + rt_size_t pool_size, + rt_uint8_t flag); +rt_err_t rt_mq_detach(rt_mq_t mq); +rt_mq_t rt_mq_create(const char *name, + rt_size_t msg_size, + rt_size_t max_msgs, + rt_uint8_t flag); +rt_err_t rt_mq_delete(rt_mq_t mq); + +rt_err_t rt_mq_send(rt_mq_t mq, void *buffer, rt_size_t size); +rt_err_t rt_mq_urgent(rt_mq_t mq, void *buffer, rt_size_t size); +rt_err_t rt_mq_recv(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout); +rt_err_t rt_mq_control(rt_mq_t mq, int cmd, void *arg); +#endif + +/**@}*/ + +#ifdef RT_USING_DEVICE +/** + * @addtogroup Device + */ + +/**@{*/ + +/* + * device (I/O) system interface + */ +rt_device_t rt_device_find(const char *name); + +rt_err_t rt_device_register(rt_device_t dev, + const char *name, + rt_uint16_t flags); +rt_err_t rt_device_unregister(rt_device_t dev); + +rt_device_t rt_device_create(int type, int attach_size); +void rt_device_destroy(rt_device_t device); + +rt_err_t rt_device_init_all(void); + +rt_err_t +rt_device_set_rx_indicate(rt_device_t dev, + rt_err_t (*rx_ind)(rt_device_t dev, rt_size_t size)); +rt_err_t +rt_device_set_tx_complete(rt_device_t dev, + rt_err_t (*tx_done)(rt_device_t dev, void *buffer)); + +rt_err_t rt_device_init (rt_device_t dev); +rt_err_t rt_device_open (rt_device_t dev, rt_uint16_t oflag); +rt_err_t rt_device_close(rt_device_t dev); +rt_size_t rt_device_read (rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size); +rt_size_t rt_device_write(rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size); +rt_err_t rt_device_control(rt_device_t dev, int cmd, void *arg); + +/**@}*/ +#endif + +/* + * interrupt service + */ + +/* + * rt_interrupt_enter and rt_interrupt_leave only can be called by BSP + */ +void rt_interrupt_enter(void); +void rt_interrupt_leave(void); + +/* + * the number of nested interrupts. + */ +rt_uint8_t rt_interrupt_get_nest(void); + +#ifdef RT_USING_HOOK +void rt_interrupt_enter_sethook(void (*hook)(void)); +void rt_interrupt_leave_sethook(void (*hook)(void)); +#endif + +#ifdef RT_USING_COMPONENTS_INIT +void rt_components_init(void); +void rt_components_board_init(void); +#endif + +/** + * @addtogroup KernelService + */ + +/**@{*/ + +/* + * general kernel service + */ +#ifndef RT_USING_CONSOLE +#define rt_kprintf(...) +#define rt_kputs(str) +#else +void rt_kprintf(const char *fmt, ...); +void rt_kputs(const char *str); +#endif +rt_int32_t rt_vsprintf(char *dest, const char *format, va_list arg_ptr); +rt_int32_t rt_vsnprintf(char *buf, rt_size_t size, const char *fmt, va_list args); +rt_int32_t rt_sprintf(char *buf, const char *format, ...); +rt_int32_t rt_snprintf(char *buf, rt_size_t size, const char *format, ...); + +#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE) +rt_device_t rt_console_set_device(const char *name); +rt_device_t rt_console_get_device(void); +#endif + +rt_err_t rt_get_errno(void); +void rt_set_errno(rt_err_t no); +int *_rt_errno(void); +#if !defined(RT_USING_NEWLIB) && !defined(_WIN32) +#ifndef errno +#define errno *_rt_errno() +#endif +#endif + +int __rt_ffs(int value); + +void *rt_memset(void *src, int c, rt_ubase_t n); +void *rt_memcpy(void *dest, const void *src, rt_ubase_t n); + +rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_ubase_t count); +rt_int32_t rt_strcmp(const char *cs, const char *ct); +rt_size_t rt_strlen(const char *src); +rt_size_t rt_strnlen(const char *s, rt_ubase_t maxlen); +char *rt_strdup(const char *s); +#if defined(__CC_ARM) || defined(__CLANG_ARM) +/* leak strdup interface */ +char* strdup(const char* str); +#endif + +char *rt_strstr(const char *str1, const char *str2); +rt_int32_t rt_sscanf(const char *buf, const char *fmt, ...); +char *rt_strncpy(char *dest, const char *src, rt_ubase_t n); +void *rt_memmove(void *dest, const void *src, rt_ubase_t n); +rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_ubase_t count); +rt_uint32_t rt_strcasecmp(const char *a, const char *b); + +void rt_show_version(void); + +#ifdef RT_DEBUG +extern void (*rt_assert_hook)(const char *ex, const char *func, rt_size_t line); +void rt_assert_set_hook(void (*hook)(const char *ex, const char *func, rt_size_t line)); + +void rt_assert_handler(const char *ex, const char *func, rt_size_t line); +#endif /* RT_DEBUG */ + +#ifdef RT_USING_FINSH +#include +#endif + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_gcc.S new file mode 100644 index 0000000000..b6b7863679 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_gcc.S @@ -0,0 +1,78 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2011-08-14 weety copy from mini2440 +; */ + +#define NOINT 0xC0 + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS R0, CPSR + ORR R1, R0, #NOINT + MSR CPSR_c, R1 + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR CPSR, R0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + STMFD SP!, {LR} @; push pc (lr should be pushed in place of pc) + STMFD SP!, {R0-R12, LR} @; push lr & register file + MRS R4, CPSR + STMFD SP!, {R4} @; push cpsr + STR SP, [R0] @; store sp in preempted tasks tcb + LDR SP, [R1] @; get new task stack pointer + LDMFD SP!, {R4} @; pop new task spsr + MSR SPSR_cxsf, R4 + LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR SP, [R0] @; get new task stack pointer + LDMFD SP!, {R4} @; pop new task cpsr + MSR SPSR_cxsf, R4 + LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOV R3, #1 @; set flag to 1 + STR R3, [R2] + LDR R2, =rt_interrupt_from_thread @; set rt_interrupt_from_thread + STR R0, [R2] +_reswitch: + LDR R2, =rt_interrupt_to_thread @; set rt_interrupt_to_thread + STR R1, [R2] + BX LR diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_iar.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_iar.S new file mode 100644 index 0000000000..902552734e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_iar.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-08-14 weety copy from mini2440 + * 2015-04-15 ArdaFu convert from context_gcc.s + */ + +#define NOINT 0xc0 + + SECTION .text:CODE(6) +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + PUBLIC rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS R0, CPSR + ORR R1, R0, #NOINT + MSR CPSR_C, R1 + MOV PC, LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + PUBLIC rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR CPSR_CXSF, R0 + MOV PC, LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ + PUBLIC rt_hw_context_switch +rt_hw_context_switch: + STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC) + STMFD SP!, {R0-R12, LR} ; push lr & register file + MRS R4, CPSR + STMFD SP!, {R4} ; push cpsr + STR SP, [R0] ; store sp in preempted tasks TCB + LDR SP, [R1] ; get new task stack pointer + LDMFD SP!, {R4} ; pop new task spsr + MSR SPSR_cxsf, R4 + LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ + PUBLIC rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR SP, [R0] ; get new task stack pointer + LDMFD SP!, {R4} ; pop new task spsr + MSR SPSR_cxsf, R4 + LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + PUBLIC rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOV R3, #1 ; set flag to 1 + STR R3, [R2] + LDR R2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR R0, [R2] +_reswitch: + LDR R2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR R1, [R2] + MOV PC, LR + END + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_rvds.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_rvds.S new file mode 100644 index 0000000000..03eff68d4c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/context_rvds.S @@ -0,0 +1,91 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2011-08-14 weety copy from mini2440 +; */ + +NOINT EQU 0XC0 ; disable interrupt in psr + + AREA |.TEXT|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS R0, CPSR + ORR R1, R0, #NOINT + MSR CPSR_C, R1 + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable proc + export rt_hw_interrupt_enable + msr cpsr_c, r0 + bx lr + endp + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch proc + export rt_hw_context_switch + stmfd sp!, {lr} ; push pc (lr should be pushed in place of pc) + stmfd sp!, {r0-r12, lr} ; push lr & register file + mrs r4, cpsr + stmfd sp!, {r4} ; push cpsr + str sp, [r0] ; store sp in preempted tasks tcb + ldr sp, [r1] ; get new task stack pointer + ldmfd sp!, {r4} ; pop new task spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc + endp + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ +rt_hw_context_switch_to proc + export rt_hw_context_switch_to + ldr sp, [r0] ; get new task stack pointer + ldmfd sp!, {r4} ; pop new task spsr + msr spsr_cxsf, r4 + ldmfd sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc + endp + +;/* +; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); +; */ + import rt_thread_switch_interrupt_flag + import rt_interrupt_from_thread + import rt_interrupt_to_thread + +rt_hw_context_switch_interrupt proc + export rt_hw_context_switch_interrupt + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + mov r3, #1 ; set flag to 1 + str r3, [r2] + ldr r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + str r0, [r2] +_reswitch + ldr r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + str r1, [r2] + bx lr + endp + + end diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/cpuport.c new file mode 100644 index 0000000000..1efb23e896 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/cpuport.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + * 2015-04-15 ArdaFu Add code for IAR + */ + +#include +#include + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +extern void machine_reset(void); +extern void machine_shutdown(void); + +#if defined(__GNUC__) || defined(__ICCARM__) +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm volatile(\ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm volatile(\ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#if defined(__CC_ARM) +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm volatile + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + + rt_kprintf("Restarting system...\n"); + machine_reset(); + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +#if defined(__CC_ARM) +int __rt_ffs(int value) +{ + register rt_uint32_t x; + + if (value == 0) + return value; + + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } + + return x; +} +#elif defined(__GNUC__) || defined(__ICCARM__) +int __rt_ffs(int value) +{ + register rt_uint32_t x; + + if (value == 0) + return value; + + __asm + ( + "rsb %[temp], %[val], #0\n" + "and %[temp], %[temp], %[val]\n" + "clz %[temp], %[temp]\n" + "rsb %[temp], %[temp], #32\n" + :[temp] "=r"(x) + :[val] "r"(value) + ); + return x; +} +#endif + +#endif + + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/mmu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/mmu.c new file mode 100644 index 0000000000..f1e475189b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/mmu.c @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2015-04-15 ArdaFu Add code for IAR + */ + +#include "mmu.h" + +/*----- Keil -----------------------------------------------------------------*/ +#ifdef __CC_ARM +void mmu_setttbase(rt_uint32_t i) +{ + register rt_uint32_t value; + + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + __asm volatile{ mcr p15, 0, value, c8, c7, 0 } + value = 0x55555555; + __asm volatile { mcr p15, 0, value, c3, c0, 0 } + __asm volatile { mcr p15, 0, i, c2, c0, 0 } +} + +void mmu_set_domain(rt_uint32_t i) +{ + __asm volatile { mcr p15, 0, i, c3, c0, 0 } +} + +void mmu_enable() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_icache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_dcache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_icache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_dcache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_clean_invalidated_cache_index(int index) +{ + __asm volatile { mcr p15, 0, index, c7, c14, 2 } +} + +void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while(ptr < buffer + size) + { + __asm volatile { MCR p15, 0, ptr, c7, c14, 1 } + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + __asm volatile { MCR p15, 0, ptr, c7, c10, 1 } + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + __asm volatile { MCR p15, 0, ptr, c7, c6, 1 } + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_tlb() +{ + register rt_uint32_t value; + + value = 0; + __asm volatile { mcr p15, 0, value, c8, c7, 0 } +} + +void mmu_invalidate_icache() +{ + register rt_uint32_t value; + + value = 0; + + __asm volatile { mcr p15, 0, value, c7, c5, 0 } +} + + +void mmu_invalidate_dcache_all() +{ + register rt_uint32_t value; + + value = 0; + + __asm volatile { mcr p15, 0, value, c7, c6, 0 } +} +/*----- GNU ------------------------------------------------------------------*/ +#elif defined(__GNUC__) || defined(__ICCARM__) +void mmu_setttbase(register rt_uint32_t i) +{ + register rt_uint32_t value; + + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + +} + +void mmu_set_domain(register rt_uint32_t i) +{ + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); +} + +void mmu_enable() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "orr r0, r0, #0x1 \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); +} + +void mmu_disable() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "bic r0, r0, #0x1 \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); + +} + +void mmu_enable_icache() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "orr r0, r0, #(1<<12) \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); +} + +void mmu_enable_dcache() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "orr r0, r0, #(1<<2) \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); + +} + +void mmu_disable_icache() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "bic r0, r0, #(1<<12) \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); + +} + +void mmu_disable_dcache() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "bic r0, r0, #(1<<2) \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); + +} + +void mmu_enable_alignfault() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "orr r0, r0, #1 \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); + +} + +void mmu_disable_alignfault() +{ + asm volatile + ( + "mrc p15, 0, r0, c1, c0, 0 \n" + "bic r0, r0, #1 \n" + "mcr p15, 0, r0, c1, c0, 0 \n" + :::"r0" + ); + +} + +void mmu_clean_invalidated_cache_index(int index) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); +} + +void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while(ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + + ptr += CACHE_LINE_SIZE; + } +} + + +void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_tlb() +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + +} + +void mmu_invalidate_icache() +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + +} + +void mmu_invalidate_dcache_all() +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); + +} +#endif + +/* level1 page table */ +#if defined(__ICCARM__) +#pragma data_alignment=(16*1024) +static volatile rt_uint32_t _page_table[4*1024]; +#else +static volatile rt_uint32_t _page_table[4*1024] \ + __attribute__((aligned(16*1024))); +#endif + +void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int nSec; + int i = 0; + pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20); + nSec=(vaddrEnd>>20)-(vaddrStart>>20); + for(i=0; i<=nSec; i++) + { + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; + } +} + +void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); + + /* set page table */ + for (; size > 0; size--) + { + mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } + + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_page_table); + + /* enables MMU */ + mmu_enable(); + + /* enable Instruction Cache */ + mmu_enable_icache(); + + /* enable Data Cache */ + mmu_enable_dcache(); + + mmu_invalidate_icache(); + mmu_invalidate_dcache_all(); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/mmu.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/mmu.h new file mode 100644 index 0000000000..7b930f5358 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/mmu.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +#include + +#define CACHE_LINE_SIZE 32 + +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ + +struct mem_desc +{ + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; +}; + +void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/stack.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/stack.c new file mode 100644 index 0000000000..fa98feb824 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/stack.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety copy from mini2440 + */ +#include + +/*****************************/ +/* CPU Mode */ +/*****************************/ +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_gcc.S new file mode 100644 index 0000000000..fee8e018cb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_gcc.S @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety first version + * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP + * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table + * 2015-06-04 aozima Align stack address to 8 byte. + */ + +#include "rt_low_level_init.h" + +#define S_FRAME_SIZE (18*4) //72 + +@#define S_SPSR (17*4) //SPSR +@#define S_CPSR (16*4) //CPSR +#define S_PC (15*4) //R15 +@#define S_LR (14*4) //R14 +@#define S_SP (13*4) //R13 + +@#define S_IP (12*4) //R12 +@#define S_FP (11*4) //R11 +@#define S_R10 (10*4) +@#define S_R9 (9*4) +@#define S_R8 (8*4) +@#define S_R7 (7*4) +@#define S_R6 (6*4) +@#define S_R5 (5*4) +@#define S_R4 (4*4) +@#define S_R3 (3*4) +@#define S_R2 (2*4) +@#define S_R1 (1*4) +@#define S_R0 (0*4) + +#define MODE_SYS 0x1F +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_ABT 0x17 +#define MODE_UND 0x1B +#define MODEMASK 0x1F + +#define NOINT 0xC0 + +@;----------------------- Stack and Heap Definitions --------------------------- + .section .nobss, "w" + + .space UND_STK_SIZE + .align 3 + .global UND_STACK_START +UND_STACK_START: + + .space ABT_STK_SIZE + .align 3 + .global ABT_STACK_START +ABT_STACK_START: + + .space FIQ_STK_SIZE + .align 3 + .global FIQ_STACK_START +FIQ_STACK_START: + + .space IRQ_STK_SIZE + .align 3 + .global IRQ_STACK_START +IRQ_STACK_START: + + .skip SYS_STK_SIZE + .align 3 + .global SYS_STACK_START +SYS_STACK_START: + + .space SVC_STK_SIZE + .align 3 + .global SVC_STACK_START +SVC_STACK_START: + +@;--------------Jump vector table----------------------------------------------- + .section .init, "ax" + .arm + + .global start +start: + LDR PC, vector_reset + LDR PC, vector_undef + LDR PC, vector_swi + LDR PC, vector_pabt + LDR PC, vector_dabt + LDR PC, vector_resv + LDR PC, vector_irq + LDR PC, vector_fiq + +vector_reset: + .word Reset_Handler +vector_undef: + .word Undef_Handler +vector_swi: + .word SWI_Handler +vector_pabt: + .word PAbt_Handler +vector_dabt: + .word DAbt_Handler +vector_resv: + .word Resv_Handler +vector_irq: + .word IRQ_Handler +vector_fiq: + .word FIQ_Handler + + .balignl 16,0xdeadbeef + +@;----------------- Reset Handler --------------------------------------------- + .global rt_low_level_init + .global main + .global Reset_Handler +Reset_Handler: + @; Set the cpu to SVC32 mode + MRS R0, CPSR + BIC R0, R0, #MODEMASK + ORR R0, R0, #MODE_SVC|NOINT + MSR CPSR_cxsf, R0 + + @; Set CO-Processor + @; little-end锛宒isbale I/D Cache MMU, vector table is 0x00000000 + MRC P15, 0, R0, C1, C0, 0 @; Read CP15 + LDR R1, =0x00003085 @; set clear bits + BIC R0, R0, R1 + MCR P15, 0, R0, C1, C0, 0 @; Write CP15 + + @; Call low level init function, + @; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. + LDR SP, =SVC_STACK_START + LDR R0, =rt_low_level_init + BLX R0 + +Setup_Stack: + @; Setup Stack for each mode + MRS R0, CPSR + BIC R0, R0, #MODEMASK + + ORR R1, R0, #MODE_UND|NOINT + MSR CPSR_cxsf, R1 @; Undef mode + LDR SP, =UND_STACK_START + + ORR R1, R0, #MODE_ABT|NOINT + MSR CPSR_cxsf, R1 @; Abort mode + LDR SP, =ABT_STACK_START + + ORR R1, R0, #MODE_IRQ|NOINT + MSR CPSR_cxsf, R1 @; IRQ mode + LDR SP, =IRQ_STACK_START + + ORR R1, R0, #MODE_FIQ|NOINT + MSR CPSR_cxsf, R1 @; FIQ mode + LDR SP, =FIQ_STACK_START + + ORR R1, R0, #MODE_SYS|NOINT + MSR CPSR_cxsf,R1 @; SYS/User mode + LDR SP, =SYS_STACK_START + + ORR R1, R0, #MODE_SVC|NOINT + MSR CPSR_cxsf, R1 @; SVC mode + LDR SP, =SVC_STACK_START + + @; clear .bss + MOV R0, #0 @; get a zero + LDR R1, =__bss_start__ @; bss start + LDR R2, =__bss_end__ @; bss end + +bss_clear_loop: + CMP R1, R2 @; check if data to clear + STRLO R0, [R1], #4 @; clear 4 bytes + BLO bss_clear_loop @; loop until done + + @; call C++ constructors of global objects + LDR R0, =__ctors_start__ + LDR R1, =__ctors_end__ + +ctor_loop: + CMP R0, R1 + BEQ ctor_end + LDR R2, [R0], #4 + STMFD SP!, {R0-R1} + MOV LR, PC + BX R2 + LDMFD SP!, {R0-R1} + B ctor_loop +ctor_end: + + @; Enter the C code + LDR R0, =rtthread_startup + BLX R0 + +@;----------------- Exception Handler ----------------------------------------- + .global rt_hw_trap_udef + .global rt_hw_trap_swi + .global rt_hw_trap_pabt + .global rt_hw_trap_dabt + .global rt_hw_trap_resv + .global rt_hw_trap_irq + .global rt_hw_trap_fiq + + .global rt_interrupt_enter + .global rt_interrupt_leave + .global rt_thread_switch_interrupt_flag + .global rt_interrupt_from_thread + .global rt_interrupt_to_thread + + .align 5 +Undef_Handler: + SUB SP, SP, #S_FRAME_SIZE + STMIA SP, {R0 - R12} @; Calling R0-R12 + ADD R8, SP, #S_PC + STMDB R8, {SP, LR} @; Calling SP, LR + STR LR, [R8, #0] @; Save calling PC + MRS R6, SPSR + STR R6, [R8, #4] @; Save CPSR + STR R0, [R8, #8] @; Save SPSR + MOV R0, SP + BL rt_hw_trap_udef + + .align 5 +SWI_Handler: + BL rt_hw_trap_swi + + .align 5 +PAbt_Handler: + BL rt_hw_trap_pabt + + .align 5 +DAbt_Handler: + SUB SP, SP, #S_FRAME_SIZE + STMIA SP, {R0 - R12} @; Calling R0-R12 + ADD R8, SP, #S_PC + STMDB R8, {SP, LR} @; Calling SP, LR + STR LR, [R8, #0] @; Save calling PC + MRS R6, SPSR + STR R6, [R8, #4] @; Save CPSR + STR R0, [R8, #8] @; Save SPSR + MOV R0, SP + BL rt_hw_trap_dabt + + .align 5 +Resv_Handler: + BL rt_hw_trap_resv + + .align 5 +FIQ_Handler: + STMFD SP!, {R0-R7,LR} + BL rt_hw_trap_fiq + LDMFD SP!, {R0-R7,LR} + SUBS PC, LR, #4 + + .align 5 +IRQ_Handler: + STMFD SP!, {R0-R12,LR} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + @; If rt_thread_switch_interrupt_flag set, + @; jump to rt_hw_context_switch_interrupt_do and don't return + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CMP R1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD SP!, {R0-R12,LR} + SUBS PC, LR, #4 + +@;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- +rt_hw_context_switch_interrupt_do: + MOV R1, #0 @; Clear flag + STR R1, [R0] @; Save to flag variable + + LDMFD SP!, {R0-R12,LR} @; Reload saved registers + STMFD SP, {R0-R2} @; Save R0-R2 + SUB R1, SP, #4*3 @; Save old task's SP to R1 + SUB R2, LR, #4 @; Save old task's PC to R2 + + MRS R0, SPSR @; Get CPSR of interrupt thread + + MSR CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt + + STMFD SP!, {R2} @; Push old task's PC + STMFD SP!, {R3-R12,LR} @; Push old task's LR,R12-R3 + LDMFD R1, {R1-R3} + STMFD SP!, {R1-R3} @; Push old task's R2-R0 + STMFD SP!, {R0} @; Push old task's CPSR + + LDR R4, =rt_interrupt_from_thread + LDR R5, [R4] @; R5 = stack ptr in old tasks's TCB + STR SP, [R5] @; Store SP in preempted tasks's TCB + + LDR R6, =rt_interrupt_to_thread + LDR R6, [R6] @; R6 = stack ptr in new tasks's TCB + LDR SP, [R6] @; Get new task's stack pointer + + LDMFD SP!, {R4} @; Pop new task's SPSR + MSR SPSR_cxsf, R4 + + LDMFD SP!, {R0-R12,LR,PC}^ @; pop new task's R0-R12,LR & PC SPSR 2 CPSR diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_iar.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_iar.S new file mode 100644 index 0000000000..080acd57b6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_iar.S @@ -0,0 +1,278 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2011-01-13 weety first version +; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP +; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table +; * 2015-06-04 aozima Align stack address to 8 byte. +; */ + +#include "rt_low_level_init.h" + +#define S_FRAME_SIZE (18*4) ;72 + +;#define S_SPSR (17*4) ;SPSR +;#define S_CPSR (16*4) ;CPSR +#define S_PC (15*4) ;R15 +;#define S_LR (14*4) ;R14 +;#define S_SP (13*4) ;R13 + +;#define S_IP (12*4) ;R12 +;#define S_FP (11*4) ;R11 +;#define S_R10 (10*4) +;#define S_R9 (9*4) +;#define S_R8 (8*4) +;#define S_R7 (7*4) +;#define S_R6 (6*4) +;#define S_R5 (5*4) +;#define S_R4 (4*4) +;#define S_R3 (3*4) +;#define S_R2 (2*4) +;#define S_R1 (1*4) +;#define S_R0 (0*4) + +#define MODE_SYS 0x1F +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_ABT 0x17 +#define MODE_UND 0x1B +#define MODEMASK 0x1F + +#define NOINT 0xC0 + +;----------------------- Stack and Heap Definitions ---------------------------- + MODULE ?cstartup + SECTION .noinit:DATA:NOROOT(3) + DATA + + ALIGNRAM 3 + DS8 UND_STK_SIZE + PUBLIC UND_STACK_START +UND_STACK_START: + + ALIGNRAM 3 + DS8 ABT_STK_SIZE + PUBLIC ABT_STACK_START +ABT_STACK_START: + + ALIGNRAM 3 + DS8 FIQ_STK_SIZE + PUBLIC FIQ_STACK_START +FIQ_STACK_START: + + ALIGNRAM 3 + DS8 IRQ_STK_SIZE + PUBLIC IRQ_STACK_START +IRQ_STACK_START: + + ALIGNRAM 3 + DS8 SYS_STK_SIZE + PUBLIC SYS_STACK_START +SYS_STACK_START: + + ALIGNRAM 3 + DS8 SVC_STK_SIZE + PUBLIC SVC_STACK_START +SVC_STACK_START: + +;--------------Jump vector table------------------------------------------------ + SECTION .intvec:CODE:ROOT(2) + ARM + PUBLIC Entry_Point +Entry_Point: +__iar_init$$done: ; The interrupt vector is not needed + ; until after copy initialization is done + LDR PC, vector_reset + LDR PC, vector_undef + LDR PC, vector_swi + LDR PC, vector_pabt + LDR PC, vector_dabt + LDR PC, vector_resv + LDR PC, vector_irq + LDR PC, vector_fiq + +vector_reset: + DC32 Reset_Handler +vector_undef: + DC32 Undef_Handler +vector_swi: + DC32 SWI_Handler +vector_pabt: + DC32 PAbt_Handler +vector_dabt: + DC32 DAbt_Handler +vector_resv: + DC32 Resv_Handler +vector_irq: + DC32 IRQ_Handler +vector_fiq: + DC32 FIQ_Handler + +;----------------- Reset Handler ----------------------------------------------- + EXTERN rt_low_level_init + EXTERN ?main + PUBLIC __iar_program_start +__iar_program_start: +Reset_Handler: + ; Set the cpu to SVC32 mode + MRS R0, CPSR + BIC R0, R0, #MODEMASK + ORR R0, R0, #MODE_SVC|NOINT + MSR CPSR_cxsf, R0 + + ; Set CO-Processor + ; little-end，disbale I/D Cache MMU, vector table is 0x00000000 + MRC P15, 0, R0, C1, C0, 0 ; Read CP15 + LDR R1, =0x00003085 ; set clear bits + BIC R0, R0, R1 + MCR P15, 0, R0, C1, C0, 0 ; Write CP15 + + ; Call low level init function, + ; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. + LDR SP, =SVC_STACK_START + LDR R0, =rt_low_level_init + BLX R0 + +Setup_Stack: + ; Setup Stack for each mode + MRS R0, CPSR + BIC R0, R0, #MODEMASK + + ORR R1, R0, #MODE_UND|NOINT + MSR CPSR_cxsf, R1 ; Undef mode + LDR SP, =UND_STACK_START + + ORR R1,R0,#MODE_ABT|NOINT + MSR CPSR_cxsf,R1 ; Abort mode + LDR SP, =ABT_STACK_START + + ORR R1,R0,#MODE_IRQ|NOINT + MSR CPSR_cxsf,R1 ; IRQ mode + LDR SP, =IRQ_STACK_START + + ORR R1,R0,#MODE_FIQ|NOINT + MSR CPSR_cxsf,R1 ; FIQ mode + LDR SP, =FIQ_STACK_START + + ORR R1,R0,#MODE_SYS|NOINT + MSR CPSR_cxsf,R1 ; SYS/User mode + LDR SP, =SYS_STACK_START + + ORR R1,R0,#MODE_SVC|NOINT + MSR CPSR_cxsf,R1 ; SVC mode + LDR SP, =SVC_STACK_START + + ; Enter the C code + LDR R0, =?main + BLX R0 + +;----------------- Exception Handler ------------------------------------------- + IMPORT rt_hw_trap_udef + IMPORT rt_hw_trap_swi + IMPORT rt_hw_trap_pabt + IMPORT rt_hw_trap_dabt + IMPORT rt_hw_trap_resv + IMPORT rt_hw_trap_irq + IMPORT rt_hw_trap_fiq + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + + SECTION .text:CODE:ROOT(2) + ARM +Undef_Handler: + SUB SP, SP, #S_FRAME_SIZE + STMIA SP, {R0 - R12} ; Calling R0-R12 + ADD R8, SP, #S_PC + STMDB R8, {SP, LR} ; Calling SP, LR + STR LR, [R8, #0] ; Save calling PC + MRS R6, SPSR + STR R6, [R8, #4] ; Save CPSR + STR R0, [R8, #8] ; Save SPSR + MOV R0, SP + BL rt_hw_trap_udef + +SWI_Handler: + BL rt_hw_trap_swi + +PAbt_Handler: + BL rt_hw_trap_pabt + +DAbt_Handler: + SUB SP, SP, #S_FRAME_SIZE + STMIA SP, {R0 - R12} ; Calling R0-R12 + ADD R8, SP, #S_PC + STMDB R8, {SP, LR} ; Calling SP, LR + STR LR, [R8, #0] ; Save calling PC + MRS R6, SPSR + STR R6, [R8, #4] ; Save CPSR + STR R0, [R8, #8] ; Save SPSR + MOV R0, SP + BL rt_hw_trap_dabt + +Resv_Handler: + BL rt_hw_trap_resv + +IRQ_Handler: + STMFD SP!, {R0-R12,LR} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; If rt_thread_switch_interrupt_flag set, + ; jump to rt_hw_context_switch_interrupt_do and don't return + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CMP R1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD SP!, {R0-R12,LR} + SUBS PC, LR, #4 + +FIQ_Handler: + STMFD SP!, {R0-R7,LR} + BL rt_hw_trap_fiq + LDMFD SP!, {R0-R7,LR} + SUBS PC, LR, #4 + +;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- +rt_hw_context_switch_interrupt_do: + MOV R1, #0 ; Clear flag + STR R1, [R0] ; Save to flag variable + + LDMFD SP!, {R0-R12,LR} ; Reload saved registers + STMFD SP, {R0-R2} ; Save R0-R2 + SUB R1, SP, #4*3 ; Save old task's SP to R1 + SUB R2, LR, #4 ; Save old task's PC to R2 + + MRS R0, SPSR ; Get CPSR of interrupt thread + + MSR CPSR_c, #MODE_SVC|NOINT ; Switch to SVC mode and no interrupt + + STMFD SP!, {R2} ; Push old task's PC + STMFD SP!, {R3-R12,LR} ; Push old task's LR,R12-R3 + LDMFD R1, {R1-R3} + STMFD SP!, {R1-R3} ; Push old task's R2-R0 + STMFD SP!, {R0} ; Push old task's CPSR + + LDR R4, =rt_interrupt_from_thread + LDR R5, [R4] ; R5 = stack ptr in old tasks's TCB + STR SP, [R5] ; Store SP in preempted tasks's TCB + + LDR R6, =rt_interrupt_to_thread + LDR R6, [R6] ; R6 = stack ptr in new tasks's TCB + LDR SP, [R6] ; Get new task's stack pointer + + LDMFD SP!, {R4} ; Pop new task's SPSR + MSR SPSR_cxsf, R4 + + LDMFD SP!, {R0-R12,LR,PC}^ ; pop new task's R0-R12,LR & PC SPSR to CPSR + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_rvds.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_rvds.S new file mode 100644 index 0000000000..fc7e84ffaa --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/start_rvds.S @@ -0,0 +1,301 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2011-08-14 weety first version +; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP +; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table +; * 2015-06-04 aozima Align stack address to 8 byte. +; */ + +UND_STK_SIZE EQU 512 +SVC_STK_SIZE EQU 4096 +ABT_STK_SIZE EQU 512 +IRQ_STK_SIZE EQU 1024 +FIQ_STK_SIZE EQU 1024 +SYS_STK_SIZE EQU 512 +Heap_Size EQU 512 + +S_FRAME_SIZE EQU (18*4) ;72 +S_PC EQU (15*4) ;R15 + +MODE_USR EQU 0X10 +MODE_FIQ EQU 0X11 +MODE_IRQ EQU 0X12 +MODE_SVC EQU 0X13 +MODE_ABT EQU 0X17 +MODE_UND EQU 0X1B +MODE_SYS EQU 0X1F +MODEMASK EQU 0X1F + +NOINT EQU 0xC0 + +;----------------------- Stack and Heap Definitions ---------------------------- + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem + + SPACE UND_STK_SIZE + EXPORT UND_STACK_START +UND_STACK_START + + ALIGN 8 + SPACE ABT_STK_SIZE + EXPORT ABT_STACK_START +ABT_STACK_START + + ALIGN 8 + SPACE FIQ_STK_SIZE + EXPORT FIQ_STACK_START +FIQ_STACK_START + + ALIGN 8 + SPACE IRQ_STK_SIZE + EXPORT IRQ_STACK_START +IRQ_STACK_START + + ALIGN 8 + SPACE SYS_STK_SIZE + EXPORT SYS_STACK_START +SYS_STACK_START + + ALIGN 8 + SPACE SVC_STK_SIZE + EXPORT SVC_STACK_START +SVC_STACK_START +Stack_Top +__initial_sp + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 +;--------------Jump vector table------------------------------------------------ + EXPORT Entry_Point + AREA RESET, CODE, READONLY + ARM +Entry_Point + LDR PC, vector_reset + LDR PC, vector_undef + LDR PC, vector_swi + LDR PC, vector_pabt + LDR PC, vector_dabt + LDR PC, vector_resv + LDR PC, vector_irq + LDR PC, vector_fiq + +vector_reset + DCD Reset_Handler +vector_undef + DCD Undef_Handler +vector_swi + DCD SWI_Handler +vector_pabt + DCD PAbt_Handler +vector_dabt + DCD DAbt_Handler +vector_resv + DCD Resv_Handler +vector_irq + DCD IRQ_Handler +vector_fiq + DCD FIQ_Handler + +;----------------- Reset Handler ----------------------------------------------- + IMPORT rt_low_level_init + IMPORT __main + EXPORT Reset_Handler +Reset_Handler + ; set the cpu to SVC32 mode + MRS R0,CPSR + BIC R0,R0,#MODEMASK + ORR R0,R0,#MODE_SVC:OR:NOINT + MSR CPSR_cxsf,R0 + + ; Set CO-Processor + ; little-end，disbale I/D Cache MMU, vector table is 0x00000000 + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 + LDR R1, =0x00003085 ; set clear bits + BIC R0, R0, R1 + MCR p15, 0, R0, c1, c0, 0 ; Write CP15 + + ; Call low level init function, + ; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. + LDR SP, =SVC_STACK_START + LDR R0, =rt_low_level_init + BLX R0 + +Setup_Stack + ; Setup Stack for each mode + MRS R0, CPSR + BIC R0, R0, #MODEMASK + + ORR R1, R0, #MODE_UND:OR:NOINT + MSR CPSR_cxsf, R1 ; Undef mode + LDR SP, =UND_STACK_START + + ORR R1,R0,#MODE_ABT:OR:NOINT + MSR CPSR_cxsf,R1 ; Abort mode + LDR SP, =ABT_STACK_START + + ORR R1,R0,#MODE_IRQ:OR:NOINT + MSR CPSR_cxsf,R1 ; IRQ mode + LDR SP, =IRQ_STACK_START + + ORR R1,R0,#MODE_FIQ:OR:NOINT + MSR CPSR_cxsf,R1 ; FIQ mode + LDR SP, =FIQ_STACK_START + + ORR R1,R0,#MODE_SYS:OR:NOINT + MSR CPSR_cxsf,R1 ; SYS/User mode + LDR SP, =SYS_STACK_START + + ORR R1,R0,#MODE_SVC:OR:NOINT + MSR CPSR_cxsf,R1 ; SVC mode + LDR SP, =SVC_STACK_START + + ; Enter the C code + LDR R0, =__main + BLX R0 + +;----------------- Exception Handler ------------------------------------------- + IMPORT rt_hw_trap_udef + IMPORT rt_hw_trap_swi + IMPORT rt_hw_trap_pabt + IMPORT rt_hw_trap_dabt + IMPORT rt_hw_trap_resv + IMPORT rt_hw_trap_irq + IMPORT rt_hw_trap_fiq + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +Undef_Handler PROC + SUB SP, SP, #S_FRAME_SIZE + STMIA SP, {R0 - R12} ; Calling R0-R12 + ADD R8, SP, #S_PC + STMDB R8, {SP, LR} ; Calling SP, LR + STR LR, [R8, #0] ; Save calling PC + MRS R6, SPSR + STR R6, [R8, #4] ; Save CPSR + STR R0, [R8, #8] ; Save SPSR + MOV R0, SP + BL rt_hw_trap_udef + ENDP + +SWI_Handler PROC + BL rt_hw_trap_swi + ENDP + +PAbt_Handler PROC + BL rt_hw_trap_pabt + ENDP + +DAbt_Handler PROC + SUB SP, SP, #S_FRAME_SIZE + STMIA SP, {R0 - R12} ; Calling R0-R12 + ADD R8, SP, #S_PC + STMDB R8, {SP, LR} ; Calling SP, LR + STR LR, [R8, #0] ; Save calling PC + MRS R6, SPSR + STR R6, [R8, #4] ; Save CPSR + STR R0, [R8, #8] ; Save SPSR + MOV R0, SP + BL rt_hw_trap_dabt + ENDP + +Resv_Handler PROC + BL rt_hw_trap_resv + ENDP + +FIQ_Handler PROC + STMFD SP!, {R0-R7,LR} + BL rt_hw_trap_fiq + LDMFD SP!, {R0-R7,LR} + SUBS PC, LR, #4 + ENDP + +IRQ_Handler PROC + STMFD SP!, {R0-R12,LR} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; If rt_thread_switch_interrupt_flag set, + ; jump to rt_hw_context_switch_interrupt_do and don't return + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CMP R1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD SP!, {R0-R12,LR} + SUBS PC, LR, #4 + ENDP + +;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- +rt_hw_context_switch_interrupt_do PROC + MOV R1, #0 ; Clear flag + STR R1, [R0] ; Save to flag variable + + LDMFD SP!, {R0-R12,LR} ; Reload saved registers + STMFD SP, {R0-R2} ; Save R0-R2 + SUB R1, SP, #4*3 ; Save old task's SP to R1 + SUB R2, LR, #4 ; Save old task's PC to R2 + + MRS R0, SPSR ; Get CPSR of interrupt thread + + MSR CPSR_c, #MODE_SVC:OR:NOINT ; Switch to SVC mode and no interrupt + + STMFD SP!, {R2} ; Push old task's PC + STMFD SP!, {R3-R12,LR} ; Push old task's LR,R12-R3 + LDMFD R1, {R1-R3} + STMFD SP!, {R1-R3} ; Push old task's R2-R0 + STMFD SP!, {R0} ; Push old task's CPSR + + LDR R4, =rt_interrupt_from_thread + LDR R5, [R4] ; R5 = stack ptr in old tasks's TCB + STR SP, [R5] ; Store SP in preempted tasks's TCB + + LDR R6, =rt_interrupt_to_thread + LDR R6, [R6] ; R6 = stack ptr in new tasks's TCB + LDR SP, [R6] ; Get new task's stack pointer + + LDMFD SP!, {R4} ; Pop new task's SPSR + MSR SPSR_cxsf, R4 + + LDMFD SP!, {R0-R12,LR,PC}^ ; pop new task's R0-R12,LR & PC SPSR to CPSR + ENDP + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem ; heap base + LDR R1, = SVC_STACK_START ; stack base (top-address) + LDR R2, = (Heap_Mem + Heap_Size) ; heap limit + LDR R3, = (SVC_STACK_START - SVC_STK_SIZE) ; stack limit (low-address) + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/trap.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/trap.c new file mode 100644 index 0000000000..054cc2741a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/arm926/trap.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP + */ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +struct rt_hw_register +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; +}; + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ + +void rt_hw_show_register (struct rt_hw_register *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", + regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", + regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", + regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", + regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", + regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When ARM7TDMI comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_udef(struct rt_hw_register *regs) +{ + rt_hw_show_register(regs); + + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_register *regs) +{ + rt_hw_show_register(regs); + + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_register *regs) +{ + rt_hw_show_register(regs); + + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_register *regs) +{ + rt_hw_show_register(regs); + + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_register *regs) +{ + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); +} + +extern struct rt_irq_desc irq_desc[]; +extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq); +extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id); + +void rt_hw_trap_irq() +{ + rt_isr_handler_t isr_func; + rt_uint32_t irq; + void *param; + + /* get irq number */ + irq = rt_hw_interrupt_get_active(INT_IRQ); + + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + + rt_hw_interrupt_ack(INT_IRQ, irq); +#ifdef RT_USING_INTERRUPT_INFO + irq_desc[irq].counter ++; +#endif +} + +void rt_hw_trap_fiq() +{ + rt_isr_handler_t isr_func; + rt_uint32_t irq; + void *param; + + /* get irq number */ + irq = rt_hw_interrupt_get_active(INT_FIQ); + + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + + rt_hw_interrupt_ack(INT_FIQ, irq); +#ifdef RT_USING_INTERRUPT_INFO + irq_desc[irq].counter ++; +#endif +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/arm_entry_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/arm_entry_gcc.S new file mode 100644 index 0000000000..6d4ac111d0 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/arm_entry_gcc.S @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2014-11-07 weety first version + */ + +#include + +#include "armv6.h" + +//#define DEBUG + +.macro PRINT, str +#ifdef DEBUG + stmfd sp!, {r0-r3, ip, lr} + add r0, pc, #4 + bl rt_kprintf + b 1f + .asciz "UNDEF: \str\n" + .balign 4 +1: ldmfd sp!, {r0-r3, ip, lr} +#endif + .endm + +.macro PRINT1, str, arg +#ifdef DEBUG + stmfd sp!, {r0-r3, ip, lr} + mov r1, \arg + add r0, pc, #4 + bl rt_kprintf + b 1f + .asciz "UNDEF: \str\n" + .balign 4 +1: ldmfd sp!, {r0-r3, ip, lr} +#endif + .endm + +.macro PRINT3, str, arg1, arg2, arg3 +#ifdef DEBUG + stmfd sp!, {r0-r3, ip, lr} + mov r3, \arg3 + mov r2, \arg2 + mov r1, \arg1 + add r0, pc, #4 + bl rt_kprintf + b 1f + .asciz "UNDEF: \str\n" + .balign 4 +1: ldmfd sp!, {r0-r3, ip, lr} +#endif + .endm + +.macro get_current_thread, rd + ldr \rd, .current_thread + ldr \rd, [\rd] + .endm + +.current_thread: + .word rt_current_thread + +#ifdef RT_USING_NEON + .align 6 + +/* is the neon instuction on arm mode? */ +.neon_opcode: + .word 0xfe000000 @ mask + .word 0xf2000000 @ opcode + + .word 0xff100000 @ mask + .word 0xf4000000 @ opcode + + .word 0x00000000 @ end mask + .word 0x00000000 @ end opcode +#endif + +/* undefined instruction exception processing */ +.globl undef_entry +undef_entry: + PRINT1 "r0=0x%08x", r0 + PRINT1 "r2=0x%08x", r2 + PRINT1 "r9=0x%08x", r9 + PRINT1 "sp=0x%08x", sp + +#ifdef RT_USING_NEON + ldr r6, .neon_opcode +__check_neon_instruction: + ldr r7, [r6], #4 @ load mask value + cmp r7, #0 @ end mask? + beq __check_vfp_instruction + and r8, r0, r7 + ldr r7, [r6], #4 @ load opcode value + cmp r8, r7 @ is NEON instruction? + bne __check_neon_instruction + b vfp_entry +__check_vfp_instruction: +#endif + tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC instruction has bit 27 + tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 instruction + moveq pc, lr @ no vfp coprocessor instruction, return + get_current_thread r10 + and r8, r0, #0x00000f00 @ get coprocessor number + PRINT1 "CP=0x%08x", r8 + add pc, pc, r8, lsr #6 + nop + mov pc, lr @ CP0 + mov pc, lr @ CP1 + mov pc, lr @ CP2 + mov pc, lr @ CP3 + mov pc, lr @ CP4 + mov pc, lr @ CP5 + mov pc, lr @ CP6 + mov pc, lr @ CP7 + mov pc, lr @ CP8 + mov pc, lr @ CP9 + mov pc, lr @ CP10 VFP + mov pc, lr @ CP11 VFP + mov pc, lr @ CP12 + mov pc, lr @ CP13 + mov pc, lr @ CP14 DEBUG + mov pc, lr @ CP15 SYS CONTROL + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/armv6.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/armv6.h new file mode 100644 index 0000000000..659ce90721 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/armv6.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __ARMV6_H__ +#define __ARMV6_H__ + + +/*****************************/ +/* CPU Mode */ +/*****************************/ +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#ifndef __ASSEMBLY__ +struct rt_hw_register +{ + rt_uint32_t cpsr; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; +}; +#if(0) +struct rt_hw_register{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; +}; +#endif +#endif + +/* rt_hw_register offset */ +#define S_FRAME_SIZE 68 + +#define S_PC 64 +#define S_LR 60 +#define S_SP 56 +#define S_IP 52 +#define S_FP 48 +#define S_R10 44 +#define S_R9 40 +#define S_R8 36 +#define S_R7 32 +#define S_R6 28 +#define S_R5 24 +#define S_R4 20 +#define S_R3 16 +#define S_R2 12 +#define S_R1 8 +#define S_R0 4 +#define S_CPSR 0 + + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/context_gcc.S new file mode 100644 index 0000000000..0446109c92 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/context_gcc.S @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety copy from mini2440 + */ + +/*! + * \addtogroup ARMv6 + */ +/*@{*/ + +#include + +#define NOINT 0xc0 +#define FPEXC_EN (1 << 30) /* VFP enable bit */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid if + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr_c, r0 + bx lr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + orrne r4, r4, #0x20 @ it's thumb code + + stmfd sp!, {r4} @ push cpsr + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task cpsr to spsr + msr spsr_cxsf, r4 +_do_switch: + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + + bic r4, r4, #0x20 @ must be ARM mode + msr cpsr_cxsf, r4 + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r3, [r2] + ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + str r0, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/cpuport.c new file mode 100644 index 0000000000..c8e9201722 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/cpuport.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + */ + +#include +#include + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +extern void machine_reset(void); +extern void machine_shutdown(void); + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + + +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + + rt_kprintf("Restarting system...\n"); + machine_reset(); + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +#if defined(__CC_ARM) +int __rt_ffs(int value) +{ + register rt_uint32_t x; + + if (value == 0) + return value; + + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } + + return x; +} +#elif defined(__IAR_SYSTEMS_ICC__) +int __rt_ffs(int value) +{ + if (value == 0) + return value; + + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); +} +#elif defined(__GNUC__) +int __rt_ffs(int value) +{ + if (value == 0) + return value; + + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); + + return (32 - value); +} +#endif + +#endif + + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/mmu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/mmu.c new file mode 100644 index 0000000000..ae3cf73559 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/mmu.c @@ -0,0 +1,548 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "mmu.h" + +#ifdef __CC_ARM +void mmu_setttbase(rt_uint32_t i) +{ + register rt_uint32_t value; + + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } + + value = 0x55555555; + __asm volatile + { + mcr p15, 0, value, c3, c0, 0 + mcr p15, 0, i, c2, c0, 0 + } +} + +void mmu_set_domain(rt_uint32_t i) +{ + __asm volatile + { + mcr p15,0, i, c3, c0, 0 + } +} + +void mmu_enable() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_icache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_dcache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_icache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_dcache() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t value; + + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_clean_invalidated_cache_index(int index) +{ + __asm volatile + { + mcr p15, 0, index, c7, c14, 2 + } +} + +void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while(ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_tlb() +{ + register rt_uint32_t value; + + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } +} + +void mmu_invalidate_icache() +{ + register rt_uint32_t value; + + value = 0; + + __asm volatile + { + mcr p15, 0, value, c7, c5, 0 + } +} + + +void mmu_invalidate_dcache_all() +{ + register rt_uint32_t value; + + value = 0; + + __asm volatile + { + mcr p15, 0, value, c7, c6, 0 + } +} +#elif defined(__GNUC__) +void mmu_setttbase(register rt_uint32_t i) +{ + register rt_uint32_t value; + + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); +} + +void mmu_set_domain(register rt_uint32_t i) +{ + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); +} + +void mmu_enable() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= 0x1; + /* Enables the extended page tables to be configured for + the hardware page translation mechanism, Subpage AP bits disabled */ + i |= (1 << 23); /* support for ARMv6 MMU features */ + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~0x1; + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 12); + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 2); + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 12); + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 2); + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 1); + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 1); + + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_clean_invalidated_cache_index(int index) +{ + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); +} + +void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while(ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } +} + + +void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) +{ + unsigned int ptr; + + ptr = buffer & ~(CACHE_LINE_SIZE - 1); + + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } +} + +void mmu_invalidate_tlb() +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); +} + +void mmu_invalidate_icache() +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} + +void mmu_invalidate_dcache_all() +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); +} +#endif + +/* level1 page table */ +static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); +/* + * level2 page table + * RT_MMU_PTE_SIZE must be 1024*n + */ +#define RT_MMU_PTE_SIZE 4096 +static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); + +void mmu_create_pgd(struct mem_desc *mdesc) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); + nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); + pTT++; + } +} + +void mmu_create_pte(struct mem_desc *mdesc) +{ + volatile rt_uint32_t *pTT; + volatile rt_uint32_t *p_pteentry; + int i; + rt_uint32_t vaddr; + rt_uint32_t total_page = 0; + rt_uint32_t pte_offset = 0; + rt_uint32_t sect_attr = 0; + + total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; + pte_offset = mdesc->sect_attr & 0xfffffc00; + sect_attr = mdesc->sect_attr & 0x3ff; + vaddr = mdesc->vaddr_start; + + for(i = 0; i < total_page; i++) + { + pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); + if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ + { + *pTT = pte_offset | sect_attr; + p_pteentry = (rt_uint32_t *)pte_offset + + ((vaddr & 0x000ff000) >> 12); + pte_offset += 1024; + } + else /* using old Level 1 page table item */ + { + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + ((vaddr & 0x000ff000) >> 12); + } + + + *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); + vaddr += 0x1000; + } +} + +static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) +{ + rt_uint32_t pte_offset = 0; + rt_uint32_t nsec = 0; + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == PAGE_MAPPED) + { + nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; + mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; + pte_offset += nsec << 10; + } + if (pte_offset >= RT_MMU_PTE_SIZE) + { + rt_kprintf("PTE table size too little\n"); + RT_ASSERT(0); + } + + mdesc++; + } +} + + +void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); + + /* clear pgd and pte table */ + rt_memset((void *)_pgd_table, 0, 16*1024); + rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); + build_pte_mem_desc(mdesc, size); + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == SECT_MAPPED) + { + mmu_create_pgd(mdesc); + } + else + { + mmu_create_pte(mdesc); + } + + mdesc++; + } + + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_pgd_table); + + /* enables MMU */ + mmu_enable(); + + /* enable Instruction Cache */ + mmu_enable_icache(); + + /* enable Data Cache */ + mmu_enable_dcache(); + + mmu_invalidate_icache(); + mmu_invalidate_dcache_all(); +} + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/mmu.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/mmu.h new file mode 100644 index 0000000000..4df61ac21d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/mmu.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +#include + +#define CACHE_LINE_SIZE 32 + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PGD) + * - common + */ +#define PGD_TYPE_MASK (3 << 0) +#define PGD_TYPE_FAULT (0 << 0) +#define PGD_TYPE_TABLE (1 << 0) +#define PGD_TYPE_SECT (2 << 0) +#define PGD_BIT4 (1 << 4) +#define PGD_DOMAIN(x) ((x) << 5) +#define PGD_PROTECTION (1 << 9) /* ARMv5 */ +/* + * - section + */ +#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_CACHEABLE (1 << 3) +#define PGD_SECT_XN (1 << 4) /* ARMv6 */ +#define PGD_SECT_AP0 (1 << 10) +#define PGD_SECT_AP1 (1 << 11) +#define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ +#define PGD_SECT_APX (1 << 15) /* ARMv6 */ +#define PGD_SECT_S (1 << 16) /* ARMv6 */ +#define PGD_SECT_nG (1 << 17) /* ARMv6 */ +#define PGD_SECT_SUPER (1 << 18) /* ARMv6 */ + +#define PGD_SECT_UNCACHED (0) +#define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE) +#define PGD_SECT_WT (PGD_SECT_CACHEABLE) +#define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) +#define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE) +#define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) +#define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2)) + + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_FAULT (0 << 0) +#define PTE_TYPE_LARGE (1 << 0) +#define PTE_TYPE_SMALL (2 << 0) +#define PTE_TYPE_EXT (3 << 0) /* ARMv5 */ +#define PTE_BUFFERABLE (1 << 2) +#define PTE_CACHEABLE (1 << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_XN (1 << 0) /* ARMv6 */ +#define PTE_EXT_AP_MASK (3 << 4) +#define PTE_EXT_AP0 (1 << 4) +#define PTE_EXT_AP1 (2 << 4) +#define PTE_EXT_AP_UNO_SRO (0 << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ +#define PTE_EXT_APX (1 << 9) /* ARMv6 */ +#define PTE_EXT_SHARED (1 << 10) /* ARMv6 */ +#define PTE_EXT_NG (1 << 11) /* ARMv6 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_MASK (0xff << 4) +#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) +#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) +#define PTE_SMALL_AP_URO_SRW (0xaa << 4) +#define PTE_SMALL_AP_URW_SRW (0xff << 4) + + +/* + * sector table properities + */ +#define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back +#define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through +#define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on +#define SECT_NCNB (0 << 2) //cache_off,WR_BUF off + +#define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW +#define SECT_AP_RO (PGD_SECT_AP0|PGD_SECT_AP1|PGD_SECT_APX) //supervisor=RO, user=RO + +#define SECT_RWX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read/Write/executable, cache, write back */ +#define SECT_RWX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read/Write/executable, cache, write through */ +#define SECT_RWX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read/Write/executable without cache and write buffer */ +#define SECT_RWX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read/Write without cache and write buffer */ + +#define SECT_RWNX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write back */ +#define SECT_RWNX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write through */ +#define SECT_RWNX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */ +#define SECT_RWNX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */ + + +#define SECT_ROX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read Only/executable, cache, write back */ +#define SECT_ROX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read Only/executable, cache, write through */ +#define SECT_ROX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read Only/executable without cache and write buffer */ +#define SECT_ROX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read Only without cache and write buffer */ + +#define SECT_RONX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write back */ +#define SECT_RONX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write through */ +#define SECT_RONX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */ +#define SECT_RONX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */ + +#define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE) /* Level 2 descriptor (PTE) entry properity */ + +/* + * page table properities + */ +#define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back +#define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through +#define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on +#define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off + +#define PAGE_AP_RW (PTE_EXT_AP0|PTE_EXT_AP1) //supervisor=RW, user=RW +#define PAGE_AP_RO (PTE_EXT_AP0|PTE_EXT_AP1|PTE_EXT_APX) //supervisor=RO, user=RO + +#define PAGE_RWX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write back */ +#define PAGE_RWX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write through */ +#define PAGE_RWX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write/executable without cache and write buffer */ +#define PAGE_RWX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ + +#define PAGE_RWNX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write back */ +#define PAGE_RWNX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write through */ +#define PAGE_RWNX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */ +#define PAGE_RWNX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */ + + +#define PAGE_ROX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write back */ +#define PAGE_ROX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write through */ +#define PAGE_ROX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only/executable without cache and write buffer */ +#define PAGE_ROX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ + +#define PAGE_RONX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write back */ +#define PAGE_RONX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write through */ +#define PAGE_RONX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ +#define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ + + +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ + +struct mem_desc { + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; +#define SECT_MAPPED 0 +#define PAGE_MAPPED 1 +}; + +void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/stack.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/stack.c new file mode 100644 index 0000000000..52de999fc2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/stack.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety copy from mini2440 + */ +#include + +/*****************************/ +/* CPU Mode */ +/*****************************/ +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/vfp.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/vfp.c new file mode 100644 index 0000000000..9aa8d34fcc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/vfp.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2014-11-07 weety first version + */ + +#include +#include +#include "vfp.h" + +#ifdef RT_USING_VFP + +void vfp_init(void) +{ + int ret = 0; + unsigned int value; + asm volatile ("mrc p15, 0, %0, c1, c0, 2" + :"=r"(value) + :); + value |= 0xf00000;/*enable CP10, CP11 user access*/ + asm volatile("mcr p15, 0, %0, c1, c0, 2" + : + :"r"(value)); + + asm volatile("fmrx %0, fpexc" + :"=r"(value)); + value |=(1<<30); + asm volatile("fmxr fpexc, %0" + : + :"r"(value)); + +} + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/vfp.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/vfp.h new file mode 100644 index 0000000000..c347dbe0a6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/armv6/vfp.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2014-11-07 weety first version + */ + +#ifndef __VFP_H__ +#define __VFP_H__ + +/* FPSID register bits */ +#define FPSID_IMPLEMENTER_BIT (24) +#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) +#define FPSID_SW (1 << 23) +#define FPSID_FORMAT_BIT (21) +#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) +#define FPSID_NODOUBLE (1 << 20) +#define FPSID_ARCH_BIT (16) +#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define FPSID_PART_BIT (8) +#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define FPSID_VARIANT_BIT (4) +#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define FPSID_REVISION_BIT (0) +#define FPSID_REVISION_MASK (0xF << FPSID_REVISION_BIT) + +/* FPSCR register bits */ +#define FPSCR_DN (1<<25) /* Default NaN mode enable bit */ +#define FPSCR_FZ (1<<24) /* Flush-to-zero mode enable bit */ +#define FPSCR_RN (0<<22) /* Round to nearest (RN) mode */ +#define FPSCR_RP (1<<22) /* Round towards plus infinity (RP) mode */ +#define FPSCR_RM (2<<22) /* Round towards minus infinity (RM) mode */ +#define FPSCR_RZ (3<<22) /* Round towards zero (RZ) mode */ +#define FPSCR_RMODE_BIT (22) +#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define FPSCR_STRIDE_BIT (20) +#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define FPSCR_LENGTH_BIT (16) +#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define FPSCR_IDE (1<<15) /* Input Subnormal exception trap enable bit */ +#define FPSCR_IXE (1<<12) /* Inexact exception trap enable bit */ +#define FPSCR_UFE (1<<11) /* Underflow exception trap enable bit */ +#define FPSCR_OFE (1<<10) /* Overflow exception trap enable bit */ +#define FPSCR_DZE (1<<9) /* Division by Zero exception trap enable bit */ +#define FPSCR_IOE (1<<8) /* Invalid Operation exception trap enable bit */ +#define FPSCR_IDC (1<<7) /* Input Subnormal cumulative exception flag */ +#define FPSCR_IXC (1<<4) /* Inexact cumulative exception flag */ +#define FPSCR_UFC (1<<3) /* Underflow cumulative exception flag */ +#define FPSCR_OFC (1<<2) /* Overflow cumulative exception flag */ +#define FPSCR_DZC (1<<1) /* Division by Zero cumulative exception flag */ +#define FPSCR_IOC (1<<0) /* Invalid Operation cumulative exception flag */ + +/* FPEXC register bits */ +#define FPEXC_EX (1 << 31) /* When EX is set, the VFP coprocessor is in the exceptional state */ +#define FPEXC_EN (1 << 30) /* VFP enable bit */ +#define FPEXC_DEX (1 << 29) /* Defined synchronous instruction exceptional flag */ +#define FPEXC_FP2V (1 << 28) /* FPINST2 instruction valid flag */ +#define FPEXC_LENGTH_BIT (8) +#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) +#define FPEXC_INV (1 << 7) /* Input exception flag */ +#define FPEXC_UFC (1 << 3) /* Potential underflow flag */ +#define FPEXC_OFC (1 << 2) /* Potential overflow flag */ +#define FPEXC_IOC (1 << 0) /* Potential invalid operation flag */ +#define FPEXC_TRAP_MASK (FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC) + + +/* MVFR0 register bits */ +#define MVFR0_A_SIMD_BIT (0) +#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) + + +/* thread switch micro */ +#define THREAD_INIT 0 +#define THREAD_EXIT 1 + +/* + * get VFP register + */ + +#define vmrs(vfp) ({ \ + rt_uint32_t var; \ + asm("vmrs %0, "#vfp"" : "=r" (var) : : "cc"); \ + var; \ + }) + +#define vmsr(vfp, var) \ + asm("vmsr "#vfp", %0" \ + : : "r" (var) : "cc") + + +#endif + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/backtrace.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/backtrace.c new file mode 100644 index 0000000000..4fc87b20d1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/backtrace.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include + +#ifdef __GNUC__ +/* +-->High Address,Stack Top +PC<------| +LR | +IP | +FP | +...... | +PC <-| | +LR | | +IP | | +FP---|-- | +...... | +PC | +LR | +IP | +FP--- +-->Low Address,Stack Bottom +*/ +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + rt_uint32_t i, pc, func_entry; + + pc = *fp; + rt_kprintf("[0x%x]\n", pc-0xC); + + for(i=0; i<10; i++) + { + fp = (rt_uint32_t *)*(fp - 3); + pc = *fp ; + + func_entry = pc - 0xC; + + if(func_entry <= 0x30000000) break; + + if(func_entry == thread_entry) + { + rt_kprintf("EntryPoint:0x%x\n", func_entry); + + break; + } + + rt_kprintf("[0x%x]\n", func_entry); + } +} +#else +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + /* old compiler implementation */ +} +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/div0.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/div0.c new file mode 100644 index 0000000000..0cb3e09b54 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/div0.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +void __div0 (void) +{ + while (1) ; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/divsi3.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/divsi3.S new file mode 100644 index 0000000000..3941bfc476 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/divsi3.S @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +/* $NetBSD: divsi3.S,v 1.5 2005/02/26 22:58:56 perry Exp $ */ + +/* + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * stack is aligned as there's a possibility of branching to L_overflow + * which makes a C call + */ + .text + .align 0 + .globl __umodsi3 + .type __umodsi3 , function +__umodsi3: + stmfd sp!, {lr} + sub sp, sp, #4 /* align stack */ + bl .L_udivide + add sp, sp, #4 /* unalign stack */ + mov r0, r1 + ldmfd sp!, {pc} + + .text + .align 0 + .globl __modsi3 + .type __modsi3 , function +__modsi3: + stmfd sp!, {lr} + sub sp, sp, #4 /* align stack */ + bl .L_divide + add sp, sp, #4 /* unalign stack */ + mov r0, r1 + ldmfd sp!, {pc} + +.L_overflow: + /* XXX should cause a fatal error */ + mvn r0, #0 + mov pc, lr + + .text + .align 0 + .globl __udivsi3 + .type __udivsi3 , function +__udivsi3: +.L_udivide: /* r0 = r0 / r1; r1 = r0 % r1 */ + eor r0, r1, r0 + eor r1, r0, r1 + eor r0, r1, r0 + /* r0 = r1 / r0; r1 = r1 % r0 */ + cmp r0, #1 + bcc .L_overflow + beq .L_divide_l0 + mov ip, #0 + movs r1, r1 + bpl .L_divide_l1 + orr ip, ip, #0x20000000 /* ip bit 0x20000000 = -ve r1 */ + movs r1, r1, lsr #1 + orrcs ip, ip, #0x10000000 /* ip bit 0x10000000 = bit 0 of r1 */ + b .L_divide_l1 + +.L_divide_l0: /* r0 == 1 */ + mov r0, r1 + mov r1, #0 + mov pc, lr + + .text + .align 0 + .globl __divsi3 + .type __divsi3 , function +__divsi3: +.L_divide: /* r0 = r0 / r1; r1 = r0 % r1 */ + eor r0, r1, r0 + eor r1, r0, r1 + eor r0, r1, r0 + /* r0 = r1 / r0; r1 = r1 % r0 */ + cmp r0, #1 + bcc .L_overflow + beq .L_divide_l0 + ands ip, r0, #0x80000000 + rsbmi r0, r0, #0 + ands r2, r1, #0x80000000 + eor ip, ip, r2 + rsbmi r1, r1, #0 + orr ip, r2, ip, lsr #1 /* ip bit 0x40000000 = -ve division */ + /* ip bit 0x80000000 = -ve remainder */ + +.L_divide_l1: + mov r2, #1 + mov r3, #0 + + /* + * If the highest bit of the dividend is set, we have to be + * careful when shifting the divisor. Test this. + */ + movs r1,r1 + bpl .L_old_code + + /* + * At this point, the highest bit of r1 is known to be set. + * We abuse this below in the tst instructions. + */ + tst r1, r0 /*, lsl #0 */ + bmi .L_divide_b1 + tst r1, r0, lsl #1 + bmi .L_divide_b2 + tst r1, r0, lsl #2 + bmi .L_divide_b3 + tst r1, r0, lsl #3 + bmi .L_divide_b4 + tst r1, r0, lsl #4 + bmi .L_divide_b5 + tst r1, r0, lsl #5 + bmi .L_divide_b6 + tst r1, r0, lsl #6 + bmi .L_divide_b7 + tst r1, r0, lsl #7 + bmi .L_divide_b8 + tst r1, r0, lsl #8 + bmi .L_divide_b9 + tst r1, r0, lsl #9 + bmi .L_divide_b10 + tst r1, r0, lsl #10 + bmi .L_divide_b11 + tst r1, r0, lsl #11 + bmi .L_divide_b12 + tst r1, r0, lsl #12 + bmi .L_divide_b13 + tst r1, r0, lsl #13 + bmi .L_divide_b14 + tst r1, r0, lsl #14 + bmi .L_divide_b15 + tst r1, r0, lsl #15 + bmi .L_divide_b16 + tst r1, r0, lsl #16 + bmi .L_divide_b17 + tst r1, r0, lsl #17 + bmi .L_divide_b18 + tst r1, r0, lsl #18 + bmi .L_divide_b19 + tst r1, r0, lsl #19 + bmi .L_divide_b20 + tst r1, r0, lsl #20 + bmi .L_divide_b21 + tst r1, r0, lsl #21 + bmi .L_divide_b22 + tst r1, r0, lsl #22 + bmi .L_divide_b23 + tst r1, r0, lsl #23 + bmi .L_divide_b24 + tst r1, r0, lsl #24 + bmi .L_divide_b25 + tst r1, r0, lsl #25 + bmi .L_divide_b26 + tst r1, r0, lsl #26 + bmi .L_divide_b27 + tst r1, r0, lsl #27 + bmi .L_divide_b28 + tst r1, r0, lsl #28 + bmi .L_divide_b29 + tst r1, r0, lsl #29 + bmi .L_divide_b30 + tst r1, r0, lsl #30 + bmi .L_divide_b31 +/* + * instead of: + * tst r1, r0, lsl #31 + * bmi .L_divide_b32 + */ + b .L_divide_b32 + +.L_old_code: + cmp r1, r0 + bcc .L_divide_b0 + cmp r1, r0, lsl #1 + bcc .L_divide_b1 + cmp r1, r0, lsl #2 + bcc .L_divide_b2 + cmp r1, r0, lsl #3 + bcc .L_divide_b3 + cmp r1, r0, lsl #4 + bcc .L_divide_b4 + cmp r1, r0, lsl #5 + bcc .L_divide_b5 + cmp r1, r0, lsl #6 + bcc .L_divide_b6 + cmp r1, r0, lsl #7 + bcc .L_divide_b7 + cmp r1, r0, lsl #8 + bcc .L_divide_b8 + cmp r1, r0, lsl #9 + bcc .L_divide_b9 + cmp r1, r0, lsl #10 + bcc .L_divide_b10 + cmp r1, r0, lsl #11 + bcc .L_divide_b11 + cmp r1, r0, lsl #12 + bcc .L_divide_b12 + cmp r1, r0, lsl #13 + bcc .L_divide_b13 + cmp r1, r0, lsl #14 + bcc .L_divide_b14 + cmp r1, r0, lsl #15 + bcc .L_divide_b15 + cmp r1, r0, lsl #16 + bcc .L_divide_b16 + cmp r1, r0, lsl #17 + bcc .L_divide_b17 + cmp r1, r0, lsl #18 + bcc .L_divide_b18 + cmp r1, r0, lsl #19 + bcc .L_divide_b19 + cmp r1, r0, lsl #20 + bcc .L_divide_b20 + cmp r1, r0, lsl #21 + bcc .L_divide_b21 + cmp r1, r0, lsl #22 + bcc .L_divide_b22 + cmp r1, r0, lsl #23 + bcc .L_divide_b23 + cmp r1, r0, lsl #24 + bcc .L_divide_b24 + cmp r1, r0, lsl #25 + bcc .L_divide_b25 + cmp r1, r0, lsl #26 + bcc .L_divide_b26 + cmp r1, r0, lsl #27 + bcc .L_divide_b27 + cmp r1, r0, lsl #28 + bcc .L_divide_b28 + cmp r1, r0, lsl #29 + bcc .L_divide_b29 + cmp r1, r0, lsl #30 + bcc .L_divide_b30 +.L_divide_b32: + cmp r1, r0, lsl #31 + subhs r1, r1,r0, lsl #31 + addhs r3, r3,r2, lsl #31 +.L_divide_b31: + cmp r1, r0, lsl #30 + subhs r1, r1,r0, lsl #30 + addhs r3, r3,r2, lsl #30 +.L_divide_b30: + cmp r1, r0, lsl #29 + subhs r1, r1,r0, lsl #29 + addhs r3, r3,r2, lsl #29 +.L_divide_b29: + cmp r1, r0, lsl #28 + subhs r1, r1,r0, lsl #28 + addhs r3, r3,r2, lsl #28 +.L_divide_b28: + cmp r1, r0, lsl #27 + subhs r1, r1,r0, lsl #27 + addhs r3, r3,r2, lsl #27 +.L_divide_b27: + cmp r1, r0, lsl #26 + subhs r1, r1,r0, lsl #26 + addhs r3, r3,r2, lsl #26 +.L_divide_b26: + cmp r1, r0, lsl #25 + subhs r1, r1,r0, lsl #25 + addhs r3, r3,r2, lsl #25 +.L_divide_b25: + cmp r1, r0, lsl #24 + subhs r1, r1,r0, lsl #24 + addhs r3, r3,r2, lsl #24 +.L_divide_b24: + cmp r1, r0, lsl #23 + subhs r1, r1,r0, lsl #23 + addhs r3, r3,r2, lsl #23 +.L_divide_b23: + cmp r1, r0, lsl #22 + subhs r1, r1,r0, lsl #22 + addhs r3, r3,r2, lsl #22 +.L_divide_b22: + cmp r1, r0, lsl #21 + subhs r1, r1,r0, lsl #21 + addhs r3, r3,r2, lsl #21 +.L_divide_b21: + cmp r1, r0, lsl #20 + subhs r1, r1,r0, lsl #20 + addhs r3, r3,r2, lsl #20 +.L_divide_b20: + cmp r1, r0, lsl #19 + subhs r1, r1,r0, lsl #19 + addhs r3, r3,r2, lsl #19 +.L_divide_b19: + cmp r1, r0, lsl #18 + subhs r1, r1,r0, lsl #18 + addhs r3, r3,r2, lsl #18 +.L_divide_b18: + cmp r1, r0, lsl #17 + subhs r1, r1,r0, lsl #17 + addhs r3, r3,r2, lsl #17 +.L_divide_b17: + cmp r1, r0, lsl #16 + subhs r1, r1,r0, lsl #16 + addhs r3, r3,r2, lsl #16 +.L_divide_b16: + cmp r1, r0, lsl #15 + subhs r1, r1,r0, lsl #15 + addhs r3, r3,r2, lsl #15 +.L_divide_b15: + cmp r1, r0, lsl #14 + subhs r1, r1,r0, lsl #14 + addhs r3, r3,r2, lsl #14 +.L_divide_b14: + cmp r1, r0, lsl #13 + subhs r1, r1,r0, lsl #13 + addhs r3, r3,r2, lsl #13 +.L_divide_b13: + cmp r1, r0, lsl #12 + subhs r1, r1,r0, lsl #12 + addhs r3, r3,r2, lsl #12 +.L_divide_b12: + cmp r1, r0, lsl #11 + subhs r1, r1,r0, lsl #11 + addhs r3, r3,r2, lsl #11 +.L_divide_b11: + cmp r1, r0, lsl #10 + subhs r1, r1,r0, lsl #10 + addhs r3, r3,r2, lsl #10 +.L_divide_b10: + cmp r1, r0, lsl #9 + subhs r1, r1,r0, lsl #9 + addhs r3, r3,r2, lsl #9 +.L_divide_b9: + cmp r1, r0, lsl #8 + subhs r1, r1,r0, lsl #8 + addhs r3, r3,r2, lsl #8 +.L_divide_b8: + cmp r1, r0, lsl #7 + subhs r1, r1,r0, lsl #7 + addhs r3, r3,r2, lsl #7 +.L_divide_b7: + cmp r1, r0, lsl #6 + subhs r1, r1,r0, lsl #6 + addhs r3, r3,r2, lsl #6 +.L_divide_b6: + cmp r1, r0, lsl #5 + subhs r1, r1,r0, lsl #5 + addhs r3, r3,r2, lsl #5 +.L_divide_b5: + cmp r1, r0, lsl #4 + subhs r1, r1,r0, lsl #4 + addhs r3, r3,r2, lsl #4 +.L_divide_b4: + cmp r1, r0, lsl #3 + subhs r1, r1,r0, lsl #3 + addhs r3, r3,r2, lsl #3 +.L_divide_b3: + cmp r1, r0, lsl #2 + subhs r1, r1,r0, lsl #2 + addhs r3, r3,r2, lsl #2 +.L_divide_b2: + cmp r1, r0, lsl #1 + subhs r1, r1,r0, lsl #1 + addhs r3, r3,r2, lsl #1 +.L_divide_b1: + cmp r1, r0 + subhs r1, r1, r0 + addhs r3, r3, r2 +.L_divide_b0: + + tst ip, #0x20000000 + bne .L_udivide_l1 + mov r0, r3 + cmp ip, #0 + rsbmi r1, r1, #0 + movs ip, ip, lsl #1 + bicmi r0, r0, #0x80000000 /* Fix incase we divided 0x80000000 */ + rsbmi r0, r0, #0 + mov pc, lr + +.L_udivide_l1: + tst ip, #0x10000000 + mov r1, r1, lsl #1 + orrne r1, r1, #1 + mov r3, r3, lsl #1 + cmp r1, r0 + subhs r1, r1, r0 + addhs r3, r3, r2 + mov r0, r3 + mov pc, lr diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/showmem.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/showmem.c new file mode 100644 index 0000000000..b770e4ce17 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/common/showmem.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include + +void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) +{ + int i = 0, j =0; + + RT_ASSERT(addr); + + addr = addr & ~0xF; + size = 4*((size + 3)/4); + + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); + + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + + addr += 4; + i++; + } + + rt_kprintf("\n"); + } + + return; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/SConscript b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/armv7.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/armv7.h new file mode 100644 index 0000000000..d22f72fa68 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/armv7.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cache.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cache.c new file mode 100644 index 0000000000..6d28d9e9f9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cache.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 quanzhao the first version + */ +#include +#include + +rt_inline rt_uint32_t rt_cpu_icache_line_size(void) +{ + rt_uint32_t ctr; + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); + return 4 << (ctr & 0xF); +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size(void) +{ + rt_uint32_t ctr; + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); + return 4 << ((ctr >> 16) & 0xF); +} + +void rt_hw_cpu_icache_invalidate(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_icache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */ + start_addr += line_size; + } +} + +void rt_hw_cpu_dcache_invalidate(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ + start_addr += line_size; + } +} + +void rt_hw_cpu_dcache_clean(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ + start_addr += line_size; + } +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_icache_invalidate(addr, size); +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + rt_hw_cpu_dcache_clean(addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_dcache_invalidate(addr, size); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/context_gcc.S new file mode 100644 index 0000000000..dff7a1de68 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/context_gcc.S @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +#include "rtconfig.h" +.section .text, "ax" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid i + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr, r0 + bx lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread); + * r0 --> to (thread stack) + * r1 --> to_thread + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + +#ifdef RT_USING_SMP + mov r0, r1 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit + +.section .bss.share.isr +_guest_switch_lvl: + .word 0 + +.globl vmm_virq_update + +.section .text.isr, "ax" +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread); + * r0 --> from (from_thread stack) + * r1 --> to (to_thread stack) + * r2 --> to_thread + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + orrne r4, r4, #0x20 @ it's thumb code + + stmfd sp!, {r4} @ push cpsr + +#ifdef RT_USING_LWP + stmfd sp, {r13, r14}^ @ push usr_sp usr_lr + sub sp, #8 +#endif + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + +#ifdef RT_USING_SMP + mov r0, r2 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: +#ifdef RT_USING_SMP + /* r0 :svc_mod context + * r1 :addr of from_thread's sp + * r2 :addr of to_thread's sp + * r3 :to_thread's tcb + */ + + str r0, [r1] + + ldr sp, [r2] + mov r0, r3 + bl rt_cpus_lock_status_restore + + b rt_hw_context_switch_exit + +#else /*RT_USING_SMP*/ + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r0, [ip] + str r3, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr +#endif /*RT_USING_SMP*/ + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: + +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mov r0, sp + cps #Mode_IRQ + bl rt_signal_check + cps #Mode_SVC + mov sp, r0 +#endif +#endif + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */ + add sp, #8 +#endif + ldmfd sp!, {r1} + msr spsr_cxsf, r1 /* original mode */ + ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cp15.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cp15.h new file mode 100644 index 0000000000..97c5b93ad2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cp15.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-25 quanzhao the first version + */ +#ifndef __CP15_H__ +#define __CP15_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cp15_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cp15_gcc.S new file mode 100644 index 0000000000..dd2436ffee --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cp15_gcc.S @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + /* clear SCTRL.V to customize the vector address */ + mrc p15, #0, r1, c1, c0, #0 + bic r1, #(1 << 13) + mcr p15, #0, r1, c1, c0, #0 + /* set up the vector address */ + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7fff + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl rt_cpu_icache_flush +rt_cpu_icache_flush: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_cpu_mmu_disable +rt_cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl rt_cpu_mmu_enable +rt_cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl rt_cpu_tlb_set +rt_cpu_tlb_set: + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cpu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cpu.c new file mode 100644 index 0000000000..6b129f89ee --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/cpu.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + * 2018-11-22 Jesven add rt_hw_cpu_id() + */ + +#include +#include +#include + +#ifdef RT_USING_SMP +int rt_hw_cpu_id(void) +{ + int cpu_id; + __asm__ volatile ( + "mrc p15, 0, %0, c0, c0, 5" + :"=r"(cpu_id) + ); + cpu_id &= 0xf; + return cpu_id; +}; + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) { + __asm__ __volatile__("wfe":::"memory"); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __asm__ volatile ("dmb":::"memory"); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __asm__ volatile ("dmb":::"memory"); + lock->tickets.owner++; + __asm__ volatile ("dsb ishst\nsev":::"memory"); +} +#endif /*RT_USING_SMP*/ + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/gic.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/gic.c new file mode 100644 index 0000000000..2a46142b54 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/gic.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ + +#include +#include + +#include "gic.h" +#include "cp15.h" + +struct arm_gic +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ + + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) + +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_pending(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n"); +} +#ifdef RT_USING_FINSH +#include +FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); +#endif + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + cpumask |= cpumask << 24; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + +#if 0 + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; +#endif + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0; + + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x01; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + GIC_CPU_BINPOINT(cpu_base) = 0x7; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_set_group(rt_uint32_t index, int vector, int group) +{ + /* As for GICv2, there are only group0 and group1. */ + RT_ASSERT(group <= 1); + RT_ASSERT(vector < _gic_max_irq); + + if (group == 0) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) &= ~(1 << (vector % 32)); + } + else if (group == 1) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) |= (1 << (vector % 32)); + } +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) + { + /* note: ipi_vector maybe different with irq_vector */ + GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector; +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/gic.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/gic.h new file mode 100644 index 0000000000..a16d0467fb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/gic.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +#include +#include + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +void arm_gic_set_group(rt_uint32_t index, int vector, int group); + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_clear_active(rt_uint32_t index, int irq); +void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/interrupt.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/interrupt.c new file mode 100644 index 0000000000..b7a70719a9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/interrupt.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + * 2018-11-22 Jesven add smp support + */ + +#include +#include +#include "interrupt.h" +#include "gic.h" + + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +#ifndef RT_USING_SMP +/* Those varibles will be accessed in ISR, so we need to share them. */ +rt_uint32_t rt_interrupt_from_thread = 0; +rt_uint32_t rt_interrupt_to_thread = 0; +rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif + +const unsigned int VECTOR_BASE = 0x00; +extern void rt_cpu_vector_set_base(unsigned int addr); +extern int system_vectors; + +void rt_hw_vector_init(void) +{ + rt_cpu_vector_set_base((unsigned int)&system_vectors); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t gic_cpu_base; + rt_uint32_t gic_dist_base; + rt_uint32_t gic_irq_start; + + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = platform_get_gic_dist_base(); + gic_cpu_base = platform_get_gic_cpu_base(); + + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + arm_gic_cpu_init(0, gic_cpu_base); +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/interrupt.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/interrupt.h new file mode 100644 index 0000000000..442187edee --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/interrupt.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_vector_init(void); + +void rt_hw_interrupt_control(int vector, int priority, int route); + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/mmu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/mmu.c new file mode 100644 index 0000000000..1260f41fe5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/mmu.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + */ + +#include +#include +#include + +#include "cp15.h" +#include "mmu.h" + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* set page table */ + for(; size > 0; size--) + { + rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } +} + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/mmu.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/mmu.h new file mode 100644 index 0000000000..fbce6df935 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/mmu.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-25 quanzhao the first version + */ +#ifndef __MMU_H_ +#define __MMU_H_ + +#include + +#define DESC_SEC (0x2) +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* eXecute Never */ +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO (2<<10) /* supervisor=RW, user=RO */ +#define SHARED (1<<16) /* shareable */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* device mapping type */ +#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) + +struct mem_desc +{ + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; +}; + + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/pmu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/pmu.c new file mode 100644 index 0000000000..8ffc1dede6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/pmu.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include +#include "pmu.h" + +void rt_hw_pmu_dump_feature(void) +{ + unsigned long reg; + + reg = rt_hw_pmu_get_control(); + rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", + reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); + RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/pmu.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/pmu.h new file mode 100644 index 0000000000..fb8390133d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/pmu.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#ifndef __PMU_H__ +#define __PMU_H__ + +#include "board.h" + +/* Number of counters */ +#define ARM_PMU_CNTER_NR 4 + +enum rt_hw_pmu_event_type { + ARM_PMU_EVENT_PMNC_SW_INCR = 0x00, + ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01, + ARM_PMU_EVENT_ITLB_REFILL = 0x02, + ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03, + ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04, + ARM_PMU_EVENT_DTLB_REFILL = 0x05, + ARM_PMU_EVENT_MEM_READ = 0x06, + ARM_PMU_EVENT_MEM_WRITE = 0x07, + ARM_PMU_EVENT_INSTR_EXECUTED = 0x08, + ARM_PMU_EVENT_EXC_TAKEN = 0x09, + ARM_PMU_EVENT_EXC_EXECUTED = 0x0A, + ARM_PMU_EVENT_CID_WRITE = 0x0B, +}; + +/* Enable bit */ +#define ARM_PMU_PMCR_E (0x01 << 0) +/* Event counter reset */ +#define ARM_PMU_PMCR_P (0x01 << 1) +/* Cycle counter reset */ +#define ARM_PMU_PMCR_C (0x01 << 2) +/* Cycle counter divider */ +#define ARM_PMU_PMCR_D (0x01 << 3) + +#ifdef __GNUC__ +rt_inline void rt_hw_pmu_enable_cnt(int divide64) +{ + unsigned long pmcr; + unsigned long pmcntenset; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C; + if (divide64) + pmcr |= ARM_PMU_PMCR_D; + else + pmcr &= ~ARM_PMU_PMCR_D; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + + /* enable all the counters */ + pmcntenset = ~0; + asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset)); + /* clear overflows(just in case) */ + asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset)); +} + +rt_inline unsigned long rt_hw_pmu_get_control(void) +{ + unsigned long pmcr; + asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + return pmcr; +} + +rt_inline unsigned long rt_hw_pmu_get_ceid(void) +{ + unsigned long reg; + /* only PMCEID0 is supported, PMCEID1 is RAZ. */ + asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_cnten(void) +{ + unsigned long pmcnt; + asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt)); + return pmcnt; +} + +rt_inline void rt_hw_pmu_reset_cycle(void) +{ + unsigned long pmcr; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_C; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile ("isb"); +} + +rt_inline void rt_hw_pmu_reset_event(void) +{ + unsigned long pmcr; + + asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_P; + asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile ("isb"); +} + +rt_inline unsigned long rt_hw_pmu_get_cycle(void) +{ + unsigned long cyc; + asm volatile ("isb"); + asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc)); + return cyc; +} + +rt_inline void rt_hw_pmu_select_counter(int idx) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx)); + /* Linux add an isb here, don't know why here. */ + asm volatile ("isb"); +} + +rt_inline void rt_hw_pmu_select_event(int idx, + enum rt_hw_pmu_event_type eve) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + rt_hw_pmu_select_counter(idx); + asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve)); +} + +rt_inline unsigned long rt_hw_pmu_read_counter(int idx) +{ + unsigned long reg; + + rt_hw_pmu_select_counter(idx); + asm volatile ("isb"); + asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_ovsr(void) +{ + unsigned long reg; + asm volatile ("isb"); + asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); + return reg; +} + +rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) +{ + asm ("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg)); + asm volatile ("isb"); +} + +#endif + +void rt_hw_pmu_dump_feature(void); + +#endif /* end of include guard: __PMU_H__ */ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/stack.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/stack.c new file mode 100644 index 0000000000..d76b8a428a --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/stack.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + +#ifdef RT_USING_LWP + *(--stk) = 0; /* user lr */ + *(--stk) = 0; /* user sp*/ +#endif + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/start_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/start_gcc.S new file mode 100644 index 0000000000..014846f3aa --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/start_gcc.S @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + * 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks + * and switches to a new thread + */ + +#include "rtconfig.h" +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000400 +.equ ABT_Stack_Size, 0x00000000 +.equ RT_FIQ_STACK_PGSZ, 0x00000000 +.equ RT_IRQ_STACK_PGSZ, 0x00000800 +.equ USR_Stack_Size, 0x00000400 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) + +.section .data.share.isr +/* stack */ +.globl stack_start +.globl stack_top + +stack_start: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top: + +.text +/* reset entry */ +.globl _reset +_reset: + /* set the cpu to SVC32 mode and disable interrupt */ + cps #Mode_SVC + + /* disable the data alignment check */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, #(1<<1) + mcr p15, 0, r1, c1, c0, 0 + + /* setup stack */ + bl stack_setup + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + +#ifdef RT_USING_SMP + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 //enable smp +#endif + + /* initialize the mmu table and enable mmu */ + ldr r0, =platform_mem_desc + ldr r1, =platform_mem_desc_size + ldr r1, [r1] + bl rt_hw_init_mmu_table + bl rt_hw_mmu_init + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup +_rtthread_startup: + .word rtthread_startup + +stack_setup: + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_FIQ_STACK_PGSZ + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_IRQ_STACK_PGSZ + + /* come back to SVC mode */ + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + bx lr + +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ +.section .text.isr, "ax" + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc, lr, #4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + +.globl rt_current_thread +.globl vmm_thread +.globl vmm_virq_check + + .align 5 +.globl vector_irq +vector_irq: +#ifdef RT_USING_SMP + clrex + + stmfd sp!, {r0, r1} + cps #Mode_SVC + mov r0, sp /* svc_sp */ + mov r1, lr /* svc_lr */ + + cps #Mode_IRQ + sub lr, #4 + stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ + stmfd r0!, {r2 - r12} + ldmfd sp!, {r1, r2} /* original r0, r1 */ + stmfd r0!, {r1 - r2} + mrs r1, spsr /* original mode */ + stmfd r0!, {r1} + +#ifdef RT_USING_LWP + stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ + sub r0, #8 +#endif + /* now irq stack is clean */ + /* r0 is task svc_sp */ + /* backup r0 -> r8 */ + mov r8, r0 + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + cps #Mode_SVC + mov sp, r8 + mov r0, r8 + bl rt_scheduler_do_irq_switch + + b rt_hw_context_switch_exit + +#else + stmfd sp!, {r0-r12,lr} + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. If the usr mode guest is + @ interrupted, this will just switch to the stack of kernel space. + @ save the registers in kernel space won't trigger data abort. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + +#ifdef RT_USING_LWP + stmfd sp, {r13, r14}^ @push usr_sp, usr_lr + sub sp, #8 +#endif + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] @ get new task's stack pointer + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr + add sp, #8 +#endif + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +#endif + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 +.weak vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + bl rt_hw_trap_undef + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . + +#ifdef RT_USING_SMP +.global set_secondary_cpu_boot_address +set_secondary_cpu_boot_address: + ldr r0, =secondary_cpu_start + + mvn r1, #0 //0xffffffff + ldr r2, =0x10000034 + str r1, [r2] + str r0, [r2, #-4] + mov pc, lr + +.global secondary_cpu_start +secondary_cpu_start: + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 //enable smp + + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1<<13) + mcr p15, 0, r0, c1, c0, 0 + + cps #Mode_IRQ + ldr sp, =irq_stack_2_limit + + cps #Mode_FIQ + ldr sp, =irq_stack_2_limit + + cps #Mode_SVC + ldr sp, =svc_stack_2_limit + + /* initialize the mmu table and enable mmu */ + bl rt_hw_mmu_init + + b secondary_cpu_c_start +#endif + +.bss +.align 2 //align to 2~2=4 +svc_stack_2: + .space (1 << 10) +svc_stack_2_limit: + +irq_stack_2: + .space (1 << 10) +irq_stack_2_limit: + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/trap.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/trap.c new file mode 100644 index 0000000000..a25f6ac862 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/trap.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include + +#include "armv7.h" +#include "interrupt.h" + +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +void rt_hw_trap_irq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + +void rt_hw_trap_fiq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/vector_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/vector_gcc.S new file mode 100644 index 0000000000..60d3c6cf1d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-a/vector_gcc.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_gcc.S new file mode 100644 index 0000000000..d9993247e2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_gcc.S @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + * 2012-06-01 aozima set pendsv priority to 0xFF. + * 2012-08-17 aozima fixed bug: store r8 - r11. + * 2013-02-20 aozima port to gcc. + * 2013-06-18 aozima add restore MSP feature. + * 2013-11-04 bright fixed hardfault bug for gcc. + */ + + .cpu cortex-m0 + .fpu softvfp + .syntax unified + .thumb + .text + + .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ + .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ + .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ + .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ + .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + .global rt_hw_interrupt_disable + .type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS R0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .global rt_hw_interrupt_enable + .type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, R0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * R0 --> from + * R1 --> to + */ + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function + .global rt_hw_context_switch + .type rt_hw_context_switch, %function +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOVS R3, #1 + STR R3, [R2] + + LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR R0, [R2] + +_reswitch: + LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR R1, [R2] + + LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + BX LR + +/* R0 --> switch from thread stack + * R1 --> switch to thread stack + * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack + */ + .global PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS R2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CMP R1, #0x00 + BEQ pendsv_exit /* pendsv aLReady handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =rt_interrupt_from_thread + LDR R1, [R0] + CMP R1, #0x00 + BEQ switch_to_thread /* skip register save at the first time */ + + MRS R1, PSP /* get from thread stack pointer */ + + SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */ + LDR R0, [R0] + STR R1, [R0] /* update from thread stack pointer */ + + STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */ + + MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */ + MOV R5, R9 + MOV R6, R10 + MOV R7, R11 + STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */ +switch_to_thread: + LDR R1, =rt_interrupt_to_thread + LDR R1, [R1] + LDR R1, [R1] /* load thread stack pointer */ + + LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */ + PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */ + + LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */ + MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */ + MOV R9, R5 + MOV R10, R6 + MOV R11, R7 + + POP {R4 - R7} /* pop {R4 - R7} from MSP */ + + MSR PSP, R1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, R2 + + MOVS R0, #0x04 + RSBS R0, R0, #0x00 + BX R0 +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * R0 --> to + */ + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR R1, =rt_interrupt_to_thread + STR R0, [R1] + + /* set from thread to 0 */ + LDR R1, =rt_interrupt_from_thread + MOVS R0, #0 + STR R0, [R1] + + /* set interrupt flag to 1 */ + LDR R1, =rt_thread_switch_interrupt_flag + MOVS R0, #1 + STR R0, [R1] + + /* set the PendSV exception priority */ + LDR R0, =NVIC_SHPR3 + LDR R1, =NVIC_PENDSV_PRI + LDR R2, [R0,#0x00] /* read */ + ORRS R1, R1, R2 /* modify */ + STR R1, [R0] /* write-back */ + + LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + NOP + /* restore MSP */ + LDR R0, =SCB_VTOR + LDR R0, [R0] + LDR R0, [R0] + NOP + MSR MSP, R0 + + /* enable interrupts at processor level */ + CPSIE I + + /* never reach here! */ + +/* compatible with old version */ + .global rt_hw_interrupt_thread_switch + .type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX LR + NOP + + .global HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS R0, PSP /* get fault thread stack pointer */ + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {PC} + + +/* + * rt_uint32_t rt_hw_interrupt_check(void); + * R0 --> state + */ + .global rt_hw_interrupt_check + .type rt_hw_interrupt_check, %function +rt_hw_interrupt_check: + MRS R0, IPSR + BX LR diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_iar.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_iar.S new file mode 100644 index 0000000000..50d3781359 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_iar.S @@ -0,0 +1,206 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; * 2013-06-18 aozima add restore MSP feature. +; */ + +;/** +; * @addtogroup CORTEX-M0 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, r0, #0x00 + BX r0 + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + NOP + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_rvds.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_rvds.S new file mode 100644 index 0000000000..fb9ce9b4bf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/context_rvds.S @@ -0,0 +1,215 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; * 2013-06-18 aozima add restore MSP feature. +; */ + +;/** +; * @addtogroup CORTEX-M0 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x01 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, r0, #0x00 + BX r0 + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + +HardFault_Handler PROC + EXPORT HardFault_Handler + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + ENDP + + ALIGN 4 + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/cpuport.c new file mode 100644 index 0000000000..5d36fa11fe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m0/cpuport.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + * 2012-05-31 aozima Merge all of the C source code into cpuport.c + * 2012-08-17 aozima fixed bug: store r8 - r11. + * 2012-12-23 aozima stack addr align to 8byte. + */ + +#include + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +struct stack_frame +{ + /* r4 ~ r7 low register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + + /* r8 ~ r11 high register */ + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + + struct exception_stack_frame exception_stack_frame; +}; + +/* flag in interrupt handling */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + + /* return task's current stack address */ + return stk; +} + +extern long list_thread(void); +extern rt_thread_t rt_current_thread; +/** + * fault exception handling + */ +void rt_hw_hard_fault_exception(struct exception_stack_frame *contex) +{ + rt_kprintf("psr: 0x%08x\n", contex->psr); + rt_kprintf(" pc: 0x%08x\n", contex->pc); + rt_kprintf(" lr: 0x%08x\n", contex->lr); + rt_kprintf("r12: 0x%08x\n", contex->r12); + rt_kprintf("r03: 0x%08x\n", contex->r3); + rt_kprintf("r02: 0x%08x\n", contex->r2); + rt_kprintf("r01: 0x%08x\n", contex->r1); + rt_kprintf("r00: 0x%08x\n", contex->r0); + + rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + + while (1); +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED00) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_gcc.S new file mode 100644 index 0000000000..d17a8aa12c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_gcc.S @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard First version + * 2010-12-29 onelife Modify for EFM32 + * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S + * 2011-07-12 onelife Add interrupt context check function + * 2013-06-18 aozima add restore MSP feature. + * 2013-07-09 aozima enhancement hard fault exception handler. + */ + + .cpu cortex-m3 + .fpu softvfp + .syntax unified + .thumb + .text + + .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ + .equ ICSR, 0xE000ED04 /* interrupt control state register */ + .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ + + .equ SHPR3, 0xE000ED20 /* system priority register (3) */ + .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + .global rt_hw_interrupt_disable + .type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS R0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .global rt_hw_interrupt_enable + .type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, R0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * R0 --> from + * R1 --> to + */ + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function + .global rt_hw_context_switch + .type rt_hw_context_switch, %function +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOV R3, #1 + STR R3, [R2] + + LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR R0, [R2] + +_reswitch: + LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR R1, [R2] + + LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ + LDR R1, =PENDSVSET_BIT + STR R1, [R0] + BX LR + +/* R0 --> switch from thread stack + * R1 --> switch to thread stack + * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack + */ + .global PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS R2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CBZ R1, pendsv_exit /* pendsv aLReady handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV R1, #0 + STR R1, [R0] + + LDR R0, =rt_interrupt_from_thread + LDR R1, [R0] + CBZ R1, switch_to_thread /* skip register save at the first time */ + + MRS R1, PSP /* get from thread stack pointer */ + STMFD R1!, {R4 - R11} /* push R4 - R11 register */ + LDR R0, [R0] + STR R1, [R0] /* update from thread stack pointer */ + +switch_to_thread: + LDR R1, =rt_interrupt_to_thread + LDR R1, [R1] + LDR R1, [R1] /* load thread stack pointer */ + + LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */ + MSR PSP, R1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, R2 + + ORR LR, LR, #0x04 + BX LR + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * R0 --> to + */ + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR R1, =rt_interrupt_to_thread + STR R0, [R1] + + /* set from thread to 0 */ + LDR R1, =rt_interrupt_from_thread + MOV R0, #0 + STR R0, [R1] + + /* set interrupt flag to 1 */ + LDR R1, =rt_thread_switch_interrupt_flag + MOV R0, #1 + STR R0, [R1] + + /* set the PendSV exception priority */ + LDR R0, =SHPR3 + LDR R1, =PENDSV_PRI_LOWEST + LDR.W R2, [R0,#0] /* read */ + ORR R1, R1, R2 /* modify */ + STR R1, [R0] /* write-back */ + + LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ + LDR R1, =PENDSVSET_BIT + STR R1, [R0] + + /* restore MSP */ + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + /* enable interrupts at processor level */ + CPSIE F + CPSIE I + + /* never reach here! */ + +/* compatible with old version */ + .global rt_hw_interrupt_thread_switch + .type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX LR + NOP + + .global HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS r0, msp /* get fault context from handler. */ + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ _get_sp_done + MRS r0, psp /* get fault context from thread. */ +_get_sp_done: + + STMFD r0!, {r4 - r11} /* push r4 - r11 register */ + STMFD r0!, {lr} /* push exec_return register */ + + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ _update_msp + MSR psp, r0 /* update stack pointer to PSP. */ + B _update_done +_update_msp: + MSR msp, r0 /* update stack pointer to MSP. */ +_update_done: + + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {LR} + + ORR LR, LR, #0x04 + BX LR + +/* + * rt_uint32_t rt_hw_interrupt_check(void); + * R0 --> state + */ + .global rt_hw_interrupt_check + .type rt_hw_interrupt_check, %function +rt_hw_interrupt_check: + MRS R0, IPSR + BX LR diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_iar.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_iar.S new file mode 100644 index 0000000000..91645c48b3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_iar.S @@ -0,0 +1,202 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-07-09 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m3 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, msp ; get fault context from handler. + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ _get_sp_done + MRS r0, psp ; get fault context from thread. +_get_sp_done + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + ;STMFD r0!, {lr} ; push exec_return register + SUB r0, r0, #0x04 + STR lr, [r0] + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ _update_msp + MSR psp, r0 ; update stack pointer to PSP. + B _update_done +_update_msp + MSR msp, r0 ; update stack pointer to MSP. +_update_done + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_rvds.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_rvds.S new file mode 100644 index 0000000000..a2a7f41a27 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/context_rvds.S @@ -0,0 +1,207 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-07-09 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup CORTEX-M3 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + TST lr, #0x04 ; if(!EXC_RETURN[2]) + ITE EQ + MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. + MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + STMFD r0!, {lr} ; push exec_return register + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + ITE EQ + MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP. + MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP. + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + ALIGN 4 + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/cpuport.c new file mode 100644 index 0000000000..a386747750 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m3/cpuport.c @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + * 2011-02-14 onelife Modify for EFM32 + * 2011-06-17 onelife Merge all of the C source code into cpuport.c + * 2012-12-23 aozima stack addr align to 8byte. + * 2012-12-29 Bernard Add exception hook. + * 2013-07-09 aozima enhancement hard fault exception handler. + */ + +#include + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +struct stack_frame +{ + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + + struct exception_stack_frame exception_stack_frame; +}; + +/* flag in interrupt handling */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; +/* exception hook */ +static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + + /* return task's current stack address */ + return stk; +} + +/** + * This function set the hook, which is invoked on fault exception handling. + * + * @param exception_handle the exception handling hook function. + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context)) +{ + rt_exception_hook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +#ifdef RT_USING_FINSH +static void usage_fault_track(void) +{ + rt_kprintf("usage fault:\n"); + rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + { + /* [0]:UNDEFINSTR */ + rt_kprintf("UNDEFINSTR "); + } + + if(SCB_CFSR_UFSR & (1<<1)) + { + /* [1]:INVSTATE */ + rt_kprintf("INVSTATE "); + } + + if(SCB_CFSR_UFSR & (1<<2)) + { + /* [2]:INVPC */ + rt_kprintf("INVPC "); + } + + if(SCB_CFSR_UFSR & (1<<3)) + { + /* [3]:NOCP */ + rt_kprintf("NOCP "); + } + + if(SCB_CFSR_UFSR & (1<<8)) + { + /* [8]:UNALIGNED */ + rt_kprintf("UNALIGNED "); + } + + if(SCB_CFSR_UFSR & (1<<9)) + { + /* [9]:DIVBYZERO */ + rt_kprintf("DIVBYZERO "); + } + + rt_kprintf("\n"); +} + +static void bus_fault_track(void) +{ + rt_kprintf("bus fault:\n"); + rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + { + /* [0]:IBUSERR */ + rt_kprintf("IBUSERR "); + } + + if(SCB_CFSR_BFSR & (1<<1)) + { + /* [1]:PRECISERR */ + rt_kprintf("PRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<2)) + { + /* [2]:IMPRECISERR */ + rt_kprintf("IMPRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<3)) + { + /* [3]:UNSTKERR */ + rt_kprintf("UNSTKERR "); + } + + if(SCB_CFSR_BFSR & (1<<4)) + { + /* [4]:STKERR */ + rt_kprintf("STKERR "); + } + + if(SCB_CFSR_BFSR & (1<<7)) + { + rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void mem_manage_fault_track(void) +{ + rt_kprintf("mem manage fault:\n"); + rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + { + /* [0]:IACCVIOL */ + rt_kprintf("IACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<1)) + { + /* [1]:DACCVIOL */ + rt_kprintf("DACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<3)) + { + /* [3]:MUNSTKERR */ + rt_kprintf("MUNSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<4)) + { + /* [4]:MSTKERR */ + rt_kprintf("MSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<7)) + { + /* [7]:MMARVALID */ + rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void hard_fault_track(void) +{ + if(SCB_HFSR & (1UL<<1)) + { + /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ + rt_kprintf("failed vector fetch\n"); + } + + if(SCB_HFSR & (1UL<<30)) + { + /* [30]:FORCED, Indicates hard fault is taken because of bus fault, + memory management fault, or usage fault. */ + if(SCB_CFSR_BFSR) + { + bus_fault_track(); + } + + if(SCB_CFSR_MFSR) + { + mem_manage_fault_track(); + } + + if(SCB_CFSR_UFSR) + { + usage_fault_track(); + } + } + + if(SCB_HFSR & (1UL<<31)) + { + /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ + rt_kprintf("debug event\n"); + } +} +#endif /* RT_USING_FINSH */ + +struct exception_info +{ + rt_uint32_t exc_return; + struct stack_frame stack_frame; +}; + +/* + * fault exception handler + */ +void rt_hw_hard_fault_exception(struct exception_info * exception_info) +{ + extern long list_thread(void); + struct stack_frame* context = &exception_info->stack_frame; + + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(exception_info); + if (result == RT_EOK) + return; + } + + rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); + + rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); + rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); + rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); + rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); + rt_kprintf("r04: 0x%08x\n", context->r4); + rt_kprintf("r05: 0x%08x\n", context->r5); + rt_kprintf("r06: 0x%08x\n", context->r6); + rt_kprintf("r07: 0x%08x\n", context->r7); + rt_kprintf("r08: 0x%08x\n", context->r8); + rt_kprintf("r09: 0x%08x\n", context->r9); + rt_kprintf("r10: 0x%08x\n", context->r10); + rt_kprintf("r11: 0x%08x\n", context->r11); + rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); + rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); + rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); + + if(exception_info->exc_return & (1 << 2) ) + { + rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif /* RT_USING_FINSH */ + } + else + { + rt_kprintf("hard fault on handler\r\n\r\n"); + } + +#ifdef RT_USING_FINSH + hard_fault_track(); +#endif /* RT_USING_FINSH */ + + while (1); +} + +/** + * shutdown CPU + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +#if defined(__CC_ARM) +__asm int __rt_ffs(int value) +{ + CMP r0, #0x00 + BEQ exit + + RBIT r0, r0 + CLZ r0, r0 + ADDS r0, r0, #0x01 + +exit + BX lr +} +#elif defined(__IAR_SYSTEMS_ICC__) +int __rt_ffs(int value) +{ + if (value == 0) return value; + + asm("RBIT %0, %1" : "=r"(value) : "r"(value)); + asm("CLZ %0, %1" : "=r"(value) : "r"(value)); + asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); + + return value; +} +#elif defined(__GNUC__) +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_gcc.S new file mode 100644 index 0000000000..420f4f8ae3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_gcc.S @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + * 2012-01-01 aozima support context switch load/store FPU register. + * 2013-06-18 aozima add restore MSP feature. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + */ + +/** + * @addtogroup cortex-m4 + */ +/*@{*/ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ +.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ +.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ +.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +.global rt_hw_context_switch +.type rt_hw_context_switch, %function + +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR r0, [r2] + +_reswitch: + LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +/* r0 --> switch from thread stack + * r1 --> switch to thread stack + * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS r2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit /* pendsv already handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread /* skip register save at the first time */ + + MRS r1, psp /* get from thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ +#endif + + STMFD r1!, {r4 - r11} /* push r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + MOV r4, #0x00 /* flag = 0 */ + + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + MOVEQ r4, #0x01 /* flag = 1 */ + + STMFD r1!, {r4} /* push flag */ +#endif + + LDR r0, [r0] + STR r1, [r0] /* update from thread stack pointer */ + +switch_to_thread: + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] /* load thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + LDMFD r1!, {r3} /* pop flag */ +#endif + + LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + CMP r3, #0 /* if(flag_r3 != 0) */ + VLDMIANE r1!, {d8 - d15} /* pop FPU register s16~s31 */ +#endif + + MSR psp, r1 /* update stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ORR lr, lr, #0x10 /* lr |= (1 << 4), clean FPCA. */ + CMP r3, #0 /* if(flag_r3 != 0) */ + BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */ +#endif + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + /* CLEAR CONTROL.FPCA */ + MRS r2, CONTROL /* read */ + BIC r2, #0x04 /* modify */ + MSR CONTROL, r2 /* write-back */ +#endif + + /* set from thread to 0 */ + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + /* set interrupt flag to 1 */ + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + /* set the PendSV exception priority */ + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] /* read */ + ORR r1,r1,r2 /* modify */ + STR r1, [r0] /* write-back */ + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + /* restore MSP */ + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + /* enable interrupts at processor level */ + CPSIE F + CPSIE I + + /* never reach here! */ + +/* compatible with old version */ +.global rt_hw_interrupt_thread_switch +.type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX lr + NOP + +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS r0, msp /* get fault context from handler. */ + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ _get_sp_done + MRS r0, psp /* get fault context from thread. */ +_get_sp_done: + + STMFD r0!, {r4 - r11} /* push r4 - r11 register */ +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + STMFD r0!, {lr} /* push dummy for flag */ +#endif + STMFD r0!, {lr} /* push exec_return register */ + + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ _update_msp + MSR psp, r0 /* update stack pointer to PSP. */ + B _update_done +_update_msp: + MSR msp, r0 /* update stack pointer to MSP. */ +_update_done: + + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {LR} + + ORR lr, lr, #0x04 + BX lr diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_iar.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_iar.S new file mode 100644 index 0000000000..06b8c7f884 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_iar.S @@ -0,0 +1,253 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; * 2012-01-01 aozima support context switch load/store FPU register. +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-06-23 aozima support lazy stack optimized. +; * 2018-07-24 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m4 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + +#if defined ( __ARMVFP__ ) + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE skip_push_fpu + VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 +skip_push_fpu +#endif + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + +#if defined ( __ARMVFP__ ) + MOV r4, #0x00 ; flag = 0 + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE push_flag + MOV r4, #0x01 ; flag = 1 +push_flag + ;STMFD r1!, {r4} ; push flag + SUB r1, r1, #0x04 + STR r4, [r1] +#endif + + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + +#if defined ( __ARMVFP__ ) + LDMFD r1!, {r3} ; pop flag +#endif + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + +#if defined ( __ARMVFP__ ) + CBZ r3, skip_pop_fpu + VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 +skip_pop_fpu +#endif + + MSR psp, r1 ; update stack pointer + +#if defined ( __ARMVFP__ ) + ORR lr, lr, #0x10 ; lr |= (1 << 4), clean FPCA. + CBZ r3, return_without_fpu ; if(flag_r3 != 0) + BIC lr, lr, #0x10 ; lr &= ~(1 << 4), set FPCA. +return_without_fpu +#endif + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + +#if defined ( __ARMVFP__ ) + ; CLEAR CONTROL.FPCA + MRS r2, CONTROL ; read + BIC r2, r2, #0x04 ; modify + MSR CONTROL, r2 ; write-back +#endif + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, msp ; get fault context from handler. + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ _get_sp_done + MRS r0, psp ; get fault context from thread. +_get_sp_done + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + ;STMFD r0!, {lr} ; push exec_return register +#if defined ( __ARMVFP__ ) + SUB r0, r0, #0x04 ; push dummy for flag + STR lr, [r0] +#endif + SUB r0, r0, #0x04 + STR lr, [r0] + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ _update_msp + MSR psp, r0 ; update stack pointer to PSP. + B _update_done +_update_msp + MSR msp, r0 ; update stack pointer to MSP. +_update_done + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_rvds.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_rvds.S new file mode 100644 index 0000000000..f6d2447c5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/context_rvds.S @@ -0,0 +1,251 @@ +;/* +;* Copyright (c) 2006-2018, RT-Thread Development Team +;* +;* SPDX-License-Identifier: Apache-2.0 +;* +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version. +; * 2012-01-01 aozima support context switch load/store FPU register. +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-06-23 aozima support lazy stack optimized. +; * 2018-07-24 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m4 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + IF {FPU} != "SoftVFP" + TST lr, #0x10 ; if(!EXC_RETURN[4]) + VSTMFDEQ r1!, {d8 - d15} ; push FPU register s16~s31 + ENDIF + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + + IF {FPU} != "SoftVFP" + MOV r4, #0x00 ; flag = 0 + + TST lr, #0x10 ; if(!EXC_RETURN[4]) + MOVEQ r4, #0x01 ; flag = 1 + + STMFD r1!, {r4} ; push flag + ENDIF + + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + IF {FPU} != "SoftVFP" + LDMFD r1!, {r3} ; pop flag + ENDIF + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + + IF {FPU} != "SoftVFP" + CMP r3, #0 ; if(flag_r3 != 0) + VLDMFDNE r1!, {d8 - d15} ; pop FPU register s16~s31 + ENDIF + + MSR psp, r1 ; update stack pointer + + IF {FPU} != "SoftVFP" + ORR lr, lr, #0x10 ; lr |= (1 << 4), clean FPCA. + CMP r3, #0 ; if(flag_r3 != 0) + BICNE lr, lr, #0x10 ; lr &= ~(1 << 4), set FPCA. + ENDIF + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + IF {FPU} != "SoftVFP" + ; CLEAR CONTROL.FPCA + MRS r2, CONTROL ; read + BIC r2, #0x04 ; modify + MSR CONTROL, r2 ; write-back + ENDIF + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + TST lr, #0x04 ; if(!EXC_RETURN[2]) + ITE EQ + MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. + MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + IF {FPU} != "SoftVFP" + STMFD r0!, {lr} ; push dummy for flag + ENDIF + STMFD r0!, {lr} ; push exec_return register + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + ITE EQ + MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP. + MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP. + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + ALIGN 4 + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/cpuport.c new file mode 100644 index 0000000000..18f027895b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m4/cpuport.c @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-10-21 Bernard the first version. + * 2011-10-27 aozima update for cortex-M4 FPU. + * 2011-12-31 aozima fixed stack align issues. + * 2012-01-01 aozima support context switch load/store FPU register. + * 2012-12-11 lgnq fixed the coding style. + * 2012-12-23 aozima stack addr align to 8byte. + * 2012-12-29 Bernard Add exception hook. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + */ + +#include + +#if /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ + /* Clang */ || (defined ( __CLANG_ARM ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \ + /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ + /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) +#define USE_FPU 1 +#else +#define USE_FPU 0 +#endif + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; +/* exception hook */ +static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +struct stack_frame +{ +#if USE_FPU + rt_uint32_t flag; +#endif /* USE_FPU */ + + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + + struct exception_stack_frame exception_stack_frame; +}; + +struct exception_stack_frame_fpu +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; + +#if USE_FPU + /* FPU register */ + rt_uint32_t S0; + rt_uint32_t S1; + rt_uint32_t S2; + rt_uint32_t S3; + rt_uint32_t S4; + rt_uint32_t S5; + rt_uint32_t S6; + rt_uint32_t S7; + rt_uint32_t S8; + rt_uint32_t S9; + rt_uint32_t S10; + rt_uint32_t S11; + rt_uint32_t S12; + rt_uint32_t S13; + rt_uint32_t S14; + rt_uint32_t S15; + rt_uint32_t FPSCR; + rt_uint32_t NO_NAME; +#endif +}; + +struct stack_frame_fpu +{ + rt_uint32_t flag; + + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + +#if USE_FPU + /* FPU register s16 ~ s31 */ + rt_uint32_t s16; + rt_uint32_t s17; + rt_uint32_t s18; + rt_uint32_t s19; + rt_uint32_t s20; + rt_uint32_t s21; + rt_uint32_t s22; + rt_uint32_t s23; + rt_uint32_t s24; + rt_uint32_t s25; + rt_uint32_t s26; + rt_uint32_t s27; + rt_uint32_t s28; + rt_uint32_t s29; + rt_uint32_t s30; + rt_uint32_t s31; +#endif + + struct exception_stack_frame_fpu exception_stack_frame; +}; + +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + +#if USE_FPU + stack_frame->flag = 0; +#endif /* USE_FPU */ + + /* return task's current stack address */ + return stk; +} + +/** + * This function set the hook, which is invoked on fault exception handling. + * + * @param exception_handle the exception handling hook function. + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) +{ + rt_exception_hook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +#ifdef RT_USING_FINSH +static void usage_fault_track(void) +{ + rt_kprintf("usage fault:\n"); + rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + { + /* [0]:UNDEFINSTR */ + rt_kprintf("UNDEFINSTR "); + } + + if(SCB_CFSR_UFSR & (1<<1)) + { + /* [1]:INVSTATE */ + rt_kprintf("INVSTATE "); + } + + if(SCB_CFSR_UFSR & (1<<2)) + { + /* [2]:INVPC */ + rt_kprintf("INVPC "); + } + + if(SCB_CFSR_UFSR & (1<<3)) + { + /* [3]:NOCP */ + rt_kprintf("NOCP "); + } + + if(SCB_CFSR_UFSR & (1<<8)) + { + /* [8]:UNALIGNED */ + rt_kprintf("UNALIGNED "); + } + + if(SCB_CFSR_UFSR & (1<<9)) + { + /* [9]:DIVBYZERO */ + rt_kprintf("DIVBYZERO "); + } + + rt_kprintf("\n"); +} + +static void bus_fault_track(void) +{ + rt_kprintf("bus fault:\n"); + rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + { + /* [0]:IBUSERR */ + rt_kprintf("IBUSERR "); + } + + if(SCB_CFSR_BFSR & (1<<1)) + { + /* [1]:PRECISERR */ + rt_kprintf("PRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<2)) + { + /* [2]:IMPRECISERR */ + rt_kprintf("IMPRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<3)) + { + /* [3]:UNSTKERR */ + rt_kprintf("UNSTKERR "); + } + + if(SCB_CFSR_BFSR & (1<<4)) + { + /* [4]:STKERR */ + rt_kprintf("STKERR "); + } + + if(SCB_CFSR_BFSR & (1<<7)) + { + rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void mem_manage_fault_track(void) +{ + rt_kprintf("mem manage fault:\n"); + rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + { + /* [0]:IACCVIOL */ + rt_kprintf("IACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<1)) + { + /* [1]:DACCVIOL */ + rt_kprintf("DACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<3)) + { + /* [3]:MUNSTKERR */ + rt_kprintf("MUNSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<4)) + { + /* [4]:MSTKERR */ + rt_kprintf("MSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<7)) + { + /* [7]:MMARVALID */ + rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void hard_fault_track(void) +{ + if(SCB_HFSR & (1UL<<1)) + { + /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ + rt_kprintf("failed vector fetch\n"); + } + + if(SCB_HFSR & (1UL<<30)) + { + /* [30]:FORCED, Indicates hard fault is taken because of bus fault, + memory management fault, or usage fault. */ + if(SCB_CFSR_BFSR) + { + bus_fault_track(); + } + + if(SCB_CFSR_MFSR) + { + mem_manage_fault_track(); + } + + if(SCB_CFSR_UFSR) + { + usage_fault_track(); + } + } + + if(SCB_HFSR & (1UL<<31)) + { + /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ + rt_kprintf("debug event\n"); + } +} +#endif /* RT_USING_FINSH */ + +struct exception_info +{ + rt_uint32_t exc_return; + struct stack_frame stack_frame; +}; + +void rt_hw_hard_fault_exception(struct exception_info *exception_info) +{ + extern long list_thread(void); + struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame; + struct stack_frame *context = &exception_info->stack_frame; + + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(exception_stack); + if (result == RT_EOK) return; + } + + rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); + + rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); + rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); + rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); + rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); + rt_kprintf("r04: 0x%08x\n", context->r4); + rt_kprintf("r05: 0x%08x\n", context->r5); + rt_kprintf("r06: 0x%08x\n", context->r6); + rt_kprintf("r07: 0x%08x\n", context->r7); + rt_kprintf("r08: 0x%08x\n", context->r8); + rt_kprintf("r09: 0x%08x\n", context->r9); + rt_kprintf("r10: 0x%08x\n", context->r10); + rt_kprintf("r11: 0x%08x\n", context->r11); + rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); + rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); + rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); + + if (exception_info->exc_return & (1 << 2)) + { + rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + } + else + { + rt_kprintf("hard fault on handler\r\n\r\n"); + } + + if ( (exception_info->exc_return & 0x10) == 0) + { + rt_kprintf("FPU active!\r\n"); + } + +#ifdef RT_USING_FINSH + hard_fault_track(); +#endif /* RT_USING_FINSH */ + + while (1); +} + +/** + * shutdown CPU + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__asm int __rt_ffs(int value) +{ + CMP r0, #0x00 + BEQ exit + + RBIT r0, r0 + CLZ r0, r0 + ADDS r0, r0, #0x01 + +exit + BX lr +} +#elif defined(__IAR_SYSTEMS_ICC__) +int __rt_ffs(int value) +{ + if (value == 0) return value; + + asm("RBIT %0, %1" : "=r"(value) : "r"(value)); + asm("CLZ %0, %1" : "=r"(value) : "r"(value)); + asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); + + return value; +} +#elif defined(__GNUC__) +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_gcc.S new file mode 100644 index 0000000000..420f4f8ae3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_gcc.S @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + * 2012-01-01 aozima support context switch load/store FPU register. + * 2013-06-18 aozima add restore MSP feature. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + */ + +/** + * @addtogroup cortex-m4 + */ +/*@{*/ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ +.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ +.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ +.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +.global rt_hw_context_switch +.type rt_hw_context_switch, %function + +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR r0, [r2] + +_reswitch: + LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +/* r0 --> switch from thread stack + * r1 --> switch to thread stack + * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS r2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit /* pendsv already handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread /* skip register save at the first time */ + + MRS r1, psp /* get from thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ +#endif + + STMFD r1!, {r4 - r11} /* push r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + MOV r4, #0x00 /* flag = 0 */ + + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + MOVEQ r4, #0x01 /* flag = 1 */ + + STMFD r1!, {r4} /* push flag */ +#endif + + LDR r0, [r0] + STR r1, [r0] /* update from thread stack pointer */ + +switch_to_thread: + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] /* load thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + LDMFD r1!, {r3} /* pop flag */ +#endif + + LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + CMP r3, #0 /* if(flag_r3 != 0) */ + VLDMIANE r1!, {d8 - d15} /* pop FPU register s16~s31 */ +#endif + + MSR psp, r1 /* update stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ORR lr, lr, #0x10 /* lr |= (1 << 4), clean FPCA. */ + CMP r3, #0 /* if(flag_r3 != 0) */ + BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */ +#endif + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + /* CLEAR CONTROL.FPCA */ + MRS r2, CONTROL /* read */ + BIC r2, #0x04 /* modify */ + MSR CONTROL, r2 /* write-back */ +#endif + + /* set from thread to 0 */ + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + /* set interrupt flag to 1 */ + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + /* set the PendSV exception priority */ + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] /* read */ + ORR r1,r1,r2 /* modify */ + STR r1, [r0] /* write-back */ + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + /* restore MSP */ + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + /* enable interrupts at processor level */ + CPSIE F + CPSIE I + + /* never reach here! */ + +/* compatible with old version */ +.global rt_hw_interrupt_thread_switch +.type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX lr + NOP + +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS r0, msp /* get fault context from handler. */ + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ _get_sp_done + MRS r0, psp /* get fault context from thread. */ +_get_sp_done: + + STMFD r0!, {r4 - r11} /* push r4 - r11 register */ +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + STMFD r0!, {lr} /* push dummy for flag */ +#endif + STMFD r0!, {lr} /* push exec_return register */ + + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ _update_msp + MSR psp, r0 /* update stack pointer to PSP. */ + B _update_done +_update_msp: + MSR msp, r0 /* update stack pointer to MSP. */ +_update_done: + + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {LR} + + ORR lr, lr, #0x04 + BX lr diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_iar.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_iar.S new file mode 100644 index 0000000000..06b8c7f884 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_iar.S @@ -0,0 +1,253 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; * 2012-01-01 aozima support context switch load/store FPU register. +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-06-23 aozima support lazy stack optimized. +; * 2018-07-24 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m4 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + +#if defined ( __ARMVFP__ ) + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE skip_push_fpu + VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 +skip_push_fpu +#endif + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + +#if defined ( __ARMVFP__ ) + MOV r4, #0x00 ; flag = 0 + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE push_flag + MOV r4, #0x01 ; flag = 1 +push_flag + ;STMFD r1!, {r4} ; push flag + SUB r1, r1, #0x04 + STR r4, [r1] +#endif + + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + +#if defined ( __ARMVFP__ ) + LDMFD r1!, {r3} ; pop flag +#endif + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + +#if defined ( __ARMVFP__ ) + CBZ r3, skip_pop_fpu + VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 +skip_pop_fpu +#endif + + MSR psp, r1 ; update stack pointer + +#if defined ( __ARMVFP__ ) + ORR lr, lr, #0x10 ; lr |= (1 << 4), clean FPCA. + CBZ r3, return_without_fpu ; if(flag_r3 != 0) + BIC lr, lr, #0x10 ; lr &= ~(1 << 4), set FPCA. +return_without_fpu +#endif + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + +#if defined ( __ARMVFP__ ) + ; CLEAR CONTROL.FPCA + MRS r2, CONTROL ; read + BIC r2, r2, #0x04 ; modify + MSR CONTROL, r2 ; write-back +#endif + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, msp ; get fault context from handler. + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ _get_sp_done + MRS r0, psp ; get fault context from thread. +_get_sp_done + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + ;STMFD r0!, {lr} ; push exec_return register +#if defined ( __ARMVFP__ ) + SUB r0, r0, #0x04 ; push dummy for flag + STR lr, [r0] +#endif + SUB r0, r0, #0x04 + STR lr, [r0] + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ _update_msp + MSR psp, r0 ; update stack pointer to PSP. + B _update_done +_update_msp + MSR msp, r0 ; update stack pointer to MSP. +_update_done + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_rvds.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_rvds.S new file mode 100644 index 0000000000..ea9e9cb8b3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/context_rvds.S @@ -0,0 +1,253 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version. +; * 2012-01-01 aozima support context switch load/store FPU register. +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-06-23 aozima support lazy stack optimized. +; * 2018-07-24 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m4 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + IF {FPU} != "SoftVFP" + TST lr, #0x10 ; if(!EXC_RETURN[4]) + VSTMFDEQ r1!, {d8 - d15} ; push FPU register s16~s31 + ENDIF + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + + IF {FPU} != "SoftVFP" + MOV r4, #0x00 ; flag = 0 + + TST lr, #0x10 ; if(!EXC_RETURN[4]) + MOVEQ r4, #0x01 ; flag = 1 + + STMFD r1!, {r4} ; push flag + ENDIF + + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + IF {FPU} != "SoftVFP" + LDMFD r1!, {r3} ; pop flag + ENDIF + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + + IF {FPU} != "SoftVFP" + CMP r3, #0 ; if(flag_r3 != 0) + VLDMFDNE r1!, {d8 - d15} ; pop FPU register s16~s31 + ENDIF + + MSR psp, r1 ; update stack pointer + + IF {FPU} != "SoftVFP" + ORR lr, lr, #0x10 ; lr |= (1 << 4), clean FPCA. + CMP r3, #0 ; if(flag_r3 != 0) + BICNE lr, lr, #0x10 ; lr &= ~(1 << 4), set FPCA. + ENDIF + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + IF {FPU} != "SoftVFP" + ; CLEAR CONTROL.FPCA + MRS r2, CONTROL ; read + BIC r2, #0x04 ; modify + MSR CONTROL, r2 ; write-back + ENDIF + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler + EXPORT MemManage_Handler +HardFault_Handler PROC +MemManage_Handler + + ; get current context + TST lr, #0x04 ; if(!EXC_RETURN[2]) + ITE EQ + MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler. + MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread. + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + IF {FPU} != "SoftVFP" + STMFD r0!, {lr} ; push dummy for flag + ENDIF + STMFD r0!, {lr} ; push exec_return register + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + ITE EQ + MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP. + MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP. + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + ALIGN 4 + + END diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/cpu_cache.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/cpu_cache.c new file mode 100644 index 0000000000..4a1a9c2201 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/cpu_cache.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-02 tanek first implementation + * 2019-04-27 misonyo update to cortex-m7 series + */ + +#include +#include +#include + +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +#define L1CACHE_LINESIZE_BYTE (32) + +void rt_hw_cpu_icache_enable(void) +{ + SCB_EnableICache(); +} + +void rt_hw_cpu_icache_disable(void) +{ + SCB_DisableICache(); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +void rt_hw_cpu_icache_ops(int ops, void* addr, int size) +{ + rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1); + rt_int32_t size_byte = size + address - (rt_uint32_t)addr; + rt_uint32_t linesize = 32U; + if (ops & RT_HW_CACHE_INVALIDATE) + { + __DSB(); + while (size_byte > 0) + { + SCB->ICIMVAU = address; + address += linesize; + size_byte -= linesize; + } + __DSB(); + __ISB(); + } +} + +void rt_hw_cpu_dcache_enable(void) +{ + SCB_EnableDCache(); +} + +void rt_hw_cpu_dcache_disable(void) +{ + SCB_DisableDCache(); +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) +{ + rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1); + rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr; + + if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) + { + SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + } + else if (ops & RT_HW_CACHE_FLUSH) + { + SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + } + else if (ops & RT_HW_CACHE_INVALIDATE) + { + SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + } + else + { + RT_ASSERT(0); + } +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/cpuport.c new file mode 100644 index 0000000000..18f027895b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-m7/cpuport.c @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-10-21 Bernard the first version. + * 2011-10-27 aozima update for cortex-M4 FPU. + * 2011-12-31 aozima fixed stack align issues. + * 2012-01-01 aozima support context switch load/store FPU register. + * 2012-12-11 lgnq fixed the coding style. + * 2012-12-23 aozima stack addr align to 8byte. + * 2012-12-29 Bernard Add exception hook. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + */ + +#include + +#if /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ + /* Clang */ || (defined ( __CLANG_ARM ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \ + /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ + /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) +#define USE_FPU 1 +#else +#define USE_FPU 0 +#endif + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; +/* exception hook */ +static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +struct stack_frame +{ +#if USE_FPU + rt_uint32_t flag; +#endif /* USE_FPU */ + + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + + struct exception_stack_frame exception_stack_frame; +}; + +struct exception_stack_frame_fpu +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; + +#if USE_FPU + /* FPU register */ + rt_uint32_t S0; + rt_uint32_t S1; + rt_uint32_t S2; + rt_uint32_t S3; + rt_uint32_t S4; + rt_uint32_t S5; + rt_uint32_t S6; + rt_uint32_t S7; + rt_uint32_t S8; + rt_uint32_t S9; + rt_uint32_t S10; + rt_uint32_t S11; + rt_uint32_t S12; + rt_uint32_t S13; + rt_uint32_t S14; + rt_uint32_t S15; + rt_uint32_t FPSCR; + rt_uint32_t NO_NAME; +#endif +}; + +struct stack_frame_fpu +{ + rt_uint32_t flag; + + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + +#if USE_FPU + /* FPU register s16 ~ s31 */ + rt_uint32_t s16; + rt_uint32_t s17; + rt_uint32_t s18; + rt_uint32_t s19; + rt_uint32_t s20; + rt_uint32_t s21; + rt_uint32_t s22; + rt_uint32_t s23; + rt_uint32_t s24; + rt_uint32_t s25; + rt_uint32_t s26; + rt_uint32_t s27; + rt_uint32_t s28; + rt_uint32_t s29; + rt_uint32_t s30; + rt_uint32_t s31; +#endif + + struct exception_stack_frame_fpu exception_stack_frame; +}; + +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + +#if USE_FPU + stack_frame->flag = 0; +#endif /* USE_FPU */ + + /* return task's current stack address */ + return stk; +} + +/** + * This function set the hook, which is invoked on fault exception handling. + * + * @param exception_handle the exception handling hook function. + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) +{ + rt_exception_hook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +#ifdef RT_USING_FINSH +static void usage_fault_track(void) +{ + rt_kprintf("usage fault:\n"); + rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + { + /* [0]:UNDEFINSTR */ + rt_kprintf("UNDEFINSTR "); + } + + if(SCB_CFSR_UFSR & (1<<1)) + { + /* [1]:INVSTATE */ + rt_kprintf("INVSTATE "); + } + + if(SCB_CFSR_UFSR & (1<<2)) + { + /* [2]:INVPC */ + rt_kprintf("INVPC "); + } + + if(SCB_CFSR_UFSR & (1<<3)) + { + /* [3]:NOCP */ + rt_kprintf("NOCP "); + } + + if(SCB_CFSR_UFSR & (1<<8)) + { + /* [8]:UNALIGNED */ + rt_kprintf("UNALIGNED "); + } + + if(SCB_CFSR_UFSR & (1<<9)) + { + /* [9]:DIVBYZERO */ + rt_kprintf("DIVBYZERO "); + } + + rt_kprintf("\n"); +} + +static void bus_fault_track(void) +{ + rt_kprintf("bus fault:\n"); + rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + { + /* [0]:IBUSERR */ + rt_kprintf("IBUSERR "); + } + + if(SCB_CFSR_BFSR & (1<<1)) + { + /* [1]:PRECISERR */ + rt_kprintf("PRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<2)) + { + /* [2]:IMPRECISERR */ + rt_kprintf("IMPRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<3)) + { + /* [3]:UNSTKERR */ + rt_kprintf("UNSTKERR "); + } + + if(SCB_CFSR_BFSR & (1<<4)) + { + /* [4]:STKERR */ + rt_kprintf("STKERR "); + } + + if(SCB_CFSR_BFSR & (1<<7)) + { + rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void mem_manage_fault_track(void) +{ + rt_kprintf("mem manage fault:\n"); + rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + { + /* [0]:IACCVIOL */ + rt_kprintf("IACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<1)) + { + /* [1]:DACCVIOL */ + rt_kprintf("DACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<3)) + { + /* [3]:MUNSTKERR */ + rt_kprintf("MUNSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<4)) + { + /* [4]:MSTKERR */ + rt_kprintf("MSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<7)) + { + /* [7]:MMARVALID */ + rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void hard_fault_track(void) +{ + if(SCB_HFSR & (1UL<<1)) + { + /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ + rt_kprintf("failed vector fetch\n"); + } + + if(SCB_HFSR & (1UL<<30)) + { + /* [30]:FORCED, Indicates hard fault is taken because of bus fault, + memory management fault, or usage fault. */ + if(SCB_CFSR_BFSR) + { + bus_fault_track(); + } + + if(SCB_CFSR_MFSR) + { + mem_manage_fault_track(); + } + + if(SCB_CFSR_UFSR) + { + usage_fault_track(); + } + } + + if(SCB_HFSR & (1UL<<31)) + { + /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ + rt_kprintf("debug event\n"); + } +} +#endif /* RT_USING_FINSH */ + +struct exception_info +{ + rt_uint32_t exc_return; + struct stack_frame stack_frame; +}; + +void rt_hw_hard_fault_exception(struct exception_info *exception_info) +{ + extern long list_thread(void); + struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame; + struct stack_frame *context = &exception_info->stack_frame; + + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(exception_stack); + if (result == RT_EOK) return; + } + + rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); + + rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); + rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); + rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); + rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); + rt_kprintf("r04: 0x%08x\n", context->r4); + rt_kprintf("r05: 0x%08x\n", context->r5); + rt_kprintf("r06: 0x%08x\n", context->r6); + rt_kprintf("r07: 0x%08x\n", context->r7); + rt_kprintf("r08: 0x%08x\n", context->r8); + rt_kprintf("r09: 0x%08x\n", context->r9); + rt_kprintf("r10: 0x%08x\n", context->r10); + rt_kprintf("r11: 0x%08x\n", context->r11); + rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); + rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); + rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); + + if (exception_info->exc_return & (1 << 2)) + { + rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + } + else + { + rt_kprintf("hard fault on handler\r\n\r\n"); + } + + if ( (exception_info->exc_return & 0x10) == 0) + { + rt_kprintf("FPU active!\r\n"); + } + +#ifdef RT_USING_FINSH + hard_fault_track(); +#endif /* RT_USING_FINSH */ + + while (1); +} + +/** + * shutdown CPU + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +#if defined(__CC_ARM) || defined(__CLANG_ARM) +__asm int __rt_ffs(int value) +{ + CMP r0, #0x00 + BEQ exit + + RBIT r0, r0 + CLZ r0, r0 + ADDS r0, r0, #0x01 + +exit + BX lr +} +#elif defined(__IAR_SYSTEMS_ICC__) +int __rt_ffs(int value) +{ + if (value == 0) return value; + + asm("RBIT %0, %1" : "=r"(value) : "r"(value)); + asm("CLZ %0, %1" : "=r"(value) : "r"(value)); + asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); + + return value; +} +#elif defined(__GNUC__) +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/armv7.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/armv7.h new file mode 100644 index 0000000000..3adcb92c5d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/armv7.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ + +#ifndef VFP_DATA_NR +#define VFP_DATA_NR 32 +#endif + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/context_ccs.asm b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/context_ccs.asm new file mode 100644 index 0000000000..9463556743 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/context_ccs.asm @@ -0,0 +1,260 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-20 Bernard first version +; * 2011-07-22 Bernard added thumb mode porting +; * 2013-05-24 Grissiom port to CCS +; * 2013-05-26 Grissiom optimize for ARMv7 +; */ + + .text + .arm + .ref rt_thread_switch_interrupt_flag + .ref rt_interrupt_from_thread + .ref rt_interrupt_to_thread + .ref rt_interrupt_enter + .ref rt_interrupt_leave + .ref rt_hw_trap_irq + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + .def rt_hw_interrupt_disable + .asmfunc +rt_hw_interrupt_disable + MRS r0, cpsr + CPSID IF + BX lr + .endasmfunc + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + .def rt_hw_interrupt_enable + .asmfunc +rt_hw_interrupt_enable + MSR cpsr_c, r0 + BX lr + .endasmfunc + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + .def rt_hw_context_switch + .asmfunc +rt_hw_context_switch + STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC) + STMDB sp!, {r0-r12, lr} ; push lr & register file + + MRS r4, cpsr + TST lr, #0x01 + ORRNE r4, r4, #0x20 ; it's thumb code + + STMDB sp!, {r4} ; push cpsr + + .if (__TI_VFP_SUPPORT__) + VMRS r4, fpexc + TST r4, #0x40000000 + BEQ __no_vfp_frame1 + VSTMDB sp!, {d0-d15} + VMRS r5, fpscr + ; TODO: add support for Common VFPv3. + ; Save registers like FPINST, FPINST2 + STMDB sp!, {r5} +__no_vfp_frame1 + STMDB sp!, {r4} + .endif + + STR sp, [r0] ; store sp in preempted tasks TCB + LDR sp, [r1] ; get new task stack pointer + + .if (__TI_VFP_SUPPORT__) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 ; restore fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame2 + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame2 + .endif + + LDMIA sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr + .endasmfunc + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + .def rt_hw_context_switch_to + .asmfunc +rt_hw_context_switch_to + LDR sp, [r0] ; get new task stack pointer + + .if (__TI_VFP_SUPPORT__) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_to + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_to + .endif + + LDMIA sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr + .endasmfunc + +;/* +; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); +; */ + + .def rt_hw_context_switch_interrupt + .asmfunc +rt_hw_context_switch_interrupt + LDR r2, pintflag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 + STR r3, [r2] + LDR r2, pfromthread ; set rt_interrupt_from_thread + STR r0, [r2] +_reswitch + LDR r2, ptothread ; set rt_interrupt_to_thread + STR r1, [r2] + BX lr + .endasmfunc + + .def IRQ_Handler +IRQ_Handler + STMDB sp!, {r0-r12,lr} + + .if (__TI_VFP_SUPPORT__) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_str_irq + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + ; TODO: add support for Common VFPv3. + ; Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_str_irq + STMDB sp!, {r0} + .endif + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, pintflag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + .if (__TI_VFP_SUPPORT__) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_ldr_irq + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_ldr_irq + .endif + + LDMIA sp!, {r0-r12,lr} + SUBS pc, lr, #4 + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ + .def rt_hw_context_switch_interrupt_do +rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + .if (__TI_VFP_SUPPORT__) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do1 + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do1 + .endif + + LDMIA sp!, {r0-r12,lr} ; reload saved registers + STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC + ; mode so there is no need to update SP. + SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3. + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + CPSID IF, #0x13 + + STMDB sp!, {r2} ; push old task's pc + STMDB sp!, {r4-r12,lr} ; push old task's lr,r12-r4 + LDMIA r1!, {r4-r7} ; restore r0-r3 of the interrupted thread + STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to + ; r0-r3 because we just want to transfer the data and don't + ; use them here. + STMDB sp!, {r3} ; push old task's cpsr + + .if (__TI_VFP_SUPPORT__) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_do2 + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + ; TODO: add support for Common VFPv3. + ; Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_do2 + STMDB sp!, {r0} + .endif + + LDR r4, pfromthread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, ptothread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + .if (__TI_VFP_SUPPORT__) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do3 + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do3 + .endif + + LDMIA sp!, {r4} ; pop new task's cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr + +pintflag .word rt_thread_switch_interrupt_flag +pfromthread .word rt_interrupt_from_thread +ptothread .word rt_interrupt_to_thread diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/context_gcc.S new file mode 100644 index 0000000000..50e1069c06 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/context_gcc.S @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-20 Bernard first version + * 2011-07-22 Bernard added thumb mode porting + * 2013-05-24 Grissiom port to CCS + * 2013-05-26 Grissiom optimize for ARMv7 + * 2013-10-20 Grissiom port to GCC + */ + +#include + + .text + .arm + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl rt_hw_trap_irq + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, cpsr + CPSID IF + BX lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR cpsr_c, r0 + BX lr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * r0 --> from + * r1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + STMDB sp!, {lr} @ push pc (lr should be pushed in place of PC) + STMDB sp!, {r0-r12, lr} @ push lr & register file + + MRS r4, cpsr + TST lr, #0x01 + ORRNE r4, r4, #0x20 @ it's thumb code + + STMDB sp!, {r4} @ push cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r4, fpexc + TST r4, #0x40000000 + BEQ __no_vfp_frame1 + VSTMDB sp!, {d0-d15} + VMRS r5, fpscr + @ TODO: add support for Common VFPv3. + @ Save registers like FPINST, FPINST2 + STMDB sp!, {r5} +__no_vfp_frame1: + STMDB sp!, {r4} +#endif + + STR sp, [r0] @ store sp in preempted tasks TCB + LDR sp, [r1] @ get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 @ restore fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame2 + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame2: + #endif + + LDMIA sp!, {r4} @ pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_to(rt_uint32 to) + * r0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR sp, [r0] @ get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_to + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_to: +#endif + + LDMIA sp!, {r4} @ pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@ + */ + + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + STR r3, [r2] + LDR r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + + STR r0, [r2] +_reswitch: + LDR r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + STR r1, [r2] + BX lr + + .globl IRQ_Handler +IRQ_Handler: + STMDB sp!, {r0-r12,lr} + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_str_irq + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + @ TODO: add support for Common VFPv3. + @ Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_str_irq: + STMDB sp!, {r0} +#endif + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_ldr_irq + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_ldr_irq: +#endif + + LDMIA sp!, {r0-r12,lr} + SUBS pc, lr, #4 + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_hw_context_switch_interrupt_do +rt_hw_context_switch_interrupt_do: + MOV r1, #0 @ clear flag + STR r1, [r0] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do1 + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do1: +#endif + + LDMIA sp!, {r0-r12,lr} @ reload saved registers + STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC + @ mode so there is no need to update SP. + SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3. + SUB r2, lr, #4 @ save old task's pc to r2 + + MRS r3, spsr @ get cpsr of interrupt thread + + @ switch to SVC mode and no interrupt + CPSID IF, #0x13 + + STMDB sp!, {r2} @ push old task's pc + STMDB sp!, {r4-r12,lr} @ push old task's lr,r12-r4 + LDMIA r1!, {r4-r7} @ restore r0-r3 of the interrupted thread + STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to + @ r0-r3 because we just want to transfer the data and don't + @ use them here. + STMDB sp!, {r3} @ push old task's cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_do2 + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + @ TODO: add support for Common VFPv3. + @ Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_do2: + STMDB sp!, {r0} +#endif + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] @ store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] @ get new task's stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do3 + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do3: +#endif + + LDMIA sp!, {r4} @ pop new task's cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/cpu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/cpu.c new file mode 100644 index 0000000000..d2e8130e7c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/cpu.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-12-11 XuXinming first version + * 2013-05-24 Grissiom port to RM48x50 + */ + +#include + +/** + * @addtogroup RM48x50 + */ +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset() +{ +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +#ifdef __TI_COMPILER_VERSION__ +#ifdef RT_USING_CPU_FFS +int __rt_ffs(int value) +{ + if (value == 0) + return value; + + __asm(" rsb r1, r0, #0"); + __asm(" and r1, r1, r0"); + __asm(" clz r1, r1"); + __asm(" rsb r0, r1, #32"); +} +#endif + +void rt_hw_cpu_icache_enable() +{ + __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable"); + __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored"); + __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache"); + __asm(" ISB"); +} + +void rt_hw_cpu_icache_disable() +{ + __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable"); + __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache"); + __asm(" ISB"); +} + +void rt_hw_cpu_dcache_enable() +{ + __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" ORR R1, R1, #0x1 <<2"); + __asm(" DSB"); + __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache"); + __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache"); +} + +void rt_hw_cpu_dcache_disable() +{ + /* FIXME: Clean entire data cache. This routine depends on the data cache + * size. It can be omitted if it is known that the data cache has no dirty + * data. */ + __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" BIC r1, r1, #0x1 <<2"); + __asm(" DSB"); + __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"); +} + +#elif __GNUC__ +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} +#endif +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/interrupt.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/interrupt.c new file mode 100644 index 0000000000..30e14f5a2d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/interrupt.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-12-11 XuXinming first version + * 2013-03-29 aozima Modify the interrupt interface implementations. + */ + +#include +#include + +#include +#include + +#include "armv7.h" + +#define MAX_HANDLERS 96 + +/* exception and interrupt handler table */ +struct rt_irq_desc irq_desc[MAX_HANDLERS]; + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * @addtogroup RM48x50 + */ + +/*@{*/ + +static void rt_hw_int_not_handle(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +#define vimRAM (0xFFF82000U) + +void rt_hw_interrupt_init(void) +{ + register int i; + + rt_uint32_t *vect_addr; + + /* the initialization is done in sys_startup.c */ + + /* init exceptions table */ + rt_memset(irq_desc, 0x00, sizeof(irq_desc)); + for(i=0; i < MAX_HANDLERS; i++) + { + irq_desc[i].handler = rt_hw_int_not_handle; + + vect_addr = (rt_uint32_t *)(vimRAM + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +void rt_hw_interrupt_mask(int vector) +{ + vimDisableInterrupt(vector); +} + +void rt_hw_interrupt_umask(int vector) +{ + vimEnableInterrupt(vector, SYS_IRQ); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param handler the interrupt service routine to be installed + * @param param the parameter for interrupt service routine + * @name unused. + * + * @return the old handler + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } + + return old_handler; +} + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/stack.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/stack.c new file mode 100644 index 0000000000..612cde3bfb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/stack.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-12-11 XuXinming first version + * 2013-05-24 Grissiom port to RM48x50 + */ +#include + +#include "armv7.h" +/** + * @addtogroup RM48x50 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + +#if defined(__TI_VFP_SUPPORT__) || (defined (__VFP_FP__) && !defined(__SOFTFP__)) +#ifndef RT_VFP_LAZY_STACKING + { + int i; + + for (i = 0; i < VFP_DATA_NR; i++) + { + *(--stk) = 0; + } + /* FPSCR TODO: do we need to set the values other than 0? */ + *(--stk) = 0; + /* FPEXC. Enable the FVP if no lazy stacking. */ + *(--stk) = 0x40000000; + } +#else + /* FPEXC. Disable the FVP by default. */ + *(--stk) = 0x00000000; +#endif +#endif + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/start_ccs.asm b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/start_ccs.asm new file mode 100644 index 0000000000..4334fa9b0f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/start_ccs.asm @@ -0,0 +1,552 @@ +;------------------------------------------------------------------------------- +; sys_core.asm +; +; (c) Texas Instruments 2009-2013, All rights reserved. +; + + .text + .arm + + .ref _c_int00 + + .def _reset + .asmfunc +_reset +;------------------------------------------------------------------------------- +; Initialize CPU Registers +; After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, lr + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + ; Switch to FIQ mode (M = 10001) + cps #17 + mov lr, r0 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + ; Switch to IRQ mode (M = 10010) + cps #18 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch to Abort mode (M = 10111) + cps #23 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch to Undefined Instruction Mode (M = 11011) + cps #27 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch to System Mode ( Shares User Mode registers ) (M = 11111) + cps #31 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + ; Switch back to Supervisor Mode (M = 10011) + cps #19 + + ; Turn on FPV coprocessor + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + + .if (RT_VFP_LAZY_STACKING) = 0 + fmrx r2, fpexc + orr r2, r2, #0x40000000 + fmxr fpexc, r2 + + fmdrr d0, r1, r1 + fmdrr d1, r1, r1 + fmdrr d2, r1, r1 + fmdrr d3, r1, r1 + fmdrr d4, r1, r1 + fmdrr d5, r1, r1 + fmdrr d6, r1, r1 + fmdrr d7, r1, r1 + fmdrr d8, r1, r1 + fmdrr d9, r1, r1 + fmdrr d10, r1, r1 + fmdrr d11, r1, r1 + fmdrr d12, r1, r1 + fmdrr d13, r1, r1 + fmdrr d14, r1, r1 + fmdrr d15, r1, r1 + .endif + +;------------------------------------------------------------------------------- +; Initialize Stack Pointers + cps #17 + ldr sp, fiqSp + cps #18 + ldr sp, irqSp + cps #23 + ldr sp, abortSp + cps #27 + ldr sp, undefSp + cps #31 + ldr sp, userSp + cps #19 + ldr sp, svcSp + + bl next1 +next1 + bl next2 +next2 + bl next3 +next3 + bl next4 +next4 + ldr lr, int00ad + bx lr + +int00ad .word _c_int00 +userSp .word 0x08000000+0x00001000 +svcSp .word 0x08000000+0x00001000+0x00000100 +fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100 +irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100 +abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100 +undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100 + + .endasmfunc + +;------------------------------------------------------------------------------- +; Enable RAM ECC Support + + .def _coreEnableRamEcc_ + .asmfunc + +_coreEnableRamEcc_ + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable RAM ECC Support + + .def _coreDisableRamEcc_ + .asmfunc + +_coreDisableRamEcc_ + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Enable Flash ECC Support + + .def _coreEnableFlashEcc_ + .asmfunc + +_coreEnableFlashEcc_ + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Disable Flash ECC Support + + .def _coreDisableFlashEcc_ + .asmfunc + +_coreDisableFlashEcc_ + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Get data fault status register + + .def _coreGetDataFault_ + .asmfunc + +_coreGetDataFault_ + + mrc p15, #0, r0, c5, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear data fault status register + + .def _coreClearDataFault_ + .asmfunc + +_coreClearDataFault_ + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get instruction fault status register + + .def _coreGetInstructionFault_ + .asmfunc + +_coreGetInstructionFault_ + + mrc p15, #0, r0, c5, c0, #1 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear instruction fault status register + + .def _coreClearInstructionFault_ + .asmfunc + +_coreClearInstructionFault_ + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get data fault address register + + .def _coreGetDataFaultAddress_ + .asmfunc + +_coreGetDataFaultAddress_ + + mrc p15, #0, r0, c6, c0, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear data fault address register + + .def _coreClearDataFaultAddress_ + .asmfunc + +_coreClearDataFaultAddress_ + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get instruction fault address register + + .def _coreGetInstructionFaultAddress_ + .asmfunc + +_coreGetInstructionFaultAddress_ + + mrc p15, #0, r0, c6, c0, #2 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear instruction fault address register + + .def _coreClearInstructionFaultAddress_ + .asmfunc + +_coreClearInstructionFaultAddress_ + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get auxiliary data fault status register + + .def _coreGetAuxiliaryDataFault_ + .asmfunc + +_coreGetAuxiliaryDataFault_ + + mrc p15, #0, r0, c5, c1, #0 + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Clear auxiliary data fault status register + + .def _coreClearAuxiliaryDataFault_ + .asmfunc + +_coreClearAuxiliaryDataFault_ + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + + +;------------------------------------------------------------------------------- +; Get auxiliary instruction fault status register + + .def _coreGetAuxiliaryInstructionFault_ + .asmfunc + +_coreGetAuxiliaryInstructionFault_ + + mrc p15, #0, r0, c5, c1, #1 + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Clear auxiliary instruction fault status register + + .def _coreClearAuxiliaryInstructionFault_ + .asmfunc + +_coreClearAuxiliaryInstructionFault_ + + stmfd sp!, {r0} + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + ldmfd sp!, {r0} + bx lr + + .endasmfunc + +;------------------------------------------------------------------------------- +; Clear ESM CCM errorss + + .def _esmCcmErrorsClear_ + .asmfunc + +_esmCcmErrorsClear_ + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG ; load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] ; clear the ESMSR1 register + + ldr r0, ESMSR2_REG ; load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] ; clear the ESMSR2 register + + ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] ; clear the ESMSSR2 register + + ldr r0, ESMKEY_REG ; load the ESMKEY register address + mov r2, #0x5 ; load R2 with 0x5 + str r2, [r0] ; clear the ESMKEY register + + ldr r0, VIM_INTREQ ; load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] ; clear the INTREQ register + ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] ; clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG .word 0xFFFFF518 +ESMSR2_REG .word 0xFFFFF51C +ESMSR3_REG .word 0xFFFFF520 +ESMKEY_REG .word 0xFFFFF538 +ESMSSR2_REG .word 0xFFFFF53C +CCMR4_STAT_REG .word 0xFFFFF600 +ERR_CLR_WRD .word 0xFFFFFFFF +CCMR4_ERR_CLR .word 0x00010000 +ESMSR1_ERR_CLR .word 0x80000000 +ESMSR2_ERR_CLR .word 0x00000004 +ESMSSR2_ERR_CLR .word 0x00000004 +VIM_INT_CLR .word 0x00000001 +VIM_INTREQ .word 0xFFFFFE20 + + .endasmfunc + +;------------------------------------------------------------------------------- +; Work Around for Errata CORTEX-R4#57: +; +; Errata Description: +; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +; Workaround: +; Disable out-of-order single-precision floating point +; multiply-accumulate instruction completion + + .def _errata_CORTEXR4_57_ + .asmfunc + +_errata_CORTEXR4_57_ + + push {r0} + mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register + pop {r0} + bx lr + .endasmfunc + +;------------------------------------------------------------------------------- +; Work Around for Errata CORTEX-R4#66: +; +; Errata Description: +; Register Corruption During A Load-Multiple Instruction At +; an Exception Vector +; Workaround: +; Disable out-of-order completion for divide instructions in +; Auxiliary Control register + + .def _errata_CORTEXR4_66_ + .asmfunc + +_errata_CORTEXR4_66_ + + push {r0} + mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register + orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion + ; for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register + pop {r0} + bx lr + .endasmfunc + + .def turnon_VFP + .asmfunc +turnon_VFP + ; Enable FPV + STMDB sp!, {r0} + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + LDMIA sp!, {r0} + subs pc, lr, #4 + .endasmfunc + +_push_svc_reg .macro + sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} ;/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr ;/* Save CPSR */ + str lr, [r0, #15*4] ;/* Push PC */ + str r6, [r0, #16*4] ;/* Push CPSR */ + cps #0x13 + str sp, [r0, #13*4] ;/* Save calling SP */ + str lr, [r0, #14*4] ;/* Save calling PC */ + .endm + + .ref rt_hw_trap_svc + .def vector_svc + .asmfunc +vector_svc: + _push_svc_reg + bl rt_hw_trap_svc + sub pc, pc, #-4 + .endasmfunc + + .ref rt_hw_trap_pabt + .def vector_pabort + .asmfunc +vector_pabort: + _push_svc_reg + bl rt_hw_trap_pabt + sub pc, pc, #-4 + .endasmfunc + + .ref rt_hw_trap_dabt + .def vector_dabort + .asmfunc +vector_dabort: + _push_svc_reg + bl rt_hw_trap_dabt + sub pc, pc, #-4 + .endasmfunc + + .ref rt_hw_trap_resv + .def vector_resv + .asmfunc +vector_resv: + _push_svc_reg + bl rt_hw_trap_resv + sub pc, pc, #-4 + .endasmfunc + +;------------------------------------------------------------------------------- +; C++ construct table pointers + + .def __TI_PINIT_Base, __TI_PINIT_Limit + .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit + +__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base +__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit + +;------------------------------------------------------------------------------- diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/start_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/start_gcc.S new file mode 100644 index 0000000000..ab77b98781 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/start_gcc.S @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +@------------------------------------------------------------------------------- +@ sys_core.asm +@ +@ (c) Texas Instruments 2009-2013, All rights reserved. +@ + +#include + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000000 +.equ ABT_Stack_Size, 0x00000000 +.equ FIQ_Stack_Size, 0x00001000 +.equ IRQ_Stack_Size, 0x00001000 + +.section .bss.noinit +/* stack */ +.globl stack_start +.globl stack_top + +stack_start: +.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) +.byte 0 +.endr +stack_top: + +.section .text, "ax" + .text + .arm + + .globl _c_int00 + +.globl _reset +_reset: +@------------------------------------------------------------------------------- +@ Initialize CPU Registers +@ After reset, the CPU is in the Supervisor mode (M = 10011) + cpsid if, #19 + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + @ Turn on FPV coprocessor + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + + fmrx r2, fpexc + orr r2, r2, #0x40000000 + fmxr fpexc, r2 +#endif + +@------------------------------------------------------------------------------- +@ Initialize Stack Pointers + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + + @ Switch back to SVC + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + ldr lr, =_c_int00 + bx lr + +.globl data_init +data_init: + /* copy .data to SRAM */ + ldr r1, =_sidata /* .data start in image */ + ldr r2, =_edata /* .data end in image */ + ldr r3, =_sdata /* sram data start */ +data_loop: + ldr r0, [r1, #0] + str r0, [r3] + + add r1, r1, #4 + add r3, r3, #4 + + cmp r3, r2 /* check if data to clear */ + blo data_loop /* loop until done */ + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r3, ip, lr} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r3, ip, lr} + b ctor_loop +ctor_end: + bx lr + +@------------------------------------------------------------------------------- +@ Enable RAM ECC Support + + .globl _coreEnableRamEcc_ +_coreEnableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Disable RAM ECC Support + + .globl _coreDisableRamEcc_ +_coreDisableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Enable Flash ECC Support + + .globl _coreEnableFlashEcc_ +_coreEnableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Disable Flash ECC Support + + .globl _coreDisableFlashEcc_ +_coreDisableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Get data fault status register + + .globl _coreGetDataFault_ +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear data fault status register + + .globl _coreClearDataFault_ +_coreClearDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get instruction fault status register + + .globl _coreGetInstructionFault_ +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear instruction fault status register + + .globl _coreClearInstructionFault_ +_coreClearInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get data fault address register + + .globl _coreGetDataFaultAddress_ +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear data fault address register + + .globl _coreClearDataFaultAddress_ +_coreClearDataFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get instruction fault address register + + .globl _coreGetInstructionFaultAddress_ +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear instruction fault address register + + .globl _coreClearInstructionFaultAddress_ +_coreClearInstructionFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get auxiliary data fault status register + + .globl _coreGetAuxiliaryDataFault_ +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear auxiliary data fault status register + + .globl _coreClearAuxiliaryDataFault_ +_coreClearAuxiliaryDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get auxiliary instruction fault status register + + .globl _coreGetAuxiliaryInstructionFault_ +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + + +@------------------------------------------------------------------------------- +@ Clear auxiliary instruction fault status register + + .globl _coreClearAuxiliaryInstructionFault_ +_coreClearAuxiliaryInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Clear ESM CCM errorss + + .globl _esmCcmErrorsClear_ +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + + +@------------------------------------------------------------------------------- +@ Work Around for Errata CORTEX-R4#57: +@ +@ Errata Description: +@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +@ Workaround: +@ Disable out-of-order single-precision floating point +@ multiply-accumulate instruction completion + + .globl _errata_CORTEXR4_57_ +_errata_CORTEXR4_57_: + + push {r0} + mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register + pop {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Work Around for Errata CORTEX-R4#66: +@ +@ Errata Description: +@ Register Corruption During A Load-Multiple Instruction At +@ an Exception Vector +@ Workaround: +@ Disable out-of-order completion for divide instructions in +@ Auxiliary Control register + + .globl _errata_CORTEXR4_66_ +_errata_CORTEXR4_66_: + + push {r0} + mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register + orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion + @ for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register + pop {r0} + bx lr + + .globl turnon_VFP +turnon_VFP: + @ Enable FPV + STMDB sp!, {r0} + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + LDMIA sp!, {r0} + subs pc, lr, #4 + + .macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ + .endm + + .globl vector_svc +vector_svc: + push_svc_reg + bl rt_hw_trap_svc + b . + + .globl vector_pabort +vector_pabort: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .globl vector_dabort +vector_dabort: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/trap.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/trap.c new file mode 100644 index 0000000000..d50ad06538 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/trap.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-12-11 XuXinming first version + * 2013-05-24 Grissiom port to RM48x50 + */ + +#include +#include + +#include + +#include "armv7.h" + +/** + * @addtogroup RM48x50 + */ +/*@{*/ + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register (struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_udef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction\n"); + rt_hw_show_register(regs); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Data Abort "); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Reserved trap\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +extern rt_isr_handler_t isr_table[]; +void rt_hw_trap_irq(void) +{ + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; + + irq = (struct rt_irq_desc*) vimREG->IRQVECREG; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + + /* invoke isr */ + irq->handler(irqno, irq->param); +} + +void rt_hw_trap_fiq(void) +{ + rt_kprintf("fast interrupt request\n"); +} + +/*@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/vector_ccs.asm b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/vector_ccs.asm new file mode 100644 index 0000000000..df2bcec925 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/vector_ccs.asm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------- +; sys_intvecs.asm +; +; (c) Texas Instruments 2009-2013, All rights reserved. +; + + .sect ".intvecs" + .arm + +;------------------------------------------------------------------------------- +; import reference for interrupt routines + + .ref _reset + .ref turnon_VFP + .ref vector_svc + .ref vector_pabort + .ref vector_dabort + .ref vector_resv + .ref IRQ_Handler + +;------------------------------------------------------------------------------- +; interrupt vectors + .def resetEntry +resetEntry + b _reset + b turnon_VFP + b vector_svc + b vector_pabort + b vector_dabort + b vector_resv + b IRQ_Handler + ldr pc,[pc,#-0x1b0] + +;------------------------------------------------------------------------------- diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/vector_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/vector_gcc.S new file mode 100644 index 0000000000..6cb2e9fab6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/arm/cortex-r4/vector_gcc.S @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +@------------------------------------------------------------------------------- +@ sys_intvecs.asm +@ +@ (c) Texas Instruments 2009-2013, All rights reserved. +@ + +.section .vectors, "ax" +.code 32 + +@------------------------------------------------------------------------------- +@ import reference for interrupt routines + + .globl _reset + .globl turnon_VFP + .globl vector_svc + .globl vector_pabort + .globl vector_dabort + .globl vector_resv + .globl IRQ_Handler + + +.globl system_vectors +system_vectors: + b _reset + b turnon_VFP + b vector_svc + b vector_pabort + b vector_dabort + b vector_resv + b IRQ_Handler + ldr pc,[pc,#-0x1b0] diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/bumblebee/interrupt_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/bumblebee/interrupt_gcc.S new file mode 100644 index 0000000000..5a86e7d748 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/bumblebee/interrupt_gcc.S @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "cpuport.h" + + .section .text.entry + .align 6 /* In ECLIC mode, the trap entry must be 64bytes aligned */ + .global irq_entry +irq_entry: + + /* save all from thread context */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + move s0, sp + + /* switch to interrupt stack */ + la sp, _sp + + /* interrupt handle */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, sp + csrrw ra, 0x07ED, ra + call rt_interrupt_leave + + /* switch to from thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + /* clear switch interrupt flag */ + sw zero, 0(s0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + +spurious_interrupt: + LOAD x1, 1 * REGBYTES(sp) + + /* Remain in M-mode after mret */ + li t0, 0x00001800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/context_gcc.S new file mode 100644 index 0000000000..f28b15319b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/context_gcc.S @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting implementation + * 2018/12/27 Jesven Add SMP support + */ + +#include "cpuport.h" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +/* + * rt_base_t rt_hw_interrupt_disable(void); + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + csrrci a0, mstatus, 8 + ret + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + csrw mstatus, a0 + ret + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_to(rt_ubase_t to); + * #endif + * a0 --> to + * a1 --> to_thread + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LOAD sp, (a0) + +#ifdef RT_USING_SMP + mv a0, a1 + jal rt_cpus_lock_status_restore +#endif + LOAD a0, 2 * REGBYTES(sp) + csrw mstatus, a0 + j rt_hw_context_switch_exit + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * #endif + * + * a0 --> from + * a1 --> to + * a2 --> to_thread + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + /* saved from thread context + * x1/ra -> sp(0) + * x1/ra -> sp(1) + * mstatus.mie -> sp(2) + * x(i) -> sp(i-4) + */ + addi sp, sp, -32 * REGBYTES + STORE sp, (a0) + + STORE x1, 0 * REGBYTES(sp) + STORE x1, 1 * REGBYTES(sp) + + csrr a0, mstatus + andi a0, a0, 8 + beqz a0, save_mpie + li a0, 0x80 +save_mpie: + STORE a0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* restore to thread context + * sp(0) -> epc; + * sp(1) -> ra; + * sp(i) -> x(i+2) + */ + LOAD sp, (a1) + +#ifdef RT_USING_SMP + mv a0, a2 + jal rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + + j rt_hw_context_switch_exit + +#ifdef RT_USING_SMP +/* + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * + * a0 --> context + * a1 --> from + * a2 --> to + * a3 --> to_thread + */ + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + + STORE a0, 0(a1) + + LOAD sp, 0(a2) + move a0, a3 + call rt_cpus_lock_status_restore + + j rt_hw_context_switch_exit + +#endif + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mv a0, sp + + csrr t0, mhartid + /* switch interrupt stack of current cpu */ + la sp, __stack_start__ + addi t1, t0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + call rt_signal_check + mv sp, a0 +#endif +#endif + /* resw ra to mepc */ + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + + LOAD x1, 1 * REGBYTES(sp) + + li t0, 0x00001800 + csrs mstatus, t0 + LOAD a0, 2 * REGBYTES(sp) + csrs mstatus, a0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/cpuport.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/cpuport.c new file mode 100644 index 0000000000..a44dc40f79 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/cpuport.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#include +#include + +#include "cpuport.h" + +#ifndef RT_USING_SMP +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif + +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t mstatus; /* - machine status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - s7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + /* force to machine mode(MPP=11) and set MPIE to 1 */ + frame->mstatus = 0x00007880; + + return stk; +} + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + * #endif + */ +#ifndef RT_USING_SMP +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} +#endif /* end of RT_USING_SMP */ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/cpuport.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/cpuport.h new file mode 100644 index 0000000000..95268732cb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/cpuport.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +/* bytes of register width */ +#ifdef ARCH_CPU_64BIT +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#else +#define STORE sw +#define LOAD lw +#define REGBYTES 4 +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/riscv-ops.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/riscv-ops.h new file mode 100644 index 0000000000..0b321c6de4 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/riscv-ops.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef RISCV_OPS_H__ +#define RISCV_OPS_H__ + +#if defined(__GNUC__) && !defined(__ASSEMBLER__) + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) +#endif /* end of __GNUC__ */ + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/riscv-plic.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/riscv-plic.h new file mode 100644 index 0000000000..1da14b2e45 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/common/riscv-plic.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ + +#ifndef RISCV_PLIC_H__ +#define RISCV_PLIC_H__ + +#ifndef PLIC_BASE_ADDR +#define PLIC_BASE_ADDR 0x0 +#endif + +/* Priority Register - 32 bits per source */ +#define PLIC_PRIORITY_OFFSET (0x00000000UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per soirce */ +#define PLIC_PENDING_OFFSET (0x00001000UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define PLIC_ENABLE_OFFSET (0x00002000UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define PLIC_CLAIM_OFFSET (0x00200004UL) +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if defined(__GNUC__) && !defined(__ASSEMBLER__) +__attribute__((always_inline)) static inline void __plic_set_feature(unsigned int feature) +{ + volatile unsigned int *feature_ptr = (volatile unsigned int *)PLIC_BASE_ADDR; + *feature_ptr = feature; +} + +__attribute__((always_inline)) static inline void __plic_set_threshold(unsigned int threshold) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *threshold_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +__attribute__((always_inline)) static inline void __plic_set_priority(unsigned int source, unsigned int priority) +{ + volatile unsigned int *priority_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +__attribute__((always_inline)) static inline void __plic_set_pending(unsigned int source) +{ + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_PENDING_OFFSET + + ((source >> 5) << 2)); + *current_ptr = (1 << (source & 0x1F)); +} + +__attribute__((always_inline)) static inline void __plic_irq_enable(unsigned int source) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + ((source >> 5) << 2)); + unsigned int current = *current_ptr; + current = current | (1 << (source & 0x1F)); + *current_ptr = current; +} + +__attribute__((always_inline)) static inline void __plic_irq_disable(unsigned int source) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + ((source >> 5) << 2)); + unsigned int current = *current_ptr; + current = current & ~((1 << (source & 0x1F))); + *current_ptr = current; +} + +__attribute__((always_inline)) static inline unsigned int __plic_irq_claim(void) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +__attribute__((always_inline)) static inline void __plic_irq_complete(unsigned int source) +{ + unsigned int hart_id = read_csr(mhartid); + volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; +} +#endif /* end of __GNUC__ */ + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/SConscript b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/SConscript new file mode 100644 index 0000000000..4e4bc0c3d9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/SConscript @@ -0,0 +1,13 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_gcc.S') + +group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/context_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/context_gcc.S new file mode 100644 index 0000000000..7aaa8db432 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/context_gcc.S @@ -0,0 +1,227 @@ +;/* +; * File : context_gcc.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2018, RT-Thread Development Team +; * +; * This program is free software; you can redistribute it and/or modify +; * it under the terms of the GNU General Public License as published by +; * the Free Software Foundation; either version 2 of the License, or +; * (at your option) any later version. +; * +; * This program is distributed in the hope that it will be useful, +; * but WITHOUT ANY WARRANTY; without even the implied warranty of +; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; * GNU General Public License for more details. +; * +; * You should have received a copy of the GNU General Public License along +; * with this program; if not, write to the Free Software Foundation, Inc., +; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * +; * Change Logs: +; * Date Author Notes +; * 2017-07-16 zhangjun for hifive1 +; * 2018-05-29 tanek optimize rt_hw_interrupt_* +; * 2018-05-29 tanek add mie register to context +; */ + +/* + * rt_base_t rt_hw_interrupt_disable(void); + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + csrrci a0, mstatus, 8 + ret + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + csrw mstatus, a0 + ret + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + + /* saved from thread context + * x1/ra -> sp(0) + * x1/ra -> sp(1) + * mstatus.mie -> sp(2) + * x(i) -> sp(i-4) + */ + addi sp, sp, -32 * 4 + sw sp, (a0) + + sw x1, 0 * 4(sp) + sw x1, 1 * 4(sp) + + csrr a0, mstatus + andi a0, a0, 8 + beqz a0, save_mpie + li a0, 0x80 +save_mpie: + sw a0, 2 * 4(sp) + + sw x4, 4 * 4(sp) + sw x5, 5 * 4(sp) + sw x6, 6 * 4(sp) + sw x7, 7 * 4(sp) + sw x8, 8 * 4(sp) + sw x9, 9 * 4(sp) + sw x10, 10 * 4(sp) + sw x11, 11 * 4(sp) + sw x12, 12 * 4(sp) + sw x13, 13 * 4(sp) + sw x14, 14 * 4(sp) + sw x15, 15 * 4(sp) + sw x16, 16 * 4(sp) + sw x17, 17 * 4(sp) + sw x18, 18 * 4(sp) + sw x19, 19 * 4(sp) + sw x20, 20 * 4(sp) + sw x21, 21 * 4(sp) + sw x22, 22 * 4(sp) + sw x23, 23 * 4(sp) + sw x24, 24 * 4(sp) + sw x25, 25 * 4(sp) + sw x26, 26 * 4(sp) + sw x27, 27 * 4(sp) + sw x28, 28 * 4(sp) + sw x29, 29 * 4(sp) + sw x30, 30 * 4(sp) + sw x31, 31 * 4(sp) + + /* restore to thread context + * sp(0) -> epc; + * sp(1) -> ra; + * sp(i) -> x(i+2) + */ + lw sp, (a1) + + /* resw ra to mepc */ + lw a1, 0 * 4(sp) + csrw mepc, a1 + lw x1, 1 * 4(sp) + + /* force to machin mode(MPP=11) */ + li a1, 0x00001800; + csrs mstatus, a1 + lw a1, 2 * 4(sp) + csrs mstatus, a1 + + lw x4, 4 * 4(sp) + lw x5, 5 * 4(sp) + lw x6, 6 * 4(sp) + lw x7, 7 * 4(sp) + lw x8, 8 * 4(sp) + lw x9, 9 * 4(sp) + lw x10, 10 * 4(sp) + lw x11, 11 * 4(sp) + lw x12, 12 * 4(sp) + lw x13, 13 * 4(sp) + lw x14, 14 * 4(sp) + lw x15, 15 * 4(sp) + lw x16, 16 * 4(sp) + lw x17, 17 * 4(sp) + lw x18, 18 * 4(sp) + lw x19, 19 * 4(sp) + lw x20, 20 * 4(sp) + lw x21, 21 * 4(sp) + lw x22, 22 * 4(sp) + lw x23, 23 * 4(sp) + lw x24, 24 * 4(sp) + lw x25, 25 * 4(sp) + lw x26, 26 * 4(sp) + lw x27, 27 * 4(sp) + lw x28, 28 * 4(sp) + lw x29, 29 * 4(sp) + lw x30, 30 * 4(sp) + lw x31, 31 * 4(sp) + + addi sp, sp, 32 * 4 + mret + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, (a0) + + /* load epc from stack */ + lw a0, 0 * 4(sp) + csrw mepc, a0 + lw x1, 1 * 4(sp) + /* load mstatus from stack */ + lw a0, 2 * 4(sp) + csrw mstatus, a0 + lw x4, 4 * 4(sp) + lw x5, 5 * 4(sp) + lw x6, 6 * 4(sp) + lw x7, 7 * 4(sp) + lw x8, 8 * 4(sp) + lw x9, 9 * 4(sp) + lw x10, 10 * 4(sp) + lw x11, 11 * 4(sp) + lw x12, 12 * 4(sp) + lw x13, 13 * 4(sp) + lw x14, 14 * 4(sp) + lw x15, 15 * 4(sp) + lw x16, 16 * 4(sp) + lw x17, 17 * 4(sp) + lw x18, 18 * 4(sp) + lw x19, 19 * 4(sp) + lw x20, 20 * 4(sp) + lw x21, 21 * 4(sp) + lw x22, 22 * 4(sp) + lw x23, 23 * 4(sp) + lw x24, 24 * 4(sp) + lw x25, 25 * 4(sp) + lw x26, 26 * 4(sp) + lw x27, 27 * 4(sp) + lw x28, 28 * 4(sp) + lw x29, 29 * 4(sp) + lw x30, 30 * 4(sp) + lw x31, 31 * 4(sp) + + addi sp, sp, 32 * 4 + mret + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + addi sp, sp, -16 + sw s0, 12(sp) + sw a0, 8(sp) + sw a5, 4(sp) + + la a0, rt_thread_switch_interrupt_flag + lw a5, (a0) + bnez a5, _reswitch + li a5, 1 + sw a5, (a0) + + la a5, rt_interrupt_from_thread + lw a0, 8(sp) + sw a0, (a5) + +_reswitch: + la a5, rt_interrupt_to_thread + sw a1, (a5) + + lw a5, 4(sp) + lw a0, 8(sp) + lw s0, 12(sp) + addi sp, sp, 16 + ret diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/entry_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/entry_gcc.S new file mode 100644 index 0000000000..83631e67ee --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/entry_gcc.S @@ -0,0 +1,145 @@ +/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2018, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-05-29 tanek first implementation + */ + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + + // save all from thread context + addi sp, sp, -32 * 4 + + sw x1, 1 * 4(sp) + li t0, 0x80 + sw t0, 2 * 4(sp) + + sw x4, 4 * 4(sp) + sw x5, 5 * 4(sp) + sw x6, 6 * 4(sp) + sw x7, 7 * 4(sp) + sw x8, 8 * 4(sp) + sw x9, 9 * 4(sp) + sw x10, 10 * 4(sp) + sw x11, 11 * 4(sp) + sw x12, 12 * 4(sp) + sw x13, 13 * 4(sp) + sw x14, 14 * 4(sp) + sw x15, 15 * 4(sp) + sw x16, 16 * 4(sp) + sw x17, 17 * 4(sp) + sw x18, 18 * 4(sp) + sw x19, 19 * 4(sp) + sw x20, 20 * 4(sp) + sw x21, 21 * 4(sp) + sw x22, 22 * 4(sp) + sw x23, 23 * 4(sp) + sw x24, 24 * 4(sp) + sw x25, 25 * 4(sp) + sw x26, 26 * 4(sp) + sw x27, 27 * 4(sp) + sw x28, 28 * 4(sp) + sw x29, 29 * 4(sp) + sw x30, 30 * 4(sp) + sw x31, 31 * 4(sp) + + // switch to interrupt stack + move s0, sp + la sp, _sp + + // interrupt handle + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + call rt_interrupt_leave + + // switch to from thread stack + move sp, s0 + + // need to switch new thread + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + sw zero, 0(s0) + + csrr a0, mepc + sw a0, 0 * 4(sp) + + la s0, rt_interrupt_from_thread + lw s1, 0(s0) + sw sp, 0(s1) + + la s0, rt_interrupt_to_thread + lw s1, 0(s0) + lw sp, 0(s1) + + lw a0, 0 * 4(sp) + csrw mepc, a0 + +spurious_interrupt: + lw x1, 1 * 4(sp) + + // Remain in M-mode after mret + li t0, 0x00001800 + csrs mstatus, t0 + lw t0, 2 * 4(sp) + csrs mstatus, t0 + + lw x4, 4 * 4(sp) + lw x5, 5 * 4(sp) + lw x6, 6 * 4(sp) + lw x7, 7 * 4(sp) + lw x8, 8 * 4(sp) + lw x9, 9 * 4(sp) + lw x10, 10 * 4(sp) + lw x11, 11 * 4(sp) + lw x12, 12 * 4(sp) + lw x13, 13 * 4(sp) + lw x14, 14 * 4(sp) + lw x15, 15 * 4(sp) + lw x16, 16 * 4(sp) + lw x17, 17 * 4(sp) + lw x18, 18 * 4(sp) + lw x19, 19 * 4(sp) + lw x20, 20 * 4(sp) + lw x21, 21 * 4(sp) + lw x22, 22 * 4(sp) + lw x23, 23 * 4(sp) + lw x24, 24 * 4(sp) + lw x25, 25 * 4(sp) + lw x26, 26 * 4(sp) + lw x27, 27 * 4(sp) + lw x28, 28 * 4(sp) + lw x29, 29 * 4(sp) + lw x30, 30 * 4(sp) + lw x31, 31 * 4(sp) + + addi sp, sp, 32 * 4 + mret + +.weak handle_trap +handle_trap: +1: + j 1b diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/stack.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/stack.c new file mode 100644 index 0000000000..a68c646e39 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/e310/stack.c @@ -0,0 +1,104 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-07-31 tanek first implementation + */ + +#include + +/* flag in interrupt handling */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +struct stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t mstatus; /* - machine status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - s7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->ra = (rt_ubase_t)texit; + stack_frame->a0 = (rt_ubase_t)parameter; + stack_frame->epc = (rt_ubase_t)tentry; + + // force to machine mode(MPP=11) and set MPIE to 1 + stack_frame->mstatus = 0x00001880; + + return stk; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/cpuport_smp.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/cpuport_smp.c new file mode 100644 index 0000000000..a31314a13f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/cpuport_smp.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/12/23 Bernard The first version + * 2018/12/27 Jesven Add secondary cpu boot + */ + +#include +#include +#include + +#include "board.h" +#include +#include +#include + +#ifdef RT_USING_SMP + +int rt_hw_cpu_id(void) +{ + return read_csr(mhartid); +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + spinlock_lock((spinlock_t *)lock); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + spinlock_unlock((spinlock_t *)lock); +} + +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + int idx; + + for (idx = 0; idx < RT_CPUS_NR; idx ++) + { + if (cpu_mask & (1 << idx)) + { + clint_ipi_send(idx); + } + } +} + +extern rt_base_t secondary_boot_flag; +void rt_hw_secondary_cpu_up(void) +{ + mb(); + secondary_boot_flag = 0xa55a; +} + +extern void rt_hw_scondary_interrupt_init(void); +extern int rt_hw_tick_init(void); +extern int rt_hw_clint_ipi_enable(void); + +void secondary_cpu_c_start(void) +{ + rt_hw_spin_lock(&_cpus_lock); + + /* initialize interrupt controller */ + rt_hw_scondary_interrupt_init(); + + rt_hw_tick_init(); + + rt_hw_clint_ipi_enable(); + + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + asm volatile ("wfi"); +} +#endif /*RT_USING_SMP*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/interrupt.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/interrupt.c new file mode 100644 index 0000000000..b582599daf --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/interrupt.c @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + * 2018/12/27 Jesven Change irq enable/disable to cpu0 + */ + +#include + +#include "tick.h" + +#include +#include +#include + +#define CPU_NUM 2 +#define MAX_HANDLERS IRQN_MAX + +static struct rt_irq_desc irq_desc[MAX_HANDLERS]; + +static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector); + return RT_NULL; +} + +int rt_hw_clint_ipi_enable(void) +{ + /* Set the Machine-Software bit in MIE */ + set_csr(mie, MIP_MSIP); + return 0; +} + +int rt_hw_clint_ipi_disable(void) +{ + /* Clear the Machine-Software bit in MIE */ + clear_csr(mie, MIP_MSIP); + return 0; +} + +int rt_hw_plic_irq_enable(plic_irq_t irq_number) +{ + unsigned long core_id = 0; + + /* Check parameters */ + if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number) + return -1; + /* Get current enable bit array by IRQ number */ + uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32]; + /* Set enable bit in enable bit array */ + current |= (uint32_t)1 << (irq_number % 32); + /* Write back the enable bit array */ + plic->target_enables.target[core_id].enable[irq_number / 32] = current; + return 0; +} + +int rt_hw_plic_irq_disable(plic_irq_t irq_number) +{ + unsigned long core_id = 0; + + /* Check parameters */ + if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number) + return -1; + /* Get current enable bit array by IRQ number */ + uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32]; + /* Clear enable bit in enable bit array */ + current &= ~((uint32_t)1 << (irq_number % 32)); + /* Write back the enable bit array */ + plic->target_enables.target[core_id].enable[irq_number / 32] = current; + return 0; +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + int idx; + int cpuid; + + cpuid = current_coreid(); + + /* Disable all interrupts for the current core. */ + for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++) + plic->target_enables.target[cpuid].enable[idx] = 0; + + /* Set priorities to zero. */ + for (idx = 0; idx < PLIC_NUM_SOURCES; idx++) + plic->source_priorities.priority[idx] = 0; + + /* Set the threshold to zero. */ + plic->targets.target[cpuid].priority_threshold = 0; + + /* init exceptions table */ + for (idx = 0; idx < MAX_HANDLERS; idx++) + { + rt_hw_interrupt_mask(idx); + irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + irq_desc[idx].param = RT_NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); + irq_desc[idx].counter = 0; +#endif + } + + /* Enable machine external interrupts. */ + set_csr(mie, MIP_MEIP); +} + +void rt_hw_scondary_interrupt_init(void) +{ + int idx; + int cpuid; + + cpuid = current_coreid(); + + /* Disable all interrupts for the current core. */ + for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++) + plic->target_enables.target[cpuid].enable[idx] = 0; + + /* Set the threshold to zero. */ + plic->targets.target[cpuid].priority_threshold = 0; + + /* Enable machine external interrupts. */ + set_csr(mie, MIP_MEIP); +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + rt_hw_plic_irq_disable(vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + plic_set_priority(vector, 1); + rt_hw_plic_irq_enable(vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if(vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector].counter = 0; +#endif + } + } + + return old_handler; +} + +RT_WEAK +void plic_irq_handle(plic_irq_t irq) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq); + return ; +} + +uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc) +{ + /* + * After the highest-priority pending interrupt is claimed by a target + * and the corresponding IP bit is cleared, other lower-priority + * pending interrupts might then become visible to the target, and so + * the PLIC EIP bit might not be cleared after a claim. The interrupt + * handler can check the local meip/heip/seip/ueip bits before exiting + * the handler, to allow more efficient service of other interrupts + * without first restoring the interrupted context and taking another + * interrupt trap. + */ + if (read_csr(mip) & MIP_MEIP) + { + /* Get current core id */ + uint64_t core_id = current_coreid(); + /* Get primitive interrupt enable flag */ + uint64_t ie_flag = read_csr(mie); + /* Get current IRQ num */ + uint32_t int_num = plic->targets.target[core_id].claim_complete; + /* Get primitive IRQ threshold */ + uint32_t int_threshold = plic->targets.target[core_id].priority_threshold; + /* Set new IRQ threshold = current IRQ threshold */ + plic->targets.target[core_id].priority_threshold = plic->source_priorities.priority[int_num]; + + /* Disable software interrupt and timer interrupt */ + clear_csr(mie, MIP_MTIP | MIP_MSIP); + + if (irq_desc[int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle) + { + /* default handler, route to kendryte bsp plic driver */ + plic_irq_handle(int_num); + } + else if (irq_desc[int_num].handler) + { + irq_desc[int_num].handler(int_num, irq_desc[int_num].param); + } + + /* Perform IRQ complete */ + plic->targets.target[core_id].claim_complete = int_num; + /* Set MPIE and MPP flag used to MRET instructions restore MIE flag */ + set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP); + /* Restore primitive interrupt enable flag */ + write_csr(mie, ie_flag); + /* Restore primitive IRQ threshold */ + plic->targets.target[core_id].priority_threshold = int_threshold; + } + + return epc; +} +struct exception_stack_frame +{ + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; + uint64_t x31; +}; + +void print_stack_frame(uintptr_t * sp) +{ + struct exception_stack_frame * esf = (struct exception_stack_frame *)(sp+1); + + rt_kprintf("\n=================================================================\n"); + rt_kprintf("x1 (ra : Return address ) ==> 0x%08x%08x\n", esf->x1 >> 32 , esf->x1 & UINT32_MAX); + rt_kprintf("x2 (sp : Stack pointer ) ==> 0x%08x%08x\n", esf->x2 >> 32 , esf->x2 & UINT32_MAX); + rt_kprintf("x3 (gp : Global pointer ) ==> 0x%08x%08x\n", esf->x3 >> 32 , esf->x3 & UINT32_MAX); + rt_kprintf("x4 (tp : Thread pointer ) ==> 0x%08x%08x\n", esf->x4 >> 32 , esf->x4 & UINT32_MAX); + rt_kprintf("x5 (t0 : Temporary ) ==> 0x%08x%08x\n", esf->x5 >> 32 , esf->x5 & UINT32_MAX); + rt_kprintf("x6 (t1 : Temporary ) ==> 0x%08x%08x\n", esf->x6 >> 32 , esf->x6 & UINT32_MAX); + rt_kprintf("x7 (t2 : Temporary ) ==> 0x%08x%08x\n", esf->x7 >> 32 , esf->x7 & UINT32_MAX); + rt_kprintf("x8 (s0/fp: Save register,frame pointer ) ==> 0x%08x%08x\n", esf->x8 >> 32 , esf->x8 & UINT32_MAX); + rt_kprintf("x9 (s1 : Save register ) ==> 0x%08x%08x\n", esf->x9 >> 32 , esf->x9 & UINT32_MAX); + rt_kprintf("x10(a0 : Function argument,return value) ==> 0x%08x%08x\n", esf->x10 >> 32 , esf->x10 & UINT32_MAX); + rt_kprintf("x11(a1 : Function argument,return value) ==> 0x%08x%08x\n", esf->x11 >> 32 , esf->x11 & UINT32_MAX); + rt_kprintf("x12(a2 : Function argument ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MAX); + rt_kprintf("x13(a3 : Function argument ) ==> 0x%08x%08x\n", esf->x13 >> 32 , esf->x13 & UINT32_MAX); + rt_kprintf("x14(a4 : Function argument ) ==> 0x%08x%08x\n", esf->x14 >> 32 , esf->x14 & UINT32_MAX); + rt_kprintf("x15(a5 : Function argument ) ==> 0x%08x%08x\n", esf->x15 >> 32 , esf->x15 & UINT32_MAX); + rt_kprintf("x16(a6 : Function argument ) ==> 0x%08x%08x\n", esf->x16 >> 32 , esf->x16 & UINT32_MAX); + rt_kprintf("x17(a7 : Function argument ) ==> 0x%08x%08x\n", esf->x17 >> 32 , esf->x17 & UINT32_MAX); + rt_kprintf("x18(s2 : Save register ) ==> 0x%08x%08x\n", esf->x18 >> 32 , esf->x18 & UINT32_MAX); + rt_kprintf("x19(s3 : Save register ) ==> 0x%08x%08x\n", esf->x19 >> 32 , esf->x19 & UINT32_MAX); + rt_kprintf("x20(s4 : Save register ) ==> 0x%08x%08x\n", esf->x20 >> 32 , esf->x20 & UINT32_MAX); + rt_kprintf("x21(s5 : Save register ) ==> 0x%08x%08x\n", esf->x21 >> 32 , esf->x21 & UINT32_MAX); + rt_kprintf("x22(s6 : Save register ) ==> 0x%08x%08x\n", esf->x22 >> 32 , esf->x22 & UINT32_MAX); + rt_kprintf("x23(s7 : Save register ) ==> 0x%08x%08x\n", esf->x23 >> 32 , esf->x23 & UINT32_MAX); + rt_kprintf("x24(s8 : Save register ) ==> 0x%08x%08x\n", esf->x24 >> 32 , esf->x24 & UINT32_MAX); + rt_kprintf("x25(s9 : Save register ) ==> 0x%08x%08x\n", esf->x25 >> 32 , esf->x25 & UINT32_MAX); + rt_kprintf("x26(s10 : Save register ) ==> 0x%08x%08x\n", esf->x26 >> 32 , esf->x26 & UINT32_MAX); + rt_kprintf("x27(s11 : Save register ) ==> 0x%08x%08x\n", esf->x27 >> 32 , esf->x27 & UINT32_MAX); + rt_kprintf("x28(t3 : Temporary ) ==> 0x%08x%08x\n", esf->x28 >> 32 , esf->x28 & UINT32_MAX); + rt_kprintf("x29(t4 : Temporary ) ==> 0x%08x%08x\n", esf->x29 >> 32 , esf->x29 & UINT32_MAX); + rt_kprintf("x30(t5 : Temporary ) ==> 0x%08x%08x\n", esf->x30 >> 32 , esf->x30 & UINT32_MAX); + rt_kprintf("x31(t6 : Temporary ) ==> 0x%08x%08x\n", esf->x31 >> 32 , esf->x31 & UINT32_MAX); + rt_kprintf("=================================================================\n"); +} + + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc, uintptr_t * sp) +{ + int cause = mcause & CAUSE_MACHINE_IRQ_REASON_MASK; + + if (mcause & (1UL << 63)) + { + switch (cause) + { + case IRQ_M_SOFT: + { + uint64_t core_id = current_coreid(); + + clint_ipi_clear(core_id); + rt_schedule(); + } + break; + case IRQ_M_EXT: + handle_irq_m_ext(mcause, epc); + break; + case IRQ_M_TIMER: + tick_isr(); + break; + } + } + else + { + rt_thread_t tid; + extern long list_thread(); + + rt_hw_interrupt_disable(); + + tid = rt_thread_self(); + rt_kprintf("\nException:\n"); + switch (cause) + { + case CAUSE_MISALIGNED_FETCH: + rt_kprintf("Instruction address misaligned"); + break; + case CAUSE_FAULT_FETCH: + rt_kprintf("Instruction access fault"); + break; + case CAUSE_ILLEGAL_INSTRUCTION: + rt_kprintf("Illegal instruction"); + break; + case CAUSE_BREAKPOINT: + rt_kprintf("Breakpoint"); + break; + case CAUSE_MISALIGNED_LOAD: + rt_kprintf("Load address misaligned"); + break; + case CAUSE_FAULT_LOAD: + rt_kprintf("Load access fault"); + break; + case CAUSE_MISALIGNED_STORE: + rt_kprintf("Store address misaligned"); + break; + case CAUSE_FAULT_STORE: + rt_kprintf("Store access fault"); + break; + case CAUSE_USER_ECALL: + rt_kprintf("Environment call from U-mode"); + break; + case CAUSE_SUPERVISOR_ECALL: + rt_kprintf("Environment call from S-mode"); + break; + case CAUSE_HYPERVISOR_ECALL: + rt_kprintf("Environment call from H-mode"); + break; + case CAUSE_MACHINE_ECALL: + rt_kprintf("Environment call from M-mode"); + break; + default: + rt_kprintf("Uknown exception : %08lX", cause); + break; + } + rt_kprintf("\n"); + print_stack_frame(sp); + rt_kprintf("exception pc => 0x%08x\n", epc); + rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name); +#ifdef RT_USING_FINSH + list_thread(); +#endif + while(1); + } + + return epc; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/interrupt_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/interrupt_gcc.S new file mode 100644 index 0000000000..0393ea51f8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/interrupt_gcc.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + * 2018/12/27 Jesven Add SMP schedule + */ + +#include "cpuport.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + + /* save thread context to thread stack */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + + csrr x1, mstatus + STORE x1, 2 * REGBYTES(sp) + + csrr x1, mepc + STORE x1, 0 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* switch to interrupt stack */ + move s0, sp + + /* get cpu id */ + csrr t0, mhartid + + /* switch interrupt stack of current cpu */ + la sp, __stack_start__ + addi t1, t0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + /* handle interrupt */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, s0 + call handle_trap + call rt_interrupt_leave + +#ifdef RT_USING_SMP + /* s0 --> sp */ + mv sp, s0 + mv a0, s0 + call rt_scheduler_do_irq_switch + j rt_hw_context_switch_exit + +#else + + /* switch to from_thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + sw zero, 0(s0) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + +#endif + +spurious_interrupt: + j rt_hw_context_switch_exit diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/startup_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/startup_gcc.S new file mode 100644 index 0000000000..f5c0d8fa94 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/startup_gcc.S @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + * 2018/12/27 Jesven Add SMP support + */ + +#define MSTATUS_FS 0x00006000U /* initial state of FPU */ +#include + + .global _start + .section ".start", "ax" +_start: + j 1f + .word 0xdeadbeef + .align 3 + .global g_wake_up + g_wake_up: + .dword 1 + .dword 0 +1: + csrw mideleg, 0 + csrw medeleg, 0 + csrw mie, 0 + csrw mip, 0 + la t0, trap_entry + csrw mtvec, t0 + + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + /* set to initial state of FPU and disable interrupt */ + li t0, MSTATUS_FS + csrs mstatus, t0 + + fssr x0 + fmv.d.x f0, x0 + fmv.d.x f1, x0 + fmv.d.x f2, x0 + fmv.d.x f3, x0 + fmv.d.x f4, x0 + fmv.d.x f5, x0 + fmv.d.x f6, x0 + fmv.d.x f7, x0 + fmv.d.x f8, x0 + fmv.d.x f9, x0 + fmv.d.x f10,x0 + fmv.d.x f11,x0 + fmv.d.x f12,x0 + fmv.d.x f13,x0 + fmv.d.x f14,x0 + fmv.d.x f15,x0 + fmv.d.x f16,x0 + fmv.d.x f17,x0 + fmv.d.x f18,x0 + fmv.d.x f19,x0 + fmv.d.x f20,x0 + fmv.d.x f21,x0 + fmv.d.x f22,x0 + fmv.d.x f23,x0 + fmv.d.x f24,x0 + fmv.d.x f25,x0 + fmv.d.x f26,x0 + fmv.d.x f27,x0 + fmv.d.x f28,x0 + fmv.d.x f29,x0 + fmv.d.x f30,x0 + fmv.d.x f31,x0 + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* get cpu id */ + csrr a0, mhartid + + la sp, __stack_start__ + addi t1, a0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + /* other cpu core, jump to cpu entry directly */ + bnez a0, secondary_cpu_entry + j primary_cpu_entry + +secondary_cpu_entry: +#ifdef RT_USING_SMP + la a0, secondary_boot_flag + ld a0, 0(a0) + li a1, 0xa55a + beq a0, a1, secondary_cpu_c_start +#endif + j secondary_cpu_entry + +#ifdef RT_USING_SMP +.data +.global secondary_boot_flag +.align 3 +secondary_boot_flag: + .dword 0 +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/tick.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/tick.c new file mode 100644 index 0000000000..144f7f1fff --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/tick.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#include +#include + +#include +#include +#include + +static volatile unsigned long tick_cycles = 0; +int tick_isr(void) +{ + uint64_t core_id = current_coreid(); + + clint->mtimecmp[core_id] += tick_cycles; + rt_tick_increase(); + + return 0; +} + +/* Sets and enable the timer interrupt */ +int rt_hw_tick_init(void) +{ + /* Read core id */ + unsigned long core_id = current_coreid(); + unsigned long interval = 1000/RT_TICK_PER_SECOND; + + /* Clear the Machine-Timer bit in MIE */ + clear_csr(mie, MIP_MTIP); + + /* calculate the tick cycles */ + tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1; + /* Set mtimecmp by core id */ + clint->mtimecmp[core_id] = clint->mtime + tick_cycles; + + /* Enable the Machine-Timer bit in MIE */ + set_csr(mie, MIP_MTIP); + + return 0; +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/tick.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/tick.h new file mode 100644 index 0000000000..0821004263 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/k210/tick.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#ifndef TICK_H__ +#define TICK_H__ + +int tick_isr(void); +int rt_hw_tick_init(void); + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/rv32m1/interrupt.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/rv32m1/interrupt.c new file mode 100644 index 0000000000..72cb344ff7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/rv32m1/interrupt.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + */ + +#include + +#include +#include + +typedef void (*irq_handler_t)(void); +extern const irq_handler_t isrTable[]; + +void SystemIrqHandler(uint32_t mcause) +{ + uint32_t intNum; + + if (mcause & 0x80000000) /* For external interrupt. */ + { + intNum = mcause & 0x1FUL; + + /* Clear pending flag in EVENT unit .*/ + EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum); + + /* Now call the real irq handler for intNum */ + isrTable[intNum](); + } +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/rv32m1/interrupt_gcc.S b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/rv32m1/interrupt_gcc.S new file mode 100644 index 0000000000..eacf667c67 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/libcpu/risc-v/rv32m1/interrupt_gcc.S @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + */ + +#include "cpuport.h" + + .section .text.entry + .align 2 + .global IRQ_Handler +IRQ_Handler: + + /* save all from thread context */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + move s0, sp + + /* switch to interrupt stack */ + la sp, __stack + + /* interrupt handle */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call SystemIrqHandler + call rt_interrupt_leave + + /* switch to from thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + /* clear switch interrupt flag */ + sw zero, 0(s0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + +spurious_interrupt: + LOAD x1, 1 * REGBYTES(sp) + + /* Remain in M-mode after mret */ + li t0, 0x00001800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/rtconfig.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/rtconfig.h new file mode 100644 index 0000000000..11de5b209c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/rtconfig.h @@ -0,0 +1,154 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +#include "RTE_Components.h" + +#if defined(RTE_USING_FINSH) +#define RT_USING_FINSH +#endif //RTE_USING_FINSH + +#endif //(__CC_ARM) || (__CLANG_ARM) + +// <<< Use Configuration Wizard in Context Menu >>> +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 8 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 8 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 256 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +//#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +//#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +//#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Dynamic Heap Management +// Dynamic Heap Management +#define RT_USING_HEAP +// +// using small memory +// using small memory +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 128 +// + +#if defined(RT_USING_FINSH) + #define FINSH_USING_MSH + #define FINSH_USING_MSH_ONLY + // Finsh Configuration + // the priority of finsh thread <1-7> + // the priority of finsh thread + // Default: 6 + #define __FINSH_THREAD_PRIORITY 5 + #define FINSH_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX / 8 * __FINSH_THREAD_PRIORITY + 1) + // the stack of finsh thread <1-4096> + // the stack of finsh thread + // Default: 4096 (4096Byte) + #define FINSH_THREAD_STACK_SIZE 512 + // the history lines of finsh thread <1-32> + // the history lines of finsh thread + // Default: 5 + #define FINSH_HISTORY_LINES 1 + + #define FINSH_USING_SYMTAB + // +#endif + +// <<< end of configuration section >>> + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/clock.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/clock.c new file mode 100644 index 0000000000..e969a19b5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/clock.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-12 Bernard first version + * 2006-05-27 Bernard add support for same priority thread schedule + * 2006-08-10 Bernard remove the last rt_schedule in rt_tick_increase + * 2010-03-08 Bernard remove rt_passed_second + * 2010-05-20 Bernard fix the tick exceeds the maximum limits + * 2010-07-13 Bernard fix rt_tick_from_millisecond issue found by kuronca + * 2011-06-26 Bernard add rt_tick_set function. + */ + +#include +#include + +static rt_tick_t rt_tick = 0; + +/** + * This function will init system tick and set it to zero. + * @ingroup SystemInit + * + * @deprecated since 1.1.0, this function does not need to be invoked + * in the system initialization. + */ +void rt_system_tick_init(void) +{ +} + +/** + * @addtogroup Clock + */ + +/**@{*/ + +/** + * This function will return current tick from operating system startup + * + * @return current tick + */ +rt_tick_t rt_tick_get(void) +{ + /* return the global tick */ + return rt_tick; +} +RTM_EXPORT(rt_tick_get); + +/** + * This function will set current tick + */ +void rt_tick_set(rt_tick_t tick) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + rt_tick = tick; + rt_hw_interrupt_enable(level); +} + +/** + * This function will notify kernel there is one tick passed. Normally, + * this function is invoked by clock ISR. + */ +void rt_tick_increase(void) +{ + struct rt_thread *thread; + + /* increase the global tick */ + ++ rt_tick; + + /* check time slice */ + thread = rt_thread_self(); + + -- thread->remaining_tick; + if (thread->remaining_tick == 0) + { + /* change to initialized tick */ + thread->remaining_tick = thread->init_tick; + + /* yield */ + rt_thread_yield(); + } + + /* check timer */ + rt_timer_check(); +} + +/** + * This function will calculate the tick from millisecond. + * + * @param ms the specified millisecond + * - Negative Number wait forever + * - Zero not wait + * - Max 0x7fffffff + * + * @return the calculated tick + */ +rt_tick_t rt_tick_from_millisecond(rt_int32_t ms) +{ + rt_tick_t tick; + + if (ms < 0) + { + tick = (rt_tick_t)RT_WAITING_FOREVER; + } + else + { + tick = RT_TICK_PER_SECOND * (ms / 1000); + tick += (RT_TICK_PER_SECOND * (ms % 1000) + 999) / 1000; + } + + /* return the calculated tick */ + return tick; +} +RTM_EXPORT(rt_tick_from_millisecond); + +/**@}*/ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/components.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/components.c new file mode 100644 index 0000000000..67658afde5 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/components.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-09-20 Bernard Change the name to components.c + * And all components related header files. + * 2012-12-23 Bernard fix the pthread initialization issue. + * 2013-06-23 Bernard Add the init_call for components initialization. + * 2013-07-05 Bernard Remove initialization feature for MS VC++ compiler + * 2015-02-06 Bernard Remove the MS VC++ support and move to the kernel + * 2015-05-04 Bernard Rename it to components.c because compiling issue + * in some IDEs. + * 2015-07-29 Arda.Fu Add support to use RT_USING_USER_MAIN with IAR + */ + +#include +#include + +#ifdef RT_USING_USER_MAIN +#ifndef RT_MAIN_THREAD_STACK_SIZE +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#endif +#ifndef RT_MAIN_THREAD_PRIORITY +#define RT_MAIN_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX / 3) +#endif +#endif + +#ifdef RT_USING_COMPONENTS_INIT +/* + * Components Initialization will initialize some driver and components as following + * order: + * rti_start --> 0 + * BOARD_EXPORT --> 1 + * rti_board_end --> 1.end + * + * DEVICE_EXPORT --> 2 + * COMPONENT_EXPORT --> 3 + * FS_EXPORT --> 4 + * ENV_EXPORT --> 5 + * APP_EXPORT --> 6 + * + * rti_end --> 6.end + * + * These automatically initialization, the driver or component initial function must + * be defined with: + * INIT_BOARD_EXPORT(fn); + * INIT_DEVICE_EXPORT(fn); + * ... + * INIT_APP_EXPORT(fn); + * etc. + */ +static int rti_start(void) +{ + return 0; +} +INIT_EXPORT(rti_start, "0"); + +static int rti_board_start(void) +{ + return 0; +} +INIT_EXPORT(rti_board_start, "0.end"); + +static int rti_board_end(void) +{ + return 0; +} +INIT_EXPORT(rti_board_end, "1.end"); + +static int rti_end(void) +{ + return 0; +} +INIT_EXPORT(rti_end, "6.end"); + +/** + * RT-Thread Components Initialization for board + */ +void rt_components_board_init(void) +{ +#if RT_DEBUG_INIT + int result; + const struct rt_init_desc *desc; + for (desc = &__rt_init_desc_rti_board_start; desc < &__rt_init_desc_rti_board_end; desc ++) + { + rt_kprintf("initialize %s", desc->fn_name); + result = desc->fn(); + rt_kprintf(":%d done\n", result); + } +#else + const init_fn_t *fn_ptr; + + for (fn_ptr = &__rt_init_rti_board_start; fn_ptr < &__rt_init_rti_board_end; fn_ptr++) + { + (*fn_ptr)(); + } +#endif +} + +/** + * RT-Thread Components Initialization + */ +void rt_components_init(void) +{ +#if RT_DEBUG_INIT + int result; + const struct rt_init_desc *desc; + + rt_kprintf("do components initialization.\n"); + for (desc = &__rt_init_desc_rti_board_end; desc < &__rt_init_desc_rti_end; desc ++) + { + rt_kprintf("initialize %s", desc->fn_name); + result = desc->fn(); + rt_kprintf(":%d done\n", result); + } +#else + const init_fn_t *fn_ptr; + + for (fn_ptr = &__rt_init_rti_board_end; fn_ptr < &__rt_init_rti_end; fn_ptr ++) + { + (*fn_ptr)(); + } +#endif +} + +#ifdef RT_USING_USER_MAIN + +void rt_application_init(void); +void rt_hw_board_init(void); +int rtthread_startup(void); + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + rtthread_startup(); + return 0; +} +#elif defined(__ICCARM__) +extern int main(void); +/* __low_level_init will auto called by IAR cstartup */ +extern void __iar_data_init3(void); +int __low_level_init(void) +{ + // call IAR table copy function. + __iar_data_init3(); + rtthread_startup(); + return 0; +} +#elif defined(__GNUC__) +extern int main(void); +/* Add -eentry to arm-none-eabi-gcc argument */ +int entry(void) +{ + rtthread_startup(); + return 0; +} +#endif + +#ifndef RT_USING_HEAP +/* if there is not enable heap, we should use static thread and stack. */ +ALIGN(8) +static rt_uint8_t main_stack[RT_MAIN_THREAD_STACK_SIZE]; +struct rt_thread main_thread; +#endif + +/* the system main thread */ +void main_thread_entry(void *parameter) +{ + extern int main(void); + extern int $Super$$main(void); + + /* RT-Thread components initialization */ + rt_components_init(); + + /* invoke system main function */ +#if defined(__CC_ARM) || defined(__CLANG_ARM) + $Super$$main(); /* for ARMCC. */ +#elif defined(__ICCARM__) || defined(__GNUC__) + main(); +#endif +} + +void rt_application_init(void) +{ + rt_thread_t tid; + +#ifdef RT_USING_HEAP + tid = rt_thread_create("main", main_thread_entry, RT_NULL, + RT_MAIN_THREAD_STACK_SIZE, RT_MAIN_THREAD_PRIORITY, 20); + RT_ASSERT(tid != RT_NULL); +#else + rt_err_t result; + + tid = &main_thread; + result = rt_thread_init(tid, "main", main_thread_entry, RT_NULL, + main_stack, sizeof(main_stack), RT_MAIN_THREAD_PRIORITY, 20); + RT_ASSERT(result == RT_EOK); + + /* if not define RT_USING_HEAP, using to eliminate the warning */ + (void)result; +#endif + + rt_thread_startup(tid); +} + +int rtthread_startup(void) +{ + rt_hw_interrupt_disable(); + + /* board level initialization + * NOTE: please initialize heap inside board initialization. + */ + rt_hw_board_init(); + + /* show RT-Thread version */ + rt_show_version(); + + /* timer system initialization */ + rt_system_timer_init(); + + /* scheduler system initialization */ + rt_system_scheduler_init(); + +#ifdef RT_USING_SIGNALS + /* signal system initialization */ + rt_system_signal_init(); +#endif + + /* create init_thread */ + rt_application_init(); + + /* timer thread initialization */ + rt_system_timer_thread_init(); + + /* idle thread initialization */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return 0; +} +#endif +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/cpu.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/cpu.c new file mode 100644 index 0000000000..5cba05fe70 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/cpu.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 Bernard The first version + */ + +#include +#include + +/* nothing on non-smp version */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/idle.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/idle.c new file mode 100644 index 0000000000..bf5f2d1dc8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/idle.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-23 Bernard the first version + * 2010-11-10 Bernard add cleanup callback function in thread exit. + * 2012-12-29 Bernard fix compiling warning. + * 2013-12-21 Grissiom let rt_thread_idle_excute loop until there is no + * dead thread. + * 2016-08-09 ArdaFu add method to get the handler of the idle thread. + * 2018-02-07 Bernard lock scheduler to protect tid->cleanup. + * 2018-07-14 armink add idle hook list + */ + +#include +#include + +#ifdef RT_USING_MODULE +#include +#endif + +#if defined (RT_USING_HOOK) +#ifndef RT_USING_IDLE_HOOK +#define RT_USING_IDLE_HOOK +#endif +#endif + +#ifndef IDLE_THREAD_STACK_SIZE +#if defined (RT_USING_IDLE_HOOK) || defined(RT_USING_HEAP) +#define IDLE_THREAD_STACK_SIZE 256 +#else +#define IDLE_THREAD_STACK_SIZE 128 +#endif +#endif + +static struct rt_thread idle; +ALIGN(RT_ALIGN_SIZE) +static rt_uint8_t rt_thread_stack[IDLE_THREAD_STACK_SIZE]; + +extern rt_list_t rt_thread_defunct; + +#ifdef RT_USING_IDLE_HOOK + +#ifndef RT_IDEL_HOOK_LIST_SIZE +#define RT_IDEL_HOOK_LIST_SIZE 4 +#endif + +static void (*idle_hook_list[RT_IDEL_HOOK_LIST_SIZE])(); + +/** + * @ingroup Hook + * This function sets a hook function to idle thread loop. When the system performs + * idle loop, this hook function should be invoked. + * + * @param hook the specified hook function + * + * @return RT_EOK: set OK + * -RT_EFULL: hook list is full + * + * @note the hook function must be simple and never be blocked or suspend. + */ +rt_err_t rt_thread_idle_sethook(void (*hook)(void)) +{ + rt_size_t i; + rt_base_t level; + rt_err_t ret = -RT_EFULL; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + for (i = 0; i < RT_IDEL_HOOK_LIST_SIZE; i++) + { + if (idle_hook_list[i] == RT_NULL) + { + idle_hook_list[i] = hook; + ret = RT_EOK; + break; + } + } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + return ret; +} + +/** + * delete the idle hook on hook list + * + * @param hook the specified hook function + * + * @return RT_EOK: delete OK + * -RT_ENOSYS: hook was not found + */ +rt_err_t rt_thread_idle_delhook(void (*hook)(void)) +{ + rt_size_t i; + rt_base_t level; + rt_err_t ret = -RT_ENOSYS; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + for (i = 0; i < RT_IDEL_HOOK_LIST_SIZE; i++) + { + if (idle_hook_list[i] == hook) + { + idle_hook_list[i] = RT_NULL; + ret = RT_EOK; + break; + } + } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + return ret; +} + +#endif + +/* Return whether there is defunctional thread to be deleted. */ +rt_inline int _has_defunct_thread(void) +{ + /* The rt_list_isempty has prototype of "int rt_list_isempty(const rt_list_t *l)". + * So the compiler has a good reason that the rt_thread_defunct list does + * not change within rt_thread_idle_excute thus optimize the "while" loop + * into a "if". + * + * So add the volatile qualifier here. */ + const volatile rt_list_t *l = (const volatile rt_list_t *)&rt_thread_defunct; + + return l->next != l; +} + +/** + * @ingroup Thread + * + * This function will perform system background job when system idle. + */ +void rt_thread_idle_excute(void) +{ + /* Loop until there is no dead thread. So one call to rt_thread_idle_excute + * will do all the cleanups. */ + while (_has_defunct_thread()) + { + rt_base_t lock; + rt_thread_t thread; +#ifdef RT_USING_MODULE + struct rt_dlmodule *module = RT_NULL; +#endif + RT_DEBUG_NOT_IN_INTERRUPT; + + /* disable interrupt */ + lock = rt_hw_interrupt_disable(); + + /* re-check whether list is empty */ + if (_has_defunct_thread()) + { + /* get defunct thread */ + thread = rt_list_entry(rt_thread_defunct.next, + struct rt_thread, + tlist); +#ifdef RT_USING_MODULE + module = (struct rt_dlmodule*)thread->module_id; + if (module) + { + dlmodule_destroy(module); + } +#endif + /* remove defunct thread */ + rt_list_remove(&(thread->tlist)); + + /* lock scheduler to prevent scheduling in cleanup function. */ + rt_enter_critical(); + + /* invoke thread cleanup */ + if (thread->cleanup != RT_NULL) + thread->cleanup(thread); + +#ifdef RT_USING_SIGNALS + rt_thread_free_sig(thread); +#endif + + /* if it's a system object, not delete it */ + if (rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE) + { + /* detach this object */ + rt_object_detach((rt_object_t)thread); + /* unlock scheduler */ + rt_exit_critical(); + + /* enable interrupt */ + rt_hw_interrupt_enable(lock); + + return; + } + + /* unlock scheduler */ + rt_exit_critical(); + } + else + { + /* enable interrupt */ + rt_hw_interrupt_enable(lock); + + /* may the defunct thread list is removed by others, just return */ + return; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(lock); + +#ifdef RT_USING_HEAP + /* release thread's stack */ + RT_KERNEL_FREE(thread->stack_addr); + /* delete thread object */ + rt_object_delete((rt_object_t)thread); +#endif + } +} + +extern void rt_system_power_manager(void); +static void rt_thread_idle_entry(void *parameter) +{ + while (1) + { + +#ifdef RT_USING_IDLE_HOOK + rt_size_t i; + + for (i = 0; i < RT_IDEL_HOOK_LIST_SIZE; i++) + { + if (idle_hook_list[i] != RT_NULL) + { + idle_hook_list[i](); + } + } +#endif + + rt_thread_idle_excute(); +#ifdef RT_USING_PM + rt_system_power_manager(); +#endif + } +} + +/** + * @ingroup SystemInit + * + * This function will initialize idle thread, then start it. + * + * @note this function must be invoked when system init. + */ +void rt_thread_idle_init(void) +{ + /* initialize thread */ + rt_thread_init(&idle, + "tidle", + rt_thread_idle_entry, + RT_NULL, + &rt_thread_stack[0], + sizeof(rt_thread_stack), + RT_THREAD_PRIORITY_MAX - 1, + 32); + + /* startup */ + rt_thread_startup(&idle); +} + +/** + * @ingroup Thread + * + * This function will get the handler of the idle thread. + * + */ +rt_thread_t rt_thread_idle_gethandler(void) +{ + return (rt_thread_t)(&idle); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/ipc.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/ipc.c new file mode 100644 index 0000000000..36b714d19f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/ipc.c @@ -0,0 +1,2328 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-14 Bernard the first version + * 2006-04-25 Bernard implement semaphore + * 2006-05-03 Bernard add RT_IPC_DEBUG + * modify the type of IPC waiting time to rt_int32_t + * 2006-05-10 Bernard fix the semaphore take bug and add IPC object + * 2006-05-12 Bernard implement mailbox and message queue + * 2006-05-20 Bernard implement mutex + * 2006-05-23 Bernard implement fast event + * 2006-05-24 Bernard implement event + * 2006-06-03 Bernard fix the thread timer init bug + * 2006-06-05 Bernard fix the mutex release bug + * 2006-06-07 Bernard fix the message queue send bug + * 2006-08-04 Bernard add hook support + * 2009-05-21 Yi.qiu fix the sem release bug + * 2009-07-18 Bernard fix the event clear bug + * 2009-09-09 Bernard remove fast event and fix ipc release bug + * 2009-10-10 Bernard change semaphore and mutex value to unsigned value + * 2009-10-25 Bernard change the mb/mq receive timeout to 0 if the + * re-calculated delta tick is a negative number. + * 2009-12-16 Bernard fix the rt_ipc_object_suspend issue when IPC flag + * is RT_IPC_FLAG_PRIO + * 2010-01-20 mbbill remove rt_ipc_object_decrease function. + * 2010-04-20 Bernard move memcpy outside interrupt disable in mq + * 2010-10-26 yi.qiu add module support in rt_mp_delete and rt_mq_delete + * 2010-11-10 Bernard add IPC reset command implementation. + * 2011-12-18 Bernard add more parameter checking in message queue + * 2013-09-14 Grissiom add an option check in rt_event_recv + */ + +#include +#include + +#ifdef RT_USING_HOOK +extern void (*rt_object_trytake_hook)(struct rt_object *object); +extern void (*rt_object_take_hook)(struct rt_object *object); +extern void (*rt_object_put_hook)(struct rt_object *object); +#endif + +/** + * @addtogroup IPC + */ + +/**@{*/ + +/** + * This function will initialize an IPC object + * + * @param ipc the IPC object + * + * @return the operation status, RT_EOK on successful + */ +rt_inline rt_err_t rt_ipc_object_init(struct rt_ipc_object *ipc) +{ + /* init ipc object */ + rt_list_init(&(ipc->suspend_thread)); + + return RT_EOK; +} + +/** + * This function will suspend a thread to a specified list. IPC object or some + * double-queue object (mailbox etc.) contains this kind of list. + * + * @param list the IPC suspended thread list + * @param thread the thread object to be suspended + * @param flag the IPC object flag, + * which shall be RT_IPC_FLAG_FIFO/RT_IPC_FLAG_PRIO. + * + * @return the operation status, RT_EOK on successful + */ +rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t *list, + struct rt_thread *thread, + rt_uint8_t flag) +{ + /* suspend thread */ + rt_thread_suspend(thread); + + switch (flag) + { + case RT_IPC_FLAG_FIFO: + rt_list_insert_before(list, &(thread->tlist)); + break; + + case RT_IPC_FLAG_PRIO: + { + struct rt_list_node *n; + struct rt_thread *sthread; + + /* find a suitable position */ + for (n = list->next; n != list; n = n->next) + { + sthread = rt_list_entry(n, struct rt_thread, tlist); + + /* find out */ + if (thread->current_priority < sthread->current_priority) + { + /* insert this thread before the sthread */ + rt_list_insert_before(&(sthread->tlist), &(thread->tlist)); + break; + } + } + + /* + * not found a suitable position, + * append to the end of suspend_thread list + */ + if (n == list) + rt_list_insert_before(list, &(thread->tlist)); + } + break; + } + + return RT_EOK; +} + +/** + * This function will resume the first thread in the list of a IPC object: + * - remove the thread from suspend queue of IPC object + * - put the thread into system ready queue + * + * @param list the thread list + * + * @return the operation status, RT_EOK on successful + */ +rt_inline rt_err_t rt_ipc_list_resume(rt_list_t *list) +{ + struct rt_thread *thread; + + /* get thread entry */ + thread = rt_list_entry(list->next, struct rt_thread, tlist); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("resume thread:%s\n", thread->name)); + + /* resume it */ + rt_thread_resume(thread); + + return RT_EOK; +} + +/** + * This function will resume all suspended threads in a list, including + * suspend list of IPC object and private list of mailbox etc. + * + * @param list of the threads to resume + * + * @return the operation status, RT_EOK on successful + */ +rt_inline rt_err_t rt_ipc_list_resume_all(rt_list_t *list) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + + /* wakeup all suspend threads */ + while (!rt_list_isempty(list)) + { + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* get next suspend thread */ + thread = rt_list_entry(list->next, struct rt_thread, tlist); + /* set error code to RT_ERROR */ + thread->error = -RT_ERROR; + + /* + * resume thread + * In rt_thread_resume function, it will remove current thread from + * suspend list + */ + rt_thread_resume(thread); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + } + + return RT_EOK; +} + +#ifdef RT_USING_SEMAPHORE +/** + * This function will initialize a semaphore and put it under control of + * resource management. + * + * @param sem the semaphore object + * @param name the name of semaphore + * @param value the init value of semaphore + * @param flag the flag of semaphore + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_sem_init(rt_sem_t sem, + const char *name, + rt_uint32_t value, + rt_uint8_t flag) +{ + RT_ASSERT(sem != RT_NULL); + RT_ASSERT(value < 0x10000U); + + /* init object */ + rt_object_init(&(sem->parent.parent), RT_Object_Class_Semaphore, name); + + /* init ipc object */ + rt_ipc_object_init(&(sem->parent)); + + /* set init value */ + sem->value = (rt_uint16_t)value; + + /* set parent */ + sem->parent.parent.flag = flag; + + return RT_EOK; +} +RTM_EXPORT(rt_sem_init); + +/** + * This function will detach a semaphore from resource management + * + * @param sem the semaphore object + * + * @return the operation status, RT_EOK on successful + * + * @see rt_sem_delete + */ +rt_err_t rt_sem_detach(rt_sem_t sem) +{ + /* parameter check */ + RT_ASSERT(sem != RT_NULL); + RT_ASSERT(rt_object_get_type(&sem->parent.parent) == RT_Object_Class_Semaphore); + RT_ASSERT(rt_object_is_systemobject(&sem->parent.parent)); + + /* wakeup all suspend threads */ + rt_ipc_list_resume_all(&(sem->parent.suspend_thread)); + + /* detach semaphore object */ + rt_object_detach(&(sem->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_sem_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a semaphore from system resource + * + * @param name the name of semaphore + * @param value the init value of semaphore + * @param flag the flag of semaphore + * + * @return the created semaphore, RT_NULL on error happen + * + * @see rt_sem_init + */ +rt_sem_t rt_sem_create(const char *name, rt_uint32_t value, rt_uint8_t flag) +{ + rt_sem_t sem; + + RT_DEBUG_NOT_IN_INTERRUPT; + RT_ASSERT(value < 0x10000U); + + /* allocate object */ + sem = (rt_sem_t)rt_object_allocate(RT_Object_Class_Semaphore, name); + if (sem == RT_NULL) + return sem; + + /* init ipc object */ + rt_ipc_object_init(&(sem->parent)); + + /* set init value */ + sem->value = value; + + /* set parent */ + sem->parent.parent.flag = flag; + + return sem; +} +RTM_EXPORT(rt_sem_create); + +/** + * This function will delete a semaphore object and release the memory + * + * @param sem the semaphore object + * + * @return the error code + * + * @see rt_sem_detach + */ +rt_err_t rt_sem_delete(rt_sem_t sem) +{ + RT_DEBUG_NOT_IN_INTERRUPT; + + /* parameter check */ + RT_ASSERT(sem != RT_NULL); + RT_ASSERT(rt_object_get_type(&sem->parent.parent) == RT_Object_Class_Semaphore); + RT_ASSERT(rt_object_is_systemobject(&sem->parent.parent) == RT_FALSE); + + /* wakeup all suspend threads */ + rt_ipc_list_resume_all(&(sem->parent.suspend_thread)); + + /* delete semaphore object */ + rt_object_delete(&(sem->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_sem_delete); +#endif + +/** + * This function will take a semaphore, if the semaphore is unavailable, the + * thread shall wait for a specified time. + * + * @param sem the semaphore object + * @param time the waiting time + * + * @return the error code + */ +rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t time) +{ + register rt_base_t temp; + struct rt_thread *thread; + + /* parameter check */ + RT_ASSERT(sem != RT_NULL); + RT_ASSERT(rt_object_get_type(&sem->parent.parent) == RT_Object_Class_Semaphore); + + RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(sem->parent.parent))); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("thread %s take sem:%s, which value is: %d\n", + rt_thread_self()->name, + ((struct rt_object *)sem)->name, + sem->value)); + + if (sem->value > 0) + { + /* semaphore is available */ + sem->value --; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + } + else + { + /* no waiting, return with timeout */ + if (time == 0) + { + rt_hw_interrupt_enable(temp); + + return -RT_ETIMEOUT; + } + else + { + /* current context checking */ + RT_DEBUG_IN_THREAD_CONTEXT; + + /* semaphore is unavailable, push to suspend list */ + /* get current thread */ + thread = rt_thread_self(); + + /* reset thread error number */ + thread->error = RT_EOK; + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("sem take: suspend thread - %s\n", + thread->name)); + + /* suspend thread */ + rt_ipc_list_suspend(&(sem->parent.suspend_thread), + thread, + sem->parent.parent.flag); + + /* has waiting time, start thread timer */ + if (time > 0) + { + RT_DEBUG_LOG(RT_DEBUG_IPC, ("set thread:%s to timer list\n", + thread->name)); + + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* do schedule */ + rt_schedule(); + + if (thread->error != RT_EOK) + { + return thread->error; + } + } + } + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(sem->parent.parent))); + + return RT_EOK; +} +RTM_EXPORT(rt_sem_take); + +/** + * This function will try to take a semaphore and immediately return + * + * @param sem the semaphore object + * + * @return the error code + */ +rt_err_t rt_sem_trytake(rt_sem_t sem) +{ + return rt_sem_take(sem, 0); +} +RTM_EXPORT(rt_sem_trytake); + +/** + * This function will release a semaphore, if there are threads suspended on + * semaphore, it will be waked up. + * + * @param sem the semaphore object + * + * @return the error code + */ +rt_err_t rt_sem_release(rt_sem_t sem) +{ + register rt_base_t temp; + register rt_bool_t need_schedule; + + /* parameter check */ + RT_ASSERT(sem != RT_NULL); + RT_ASSERT(rt_object_get_type(&sem->parent.parent) == RT_Object_Class_Semaphore); + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(sem->parent.parent))); + + need_schedule = RT_FALSE; + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("thread %s releases sem:%s, which value is: %d\n", + rt_thread_self()->name, + ((struct rt_object *)sem)->name, + sem->value)); + + if (!rt_list_isempty(&sem->parent.suspend_thread)) + { + /* resume the suspended thread */ + rt_ipc_list_resume(&(sem->parent.suspend_thread)); + need_schedule = RT_TRUE; + } + else + sem->value ++; /* increase value */ + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* resume a thread, re-schedule */ + if (need_schedule == RT_TRUE) + rt_schedule(); + + return RT_EOK; +} +RTM_EXPORT(rt_sem_release); + +/** + * This function can get or set some extra attributions of a semaphore object. + * + * @param sem the semaphore object + * @param cmd the execution command + * @param arg the execution argument + * + * @return the error code + */ +rt_err_t rt_sem_control(rt_sem_t sem, int cmd, void *arg) +{ + rt_ubase_t level; + + /* parameter check */ + RT_ASSERT(sem != RT_NULL); + RT_ASSERT(rt_object_get_type(&sem->parent.parent) == RT_Object_Class_Semaphore); + + if (cmd == RT_IPC_CMD_RESET) + { + rt_uint32_t value; + + /* get value */ + value = (rt_uint32_t)arg; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* resume all waiting thread */ + rt_ipc_list_resume_all(&sem->parent.suspend_thread); + + /* set new value */ + sem->value = (rt_uint16_t)value; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_schedule(); + + return RT_EOK; + } + + return -RT_ERROR; +} +RTM_EXPORT(rt_sem_control); +#endif /* end of RT_USING_SEMAPHORE */ + +#ifdef RT_USING_MUTEX +/** + * This function will initialize a mutex and put it under control of resource + * management. + * + * @param mutex the mutex object + * @param name the name of mutex + * @param flag the flag of mutex + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_mutex_init(rt_mutex_t mutex, const char *name, rt_uint8_t flag) +{ + /* parameter check */ + RT_ASSERT(mutex != RT_NULL); + + /* init object */ + rt_object_init(&(mutex->parent.parent), RT_Object_Class_Mutex, name); + + /* init ipc object */ + rt_ipc_object_init(&(mutex->parent)); + + mutex->value = 1; + mutex->owner = RT_NULL; + mutex->original_priority = 0xFF; + mutex->hold = 0; + + /* set flag */ + mutex->parent.parent.flag = flag; + + return RT_EOK; +} +RTM_EXPORT(rt_mutex_init); + +/** + * This function will detach a mutex from resource management + * + * @param mutex the mutex object + * + * @return the operation status, RT_EOK on successful + * + * @see rt_mutex_delete + */ +rt_err_t rt_mutex_detach(rt_mutex_t mutex) +{ + /* parameter check */ + RT_ASSERT(mutex != RT_NULL); + RT_ASSERT(rt_object_get_type(&mutex->parent.parent) == RT_Object_Class_Mutex); + RT_ASSERT(rt_object_is_systemobject(&mutex->parent.parent)); + + /* wakeup all suspend threads */ + rt_ipc_list_resume_all(&(mutex->parent.suspend_thread)); + + /* detach semaphore object */ + rt_object_detach(&(mutex->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mutex_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a mutex from system resource + * + * @param name the name of mutex + * @param flag the flag of mutex + * + * @return the created mutex, RT_NULL on error happen + * + * @see rt_mutex_init + */ +rt_mutex_t rt_mutex_create(const char *name, rt_uint8_t flag) +{ + struct rt_mutex *mutex; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* allocate object */ + mutex = (rt_mutex_t)rt_object_allocate(RT_Object_Class_Mutex, name); + if (mutex == RT_NULL) + return mutex; + + /* init ipc object */ + rt_ipc_object_init(&(mutex->parent)); + + mutex->value = 1; + mutex->owner = RT_NULL; + mutex->original_priority = 0xFF; + mutex->hold = 0; + + /* set flag */ + mutex->parent.parent.flag = flag; + + return mutex; +} +RTM_EXPORT(rt_mutex_create); + +/** + * This function will delete a mutex object and release the memory + * + * @param mutex the mutex object + * + * @return the error code + * + * @see rt_mutex_detach + */ +rt_err_t rt_mutex_delete(rt_mutex_t mutex) +{ + RT_DEBUG_NOT_IN_INTERRUPT; + + /* parameter check */ + RT_ASSERT(mutex != RT_NULL); + RT_ASSERT(rt_object_get_type(&mutex->parent.parent) == RT_Object_Class_Mutex); + RT_ASSERT(rt_object_is_systemobject(&mutex->parent.parent) == RT_FALSE); + + /* wakeup all suspend threads */ + rt_ipc_list_resume_all(&(mutex->parent.suspend_thread)); + + /* delete semaphore object */ + rt_object_delete(&(mutex->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mutex_delete); +#endif + +/** + * This function will take a mutex, if the mutex is unavailable, the + * thread shall wait for a specified time. + * + * @param mutex the mutex object + * @param time the waiting time + * + * @return the error code + */ +rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time) +{ + register rt_base_t temp; + struct rt_thread *thread; + + /* this function must not be used in interrupt even if time = 0 */ + RT_DEBUG_IN_THREAD_CONTEXT; + + /* parameter check */ + RT_ASSERT(mutex != RT_NULL); + RT_ASSERT(rt_object_get_type(&mutex->parent.parent) == RT_Object_Class_Mutex); + + /* get current thread */ + thread = rt_thread_self(); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(mutex->parent.parent))); + + RT_DEBUG_LOG(RT_DEBUG_IPC, + ("mutex_take: current thread %s, mutex value: %d, hold: %d\n", + thread->name, mutex->value, mutex->hold)); + + /* reset thread error */ + thread->error = RT_EOK; + + if (mutex->owner == thread) + { + /* it's the same thread */ + mutex->hold ++; + } + else + { +__again: + /* The value of mutex is 1 in initial status. Therefore, if the + * value is great than 0, it indicates the mutex is avaible. + */ + if (mutex->value > 0) + { + /* mutex is available */ + mutex->value --; + + /* set mutex owner and original priority */ + mutex->owner = thread; + mutex->original_priority = thread->current_priority; + mutex->hold ++; + } + else + { + /* no waiting, return with timeout */ + if (time == 0) + { + /* set error as timeout */ + thread->error = -RT_ETIMEOUT; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return -RT_ETIMEOUT; + } + else + { + /* mutex is unavailable, push to suspend list */ + RT_DEBUG_LOG(RT_DEBUG_IPC, ("mutex_take: suspend thread: %s\n", + thread->name)); + + /* change the owner thread priority of mutex */ + if (thread->current_priority < mutex->owner->current_priority) + { + /* change the owner thread priority */ + rt_thread_control(mutex->owner, + RT_THREAD_CTRL_CHANGE_PRIORITY, + &thread->current_priority); + } + + /* suspend current thread */ + rt_ipc_list_suspend(&(mutex->parent.suspend_thread), + thread, + mutex->parent.parent.flag); + + /* has waiting time, start thread timer */ + if (time > 0) + { + RT_DEBUG_LOG(RT_DEBUG_IPC, + ("mutex_take: start the timer of thread:%s\n", + thread->name)); + + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* do schedule */ + rt_schedule(); + + if (thread->error != RT_EOK) + { + /* interrupt by signal, try it again */ + if (thread->error == -RT_EINTR) goto __again; + + /* return error */ + return thread->error; + } + else + { + /* the mutex is taken successfully. */ + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + } + } + } + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(mutex->parent.parent))); + + return RT_EOK; +} +RTM_EXPORT(rt_mutex_take); + +/** + * This function will release a mutex, if there are threads suspended on mutex, + * it will be waked up. + * + * @param mutex the mutex object + * + * @return the error code + */ +rt_err_t rt_mutex_release(rt_mutex_t mutex) +{ + register rt_base_t temp; + struct rt_thread *thread; + rt_bool_t need_schedule; + + /* parameter check */ + RT_ASSERT(mutex != RT_NULL); + RT_ASSERT(rt_object_get_type(&mutex->parent.parent) == RT_Object_Class_Mutex); + + need_schedule = RT_FALSE; + + /* only thread could release mutex because we need test the ownership */ + RT_DEBUG_IN_THREAD_CONTEXT; + + /* get current thread */ + thread = rt_thread_self(); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + RT_DEBUG_LOG(RT_DEBUG_IPC, + ("mutex_release:current thread %s, mutex value: %d, hold: %d\n", + thread->name, mutex->value, mutex->hold)); + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(mutex->parent.parent))); + + /* mutex only can be released by owner */ + if (thread != mutex->owner) + { + thread->error = -RT_ERROR; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return -RT_ERROR; + } + + /* decrease hold */ + mutex->hold --; + /* if no hold */ + if (mutex->hold == 0) + { + /* change the owner thread to original priority */ + if (mutex->original_priority != mutex->owner->current_priority) + { + rt_thread_control(mutex->owner, + RT_THREAD_CTRL_CHANGE_PRIORITY, + &(mutex->original_priority)); + } + + /* wakeup suspended thread */ + if (!rt_list_isempty(&mutex->parent.suspend_thread)) + { + /* get suspended thread */ + thread = rt_list_entry(mutex->parent.suspend_thread.next, + struct rt_thread, + tlist); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("mutex_release: resume thread: %s\n", + thread->name)); + + /* set new owner and priority */ + mutex->owner = thread; + mutex->original_priority = thread->current_priority; + mutex->hold ++; + + /* resume thread */ + rt_ipc_list_resume(&(mutex->parent.suspend_thread)); + + need_schedule = RT_TRUE; + } + else + { + /* increase value */ + mutex->value ++; + + /* clear owner */ + mutex->owner = RT_NULL; + mutex->original_priority = 0xff; + } + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* perform a schedule */ + if (need_schedule == RT_TRUE) + rt_schedule(); + + return RT_EOK; +} +RTM_EXPORT(rt_mutex_release); + +/** + * This function can get or set some extra attributions of a mutex object. + * + * @param mutex the mutex object + * @param cmd the execution command + * @param arg the execution argument + * + * @return the error code + */ +rt_err_t rt_mutex_control(rt_mutex_t mutex, int cmd, void *arg) +{ + /* parameter check */ + RT_ASSERT(mutex != RT_NULL); + RT_ASSERT(rt_object_get_type(&mutex->parent.parent) == RT_Object_Class_Mutex); + + return -RT_ERROR; +} +RTM_EXPORT(rt_mutex_control); +#endif /* end of RT_USING_MUTEX */ + +#ifdef RT_USING_EVENT +/** + * This function will initialize an event and put it under control of resource + * management. + * + * @param event the event object + * @param name the name of event + * @param flag the flag of event + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_event_init(rt_event_t event, const char *name, rt_uint8_t flag) +{ + /* parameter check */ + RT_ASSERT(event != RT_NULL); + + /* init object */ + rt_object_init(&(event->parent.parent), RT_Object_Class_Event, name); + + /* set parent flag */ + event->parent.parent.flag = flag; + + /* init ipc object */ + rt_ipc_object_init(&(event->parent)); + + /* init event */ + event->set = 0; + + return RT_EOK; +} +RTM_EXPORT(rt_event_init); + +/** + * This function will detach an event object from resource management + * + * @param event the event object + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_event_detach(rt_event_t event) +{ + /* parameter check */ + RT_ASSERT(event != RT_NULL); + RT_ASSERT(rt_object_get_type(&event->parent.parent) == RT_Object_Class_Event); + RT_ASSERT(rt_object_is_systemobject(&event->parent.parent)); + + /* resume all suspended thread */ + rt_ipc_list_resume_all(&(event->parent.suspend_thread)); + + /* detach event object */ + rt_object_detach(&(event->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_event_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create an event object from system resource + * + * @param name the name of event + * @param flag the flag of event + * + * @return the created event, RT_NULL on error happen + */ +rt_event_t rt_event_create(const char *name, rt_uint8_t flag) +{ + rt_event_t event; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* allocate object */ + event = (rt_event_t)rt_object_allocate(RT_Object_Class_Event, name); + if (event == RT_NULL) + return event; + + /* set parent */ + event->parent.parent.flag = flag; + + /* init ipc object */ + rt_ipc_object_init(&(event->parent)); + + /* init event */ + event->set = 0; + + return event; +} +RTM_EXPORT(rt_event_create); + +/** + * This function will delete an event object and release the memory + * + * @param event the event object + * + * @return the error code + */ +rt_err_t rt_event_delete(rt_event_t event) +{ + /* parameter check */ + RT_ASSERT(event != RT_NULL); + RT_ASSERT(rt_object_get_type(&event->parent.parent) == RT_Object_Class_Event); + RT_ASSERT(rt_object_is_systemobject(&event->parent.parent) == RT_FALSE); + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* resume all suspended thread */ + rt_ipc_list_resume_all(&(event->parent.suspend_thread)); + + /* delete event object */ + rt_object_delete(&(event->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_event_delete); +#endif + +/** + * This function will send an event to the event object, if there are threads + * suspended on event object, it will be waked up. + * + * @param event the event object + * @param set the event set + * + * @return the error code + */ +rt_err_t rt_event_send(rt_event_t event, rt_uint32_t set) +{ + struct rt_list_node *n; + struct rt_thread *thread; + register rt_ubase_t level; + register rt_base_t status; + rt_bool_t need_schedule; + + /* parameter check */ + RT_ASSERT(event != RT_NULL); + RT_ASSERT(rt_object_get_type(&event->parent.parent) == RT_Object_Class_Event); + + if (set == 0) + return -RT_ERROR; + + need_schedule = RT_FALSE; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* set event */ + event->set |= set; + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(event->parent.parent))); + + if (!rt_list_isempty(&event->parent.suspend_thread)) + { + /* search thread list to resume thread */ + n = event->parent.suspend_thread.next; + while (n != &(event->parent.suspend_thread)) + { + /* get thread */ + thread = rt_list_entry(n, struct rt_thread, tlist); + + status = -RT_ERROR; + if (thread->event_info & RT_EVENT_FLAG_AND) + { + if ((thread->event_set & event->set) == thread->event_set) + { + /* received an AND event */ + status = RT_EOK; + } + } + else if (thread->event_info & RT_EVENT_FLAG_OR) + { + if (thread->event_set & event->set) + { + /* save recieved event set */ + thread->event_set = thread->event_set & event->set; + + /* received an OR event */ + status = RT_EOK; + } + } + + /* move node to the next */ + n = n->next; + + /* condition is satisfied, resume thread */ + if (status == RT_EOK) + { + /* clear event */ + if (thread->event_info & RT_EVENT_FLAG_CLEAR) + event->set &= ~thread->event_set; + + /* resume thread, and thread list breaks out */ + rt_thread_resume(thread); + + /* need do a scheduling */ + need_schedule = RT_TRUE; + } + } + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* do a schedule */ + if (need_schedule == RT_TRUE) + rt_schedule(); + + return RT_EOK; +} +RTM_EXPORT(rt_event_send); + +/** + * This function will receive an event from event object, if the event is + * unavailable, the thread shall wait for a specified time. + * + * @param event the fast event object + * @param set the interested event set + * @param option the receive option, either RT_EVENT_FLAG_AND or + * RT_EVENT_FLAG_OR should be set. + * @param timeout the waiting time + * @param recved the received event, if you don't care, RT_NULL can be set. + * + * @return the error code + */ +rt_err_t rt_event_recv(rt_event_t event, + rt_uint32_t set, + rt_uint8_t option, + rt_int32_t timeout, + rt_uint32_t *recved) +{ + struct rt_thread *thread; + register rt_ubase_t level; + register rt_base_t status; + + RT_DEBUG_IN_THREAD_CONTEXT; + + /* parameter check */ + RT_ASSERT(event != RT_NULL); + RT_ASSERT(rt_object_get_type(&event->parent.parent) == RT_Object_Class_Event); + + if (set == 0) + return -RT_ERROR; + + /* init status */ + status = -RT_ERROR; + /* get current thread */ + thread = rt_thread_self(); + /* reset thread error */ + thread->error = RT_EOK; + + RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(event->parent.parent))); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* check event set */ + if (option & RT_EVENT_FLAG_AND) + { + if ((event->set & set) == set) + status = RT_EOK; + } + else if (option & RT_EVENT_FLAG_OR) + { + if (event->set & set) + status = RT_EOK; + } + else + { + /* either RT_EVENT_FLAG_AND or RT_EVENT_FLAG_OR should be set */ + RT_ASSERT(0); + } + + if (status == RT_EOK) + { + /* set received event */ + if (recved) + *recved = (event->set & set); + + /* received event */ + if (option & RT_EVENT_FLAG_CLEAR) + event->set &= ~set; + } + else if (timeout == 0) + { + /* no waiting */ + thread->error = -RT_ETIMEOUT; + } + else + { + /* fill thread event info */ + thread->event_set = set; + thread->event_info = option; + + /* put thread to suspended thread list */ + rt_ipc_list_suspend(&(event->parent.suspend_thread), + thread, + event->parent.parent.flag); + + /* if there is a waiting timeout, active thread timer */ + if (timeout > 0) + { + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &timeout); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* do a schedule */ + rt_schedule(); + + if (thread->error != RT_EOK) + { + /* return error */ + return thread->error; + } + + /* received an event, disable interrupt to protect */ + level = rt_hw_interrupt_disable(); + + /* set received event */ + if (recved) + *recved = thread->event_set; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(event->parent.parent))); + + return thread->error; +} +RTM_EXPORT(rt_event_recv); + +/** + * This function can get or set some extra attributions of an event object. + * + * @param event the event object + * @param cmd the execution command + * @param arg the execution argument + * + * @return the error code + */ +rt_err_t rt_event_control(rt_event_t event, int cmd, void *arg) +{ + rt_ubase_t level; + + /* parameter check */ + RT_ASSERT(event != RT_NULL); + RT_ASSERT(rt_object_get_type(&event->parent.parent) == RT_Object_Class_Event); + + if (cmd == RT_IPC_CMD_RESET) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* resume all waiting thread */ + rt_ipc_list_resume_all(&event->parent.suspend_thread); + + /* init event set */ + event->set = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_schedule(); + + return RT_EOK; + } + + return -RT_ERROR; +} +RTM_EXPORT(rt_event_control); +#endif /* end of RT_USING_EVENT */ + +#ifdef RT_USING_MAILBOX +/** + * This function will initialize a mailbox and put it under control of resource + * management. + * + * @param mb the mailbox object + * @param name the name of mailbox + * @param msgpool the begin address of buffer to save received mail + * @param size the size of mailbox + * @param flag the flag of mailbox + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_mb_init(rt_mailbox_t mb, + const char *name, + void *msgpool, + rt_size_t size, + rt_uint8_t flag) +{ + RT_ASSERT(mb != RT_NULL); + + /* init object */ + rt_object_init(&(mb->parent.parent), RT_Object_Class_MailBox, name); + + /* set parent flag */ + mb->parent.parent.flag = flag; + + /* init ipc object */ + rt_ipc_object_init(&(mb->parent)); + + /* init mailbox */ + mb->msg_pool = msgpool; + mb->size = size; + mb->entry = 0; + mb->in_offset = 0; + mb->out_offset = 0; + + /* init an additional list of sender suspend thread */ + rt_list_init(&(mb->suspend_sender_thread)); + + return RT_EOK; +} +RTM_EXPORT(rt_mb_init); + +/** + * This function will detach a mailbox from resource management + * + * @param mb the mailbox object + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_mb_detach(rt_mailbox_t mb) +{ + /* parameter check */ + RT_ASSERT(mb != RT_NULL); + RT_ASSERT(rt_object_get_type(&mb->parent.parent) == RT_Object_Class_MailBox); + RT_ASSERT(rt_object_is_systemobject(&mb->parent.parent)); + + /* resume all suspended thread */ + rt_ipc_list_resume_all(&(mb->parent.suspend_thread)); + /* also resume all mailbox private suspended thread */ + rt_ipc_list_resume_all(&(mb->suspend_sender_thread)); + + /* detach mailbox object */ + rt_object_detach(&(mb->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mb_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a mailbox object from system resource + * + * @param name the name of mailbox + * @param size the size of mailbox + * @param flag the flag of mailbox + * + * @return the created mailbox, RT_NULL on error happen + */ +rt_mailbox_t rt_mb_create(const char *name, rt_size_t size, rt_uint8_t flag) +{ + rt_mailbox_t mb; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* allocate object */ + mb = (rt_mailbox_t)rt_object_allocate(RT_Object_Class_MailBox, name); + if (mb == RT_NULL) + return mb; + + /* set parent */ + mb->parent.parent.flag = flag; + + /* init ipc object */ + rt_ipc_object_init(&(mb->parent)); + + /* init mailbox */ + mb->size = size; + mb->msg_pool = RT_KERNEL_MALLOC(mb->size * sizeof(rt_uint32_t)); + if (mb->msg_pool == RT_NULL) + { + /* delete mailbox object */ + rt_object_delete(&(mb->parent.parent)); + + return RT_NULL; + } + mb->entry = 0; + mb->in_offset = 0; + mb->out_offset = 0; + + /* init an additional list of sender suspend thread */ + rt_list_init(&(mb->suspend_sender_thread)); + + return mb; +} +RTM_EXPORT(rt_mb_create); + +/** + * This function will delete a mailbox object and release the memory + * + * @param mb the mailbox object + * + * @return the error code + */ +rt_err_t rt_mb_delete(rt_mailbox_t mb) +{ + RT_DEBUG_NOT_IN_INTERRUPT; + + /* parameter check */ + RT_ASSERT(mb != RT_NULL); + RT_ASSERT(rt_object_get_type(&mb->parent.parent) == RT_Object_Class_MailBox); + RT_ASSERT(rt_object_is_systemobject(&mb->parent.parent) == RT_FALSE); + + /* resume all suspended thread */ + rt_ipc_list_resume_all(&(mb->parent.suspend_thread)); + + /* also resume all mailbox private suspended thread */ + rt_ipc_list_resume_all(&(mb->suspend_sender_thread)); + + /* free mailbox pool */ + RT_KERNEL_FREE(mb->msg_pool); + + /* delete mailbox object */ + rt_object_delete(&(mb->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mb_delete); +#endif + +/** + * This function will send a mail to mailbox object. If the mailbox is full, + * current thread will be suspended until timeout. + * + * @param mb the mailbox object + * @param value the mail + * @param timeout the waiting time + * + * @return the error code + */ +rt_err_t rt_mb_send_wait(rt_mailbox_t mb, + rt_uint32_t value, + rt_int32_t timeout) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + rt_uint32_t tick_delta; + + /* parameter check */ + RT_ASSERT(mb != RT_NULL); + RT_ASSERT(rt_object_get_type(&mb->parent.parent) == RT_Object_Class_MailBox); + + /* initialize delta tick */ + tick_delta = 0; + /* get current thread */ + thread = rt_thread_self(); + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(mb->parent.parent))); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* for non-blocking call */ + if (mb->entry == mb->size && timeout == 0) + { + rt_hw_interrupt_enable(temp); + + return -RT_EFULL; + } + + /* mailbox is full */ + while (mb->entry == mb->size) + { + /* reset error number in thread */ + thread->error = RT_EOK; + + /* no waiting, return timeout */ + if (timeout == 0) + { + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return -RT_EFULL; + } + + RT_DEBUG_IN_THREAD_CONTEXT; + /* suspend current thread */ + rt_ipc_list_suspend(&(mb->suspend_sender_thread), + thread, + mb->parent.parent.flag); + + /* has waiting time, start thread timer */ + if (timeout > 0) + { + /* get the start tick of timer */ + tick_delta = rt_tick_get(); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("mb_send_wait: start timer of thread:%s\n", + thread->name)); + + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &timeout); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* re-schedule */ + rt_schedule(); + + /* resume from suspend state */ + if (thread->error != RT_EOK) + { + /* return error */ + return thread->error; + } + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* if it's not waiting forever and then re-calculate timeout tick */ + if (timeout > 0) + { + tick_delta = rt_tick_get() - tick_delta; + timeout -= tick_delta; + if (timeout < 0) + timeout = 0; + } + } + + /* set ptr */ + mb->msg_pool[mb->in_offset] = value; + /* increase input offset */ + ++ mb->in_offset; + if (mb->in_offset >= mb->size) + mb->in_offset = 0; + /* increase message entry */ + mb->entry ++; + + /* resume suspended thread */ + if (!rt_list_isempty(&mb->parent.suspend_thread)) + { + rt_ipc_list_resume(&(mb->parent.suspend_thread)); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + rt_schedule(); + + return RT_EOK; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return RT_EOK; +} +RTM_EXPORT(rt_mb_send_wait); + +/** + * This function will send a mail to mailbox object, if there are threads + * suspended on mailbox object, it will be waked up. This function will return + * immediately, if you want blocking send, use rt_mb_send_wait instead. + * + * @param mb the mailbox object + * @param value the mail + * + * @return the error code + */ +rt_err_t rt_mb_send(rt_mailbox_t mb, rt_uint32_t value) +{ + return rt_mb_send_wait(mb, value, 0); +} +RTM_EXPORT(rt_mb_send); + +/** + * This function will receive a mail from mailbox object, if there is no mail + * in mailbox object, the thread shall wait for a specified time. + * + * @param mb the mailbox object + * @param value the received mail will be saved in + * @param timeout the waiting time + * + * @return the error code + */ +rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_uint32_t *value, rt_int32_t timeout) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + rt_uint32_t tick_delta; + + /* parameter check */ + RT_ASSERT(mb != RT_NULL); + RT_ASSERT(rt_object_get_type(&mb->parent.parent) == RT_Object_Class_MailBox); + + /* initialize delta tick */ + tick_delta = 0; + /* get current thread */ + thread = rt_thread_self(); + + RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(mb->parent.parent))); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* for non-blocking call */ + if (mb->entry == 0 && timeout == 0) + { + rt_hw_interrupt_enable(temp); + + return -RT_ETIMEOUT; + } + + /* mailbox is empty */ + while (mb->entry == 0) + { + /* reset error number in thread */ + thread->error = RT_EOK; + + /* no waiting, return timeout */ + if (timeout == 0) + { + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + thread->error = -RT_ETIMEOUT; + + return -RT_ETIMEOUT; + } + + RT_DEBUG_IN_THREAD_CONTEXT; + /* suspend current thread */ + rt_ipc_list_suspend(&(mb->parent.suspend_thread), + thread, + mb->parent.parent.flag); + + /* has waiting time, start thread timer */ + if (timeout > 0) + { + /* get the start tick of timer */ + tick_delta = rt_tick_get(); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("mb_recv: start timer of thread:%s\n", + thread->name)); + + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &timeout); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* re-schedule */ + rt_schedule(); + + /* resume from suspend state */ + if (thread->error != RT_EOK) + { + /* return error */ + return thread->error; + } + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* if it's not waiting forever and then re-calculate timeout tick */ + if (timeout > 0) + { + tick_delta = rt_tick_get() - tick_delta; + timeout -= tick_delta; + if (timeout < 0) + timeout = 0; + } + } + + /* fill ptr */ + *value = mb->msg_pool[mb->out_offset]; + + /* increase output offset */ + ++ mb->out_offset; + if (mb->out_offset >= mb->size) + mb->out_offset = 0; + /* decrease message entry */ + mb->entry --; + + /* resume suspended thread */ + if (!rt_list_isempty(&(mb->suspend_sender_thread))) + { + rt_ipc_list_resume(&(mb->suspend_sender_thread)); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(mb->parent.parent))); + + rt_schedule(); + + return RT_EOK; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(mb->parent.parent))); + + return RT_EOK; +} +RTM_EXPORT(rt_mb_recv); + +/** + * This function can get or set some extra attributions of a mailbox object. + * + * @param mb the mailbox object + * @param cmd the execution command + * @param arg the execution argument + * + * @return the error code + */ +rt_err_t rt_mb_control(rt_mailbox_t mb, int cmd, void *arg) +{ + rt_ubase_t level; + + /* parameter check */ + RT_ASSERT(mb != RT_NULL); + RT_ASSERT(rt_object_get_type(&mb->parent.parent) == RT_Object_Class_MailBox); + + if (cmd == RT_IPC_CMD_RESET) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* resume all waiting thread */ + rt_ipc_list_resume_all(&(mb->parent.suspend_thread)); + /* also resume all mailbox private suspended thread */ + rt_ipc_list_resume_all(&(mb->suspend_sender_thread)); + + /* re-init mailbox */ + mb->entry = 0; + mb->in_offset = 0; + mb->out_offset = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_schedule(); + + return RT_EOK; + } + + return -RT_ERROR; +} +RTM_EXPORT(rt_mb_control); +#endif /* end of RT_USING_MAILBOX */ + +#ifdef RT_USING_MESSAGEQUEUE +struct rt_mq_message +{ + struct rt_mq_message *next; +}; + +/** + * This function will initialize a message queue and put it under control of + * resource management. + * + * @param mq the message object + * @param name the name of message queue + * @param msgpool the beginning address of buffer to save messages + * @param msg_size the maximum size of message + * @param pool_size the size of buffer to save messages + * @param flag the flag of message queue + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_mq_init(rt_mq_t mq, + const char *name, + void *msgpool, + rt_size_t msg_size, + rt_size_t pool_size, + rt_uint8_t flag) +{ + struct rt_mq_message *head; + register rt_base_t temp; + + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + + /* init object */ + rt_object_init(&(mq->parent.parent), RT_Object_Class_MessageQueue, name); + + /* set parent flag */ + mq->parent.parent.flag = flag; + + /* init ipc object */ + rt_ipc_object_init(&(mq->parent)); + + /* set messasge pool */ + mq->msg_pool = msgpool; + + /* get correct message size */ + mq->msg_size = RT_ALIGN(msg_size, RT_ALIGN_SIZE); + mq->max_msgs = pool_size / (mq->msg_size + sizeof(struct rt_mq_message)); + + /* init message list */ + mq->msg_queue_head = RT_NULL; + mq->msg_queue_tail = RT_NULL; + + /* init message empty list */ + mq->msg_queue_free = RT_NULL; + for (temp = 0; temp < mq->max_msgs; temp ++) + { + head = (struct rt_mq_message *)((rt_uint8_t *)mq->msg_pool + + temp * (mq->msg_size + sizeof(struct rt_mq_message))); + head->next = mq->msg_queue_free; + mq->msg_queue_free = head; + } + + /* the initial entry is zero */ + mq->entry = 0; + + return RT_EOK; +} +RTM_EXPORT(rt_mq_init); + +/** + * This function will detach a message queue object from resource management + * + * @param mq the message queue object + * + * @return the operation status, RT_EOK on successful + */ +rt_err_t rt_mq_detach(rt_mq_t mq) +{ + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + RT_ASSERT(rt_object_get_type(&mq->parent.parent) == RT_Object_Class_MessageQueue); + RT_ASSERT(rt_object_is_systemobject(&mq->parent.parent)); + + /* resume all suspended thread */ + rt_ipc_list_resume_all(&mq->parent.suspend_thread); + + /* detach message queue object */ + rt_object_detach(&(mq->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mq_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a message queue object from system resource + * + * @param name the name of message queue + * @param msg_size the size of message + * @param max_msgs the maximum number of message in queue + * @param flag the flag of message queue + * + * @return the created message queue, RT_NULL on error happen + */ +rt_mq_t rt_mq_create(const char *name, + rt_size_t msg_size, + rt_size_t max_msgs, + rt_uint8_t flag) +{ + struct rt_messagequeue *mq; + struct rt_mq_message *head; + register rt_base_t temp; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* allocate object */ + mq = (rt_mq_t)rt_object_allocate(RT_Object_Class_MessageQueue, name); + if (mq == RT_NULL) + return mq; + + /* set parent */ + mq->parent.parent.flag = flag; + + /* init ipc object */ + rt_ipc_object_init(&(mq->parent)); + + /* init message queue */ + + /* get correct message size */ + mq->msg_size = RT_ALIGN(msg_size, RT_ALIGN_SIZE); + mq->max_msgs = max_msgs; + + /* allocate message pool */ + mq->msg_pool = RT_KERNEL_MALLOC((mq->msg_size + sizeof(struct rt_mq_message)) * mq->max_msgs); + if (mq->msg_pool == RT_NULL) + { + rt_mq_delete(mq); + + return RT_NULL; + } + + /* init message list */ + mq->msg_queue_head = RT_NULL; + mq->msg_queue_tail = RT_NULL; + + /* init message empty list */ + mq->msg_queue_free = RT_NULL; + for (temp = 0; temp < mq->max_msgs; temp ++) + { + head = (struct rt_mq_message *)((rt_uint8_t *)mq->msg_pool + + temp * (mq->msg_size + sizeof(struct rt_mq_message))); + head->next = mq->msg_queue_free; + mq->msg_queue_free = head; + } + + /* the initial entry is zero */ + mq->entry = 0; + + return mq; +} +RTM_EXPORT(rt_mq_create); + +/** + * This function will delete a message queue object and release the memory + * + * @param mq the message queue object + * + * @return the error code + */ +rt_err_t rt_mq_delete(rt_mq_t mq) +{ + RT_DEBUG_NOT_IN_INTERRUPT; + + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + RT_ASSERT(rt_object_get_type(&mq->parent.parent) == RT_Object_Class_MessageQueue); + RT_ASSERT(rt_object_is_systemobject(&mq->parent.parent) == RT_FALSE); + + /* resume all suspended thread */ + rt_ipc_list_resume_all(&(mq->parent.suspend_thread)); + + /* free message queue pool */ + RT_KERNEL_FREE(mq->msg_pool); + + /* delete message queue object */ + rt_object_delete(&(mq->parent.parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mq_delete); +#endif + +/** + * This function will send a message to message queue object, if there are + * threads suspended on message queue object, it will be waked up. + * + * @param mq the message queue object + * @param buffer the message + * @param size the size of buffer + * + * @return the error code + */ +rt_err_t rt_mq_send(rt_mq_t mq, void *buffer, rt_size_t size) +{ + register rt_ubase_t temp; + struct rt_mq_message *msg; + + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + RT_ASSERT(rt_object_get_type(&mq->parent.parent) == RT_Object_Class_MessageQueue); + RT_ASSERT(buffer != RT_NULL); + RT_ASSERT(size != 0); + + /* greater than one message size */ + if (size > mq->msg_size) + return -RT_ERROR; + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(mq->parent.parent))); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* get a free list, there must be an empty item */ + msg = (struct rt_mq_message *)mq->msg_queue_free; + /* message queue is full */ + if (msg == RT_NULL) + { + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return -RT_EFULL; + } + /* move free list pointer */ + mq->msg_queue_free = msg->next; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* the msg is the new tailer of list, the next shall be NULL */ + msg->next = RT_NULL; + /* copy buffer */ + rt_memcpy(msg + 1, buffer, size); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + /* link msg to message queue */ + if (mq->msg_queue_tail != RT_NULL) + { + /* if the tail exists, */ + ((struct rt_mq_message *)mq->msg_queue_tail)->next = msg; + } + + /* set new tail */ + mq->msg_queue_tail = msg; + /* if the head is empty, set head */ + if (mq->msg_queue_head == RT_NULL) + mq->msg_queue_head = msg; + + /* increase message entry */ + mq->entry ++; + + /* resume suspended thread */ + if (!rt_list_isempty(&mq->parent.suspend_thread)) + { + rt_ipc_list_resume(&(mq->parent.suspend_thread)); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + rt_schedule(); + + return RT_EOK; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return RT_EOK; +} +RTM_EXPORT(rt_mq_send); + +/** + * This function will send an urgent message to message queue object, which + * means the message will be inserted to the head of message queue. If there + * are threads suspended on message queue object, it will be waked up. + * + * @param mq the message queue object + * @param buffer the message + * @param size the size of buffer + * + * @return the error code + */ +rt_err_t rt_mq_urgent(rt_mq_t mq, void *buffer, rt_size_t size) +{ + register rt_ubase_t temp; + struct rt_mq_message *msg; + + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + RT_ASSERT(rt_object_get_type(&mq->parent.parent) == RT_Object_Class_MessageQueue); + RT_ASSERT(buffer != RT_NULL); + RT_ASSERT(size != 0); + + /* greater than one message size */ + if (size > mq->msg_size) + return -RT_ERROR; + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(mq->parent.parent))); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* get a free list, there must be an empty item */ + msg = (struct rt_mq_message *)mq->msg_queue_free; + /* message queue is full */ + if (msg == RT_NULL) + { + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return -RT_EFULL; + } + /* move free list pointer */ + mq->msg_queue_free = msg->next; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* copy buffer */ + rt_memcpy(msg + 1, buffer, size); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* link msg to the beginning of message queue */ + msg->next = mq->msg_queue_head; + mq->msg_queue_head = msg; + + /* if there is no tail */ + if (mq->msg_queue_tail == RT_NULL) + mq->msg_queue_tail = msg; + + /* increase message entry */ + mq->entry ++; + + /* resume suspended thread */ + if (!rt_list_isempty(&mq->parent.suspend_thread)) + { + rt_ipc_list_resume(&(mq->parent.suspend_thread)); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + rt_schedule(); + + return RT_EOK; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + return RT_EOK; +} +RTM_EXPORT(rt_mq_urgent); + +/** + * This function will receive a message from message queue object, if there is + * no message in message queue object, the thread shall wait for a specified + * time. + * + * @param mq the message queue object + * @param buffer the received message will be saved in + * @param size the size of buffer + * @param timeout the waiting time + * + * @return the error code + */ +rt_err_t rt_mq_recv(rt_mq_t mq, + void *buffer, + rt_size_t size, + rt_int32_t timeout) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + struct rt_mq_message *msg; + rt_uint32_t tick_delta; + + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + RT_ASSERT(rt_object_get_type(&mq->parent.parent) == RT_Object_Class_MessageQueue); + RT_ASSERT(buffer != RT_NULL); + RT_ASSERT(size != 0); + + /* initialize delta tick */ + tick_delta = 0; + /* get current thread */ + thread = rt_thread_self(); + RT_OBJECT_HOOK_CALL(rt_object_trytake_hook, (&(mq->parent.parent))); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* for non-blocking call */ + if (mq->entry == 0 && timeout == 0) + { + rt_hw_interrupt_enable(temp); + + return -RT_ETIMEOUT; + } + + /* message queue is empty */ + while (mq->entry == 0) + { + RT_DEBUG_IN_THREAD_CONTEXT; + + /* reset error number in thread */ + thread->error = RT_EOK; + + /* no waiting, return timeout */ + if (timeout == 0) + { + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + thread->error = -RT_ETIMEOUT; + + return -RT_ETIMEOUT; + } + + /* suspend current thread */ + rt_ipc_list_suspend(&(mq->parent.suspend_thread), + thread, + mq->parent.parent.flag); + + /* has waiting time, start thread timer */ + if (timeout > 0) + { + /* get the start tick of timer */ + tick_delta = rt_tick_get(); + + RT_DEBUG_LOG(RT_DEBUG_IPC, ("set thread:%s to timer list\n", + thread->name)); + + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &timeout); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* re-schedule */ + rt_schedule(); + + /* recv message */ + if (thread->error != RT_EOK) + { + /* return error */ + return thread->error; + } + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* if it's not waiting forever and then re-calculate timeout tick */ + if (timeout > 0) + { + tick_delta = rt_tick_get() - tick_delta; + timeout -= tick_delta; + if (timeout < 0) + timeout = 0; + } + } + + /* get message from queue */ + msg = (struct rt_mq_message *)mq->msg_queue_head; + + /* move message queue head */ + mq->msg_queue_head = msg->next; + /* reach queue tail, set to NULL */ + if (mq->msg_queue_tail == msg) + mq->msg_queue_tail = RT_NULL; + + /* decrease message entry */ + mq->entry --; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* copy message */ + rt_memcpy(buffer, msg + 1, size > mq->msg_size ? mq->msg_size : size); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + /* put message to free list */ + msg->next = (struct rt_mq_message *)mq->msg_queue_free; + mq->msg_queue_free = msg; + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(mq->parent.parent))); + + return RT_EOK; +} +RTM_EXPORT(rt_mq_recv); + +/** + * This function can get or set some extra attributions of a message queue + * object. + * + * @param mq the message queue object + * @param cmd the execution command + * @param arg the execution argument + * + * @return the error code + */ +rt_err_t rt_mq_control(rt_mq_t mq, int cmd, void *arg) +{ + rt_ubase_t level; + struct rt_mq_message *msg; + + /* parameter check */ + RT_ASSERT(mq != RT_NULL); + RT_ASSERT(rt_object_get_type(&mq->parent.parent) == RT_Object_Class_MessageQueue); + + if (cmd == RT_IPC_CMD_RESET) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* resume all waiting thread */ + rt_ipc_list_resume_all(&mq->parent.suspend_thread); + + /* release all message in the queue */ + while (mq->msg_queue_head != RT_NULL) + { + /* get message from queue */ + msg = (struct rt_mq_message *)mq->msg_queue_head; + + /* move message queue head */ + mq->msg_queue_head = msg->next; + /* reach queue tail, set to NULL */ + if (mq->msg_queue_tail == msg) + mq->msg_queue_tail = RT_NULL; + + /* put message to free list */ + msg->next = (struct rt_mq_message *)mq->msg_queue_free; + mq->msg_queue_free = msg; + } + + /* clean entry */ + mq->entry = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_schedule(); + + return RT_EOK; + } + + return -RT_ERROR; +} +RTM_EXPORT(rt_mq_control); +#endif /* end of RT_USING_MESSAGEQUEUE */ + +/**@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/irq.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/irq.c new file mode 100644 index 0000000000..72d220bd92 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/irq.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-02-24 Bernard first version + * 2006-05-03 Bernard add IRQ_DEBUG + * 2016-08-09 ArdaFu add interrupt enter and leave hook. + */ + +#include +#include + +#ifdef RT_USING_HOOK + +static void (*rt_interrupt_enter_hook)(void); +static void (*rt_interrupt_leave_hook)(void); + +/** + * @ingroup Hook + * This function set a hook function when the system enter a interrupt + * + * @note the hook function must be simple and never be blocked or suspend. + */ +void rt_interrupt_enter_sethook(void (*hook)(void)) +{ + rt_interrupt_enter_hook = hook; +} +/** + * @ingroup Hook + * This function set a hook function when the system exit a interrupt. + * + * @note the hook function must be simple and never be blocked or suspend. + */ +void rt_interrupt_leave_sethook(void (*hook)(void)) +{ + rt_interrupt_leave_hook = hook; +} +#endif + +/* #define IRQ_DEBUG */ + +/** + * @addtogroup Kernel + */ + +/**@{*/ + +volatile rt_uint8_t rt_interrupt_nest; + +/** + * This function will be invoked by BSP, when enter interrupt service routine + * + * @note please don't invoke this routine in application + * + * @see rt_interrupt_leave + */ +void rt_interrupt_enter(void) +{ + rt_base_t level; + + RT_DEBUG_LOG(RT_DEBUG_IRQ, ("irq coming..., irq nest:%d\n", + rt_interrupt_nest)); + + level = rt_hw_interrupt_disable(); + rt_interrupt_nest ++; + RT_OBJECT_HOOK_CALL(rt_interrupt_enter_hook,()); + rt_hw_interrupt_enable(level); +} +RTM_EXPORT(rt_interrupt_enter); + +/** + * This function will be invoked by BSP, when leave interrupt service routine + * + * @note please don't invoke this routine in application + * + * @see rt_interrupt_enter + */ +void rt_interrupt_leave(void) +{ + rt_base_t level; + + RT_DEBUG_LOG(RT_DEBUG_IRQ, ("irq leave, irq nest:%d\n", + rt_interrupt_nest)); + + level = rt_hw_interrupt_disable(); + rt_interrupt_nest --; + RT_OBJECT_HOOK_CALL(rt_interrupt_leave_hook,()); + rt_hw_interrupt_enable(level); +} +RTM_EXPORT(rt_interrupt_leave); + +/** + * This function will return the nest of interrupt. + * + * User application can invoke this function to get whether current + * context is interrupt context. + * + * @return the number of nested interrupts. + */ +rt_uint8_t rt_interrupt_get_nest(void) +{ + return rt_interrupt_nest; +} +RTM_EXPORT(rt_interrupt_get_nest); + +RTM_EXPORT(rt_hw_interrupt_disable); +RTM_EXPORT(rt_hw_interrupt_enable); + +/**@}*/ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/kservice.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/kservice.c new file mode 100644 index 0000000000..1d3dace340 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/kservice.c @@ -0,0 +1,1397 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-16 Bernard the first version + * 2006-05-25 Bernard rewrite vsprintf + * 2006-08-10 Bernard add rt_show_version + * 2010-03-17 Bernard remove rt_strlcpy function + * fix gcc compiling issue. + * 2010-04-15 Bernard remove weak definition on ICCM16C compiler + * 2012-07-18 Arda add the alignment display for signed integer + * 2012-11-23 Bernard fix IAR compiler error. + * 2012-12-22 Bernard fix rt_kprintf issue, which found by Grissiom. + * 2013-06-24 Bernard remove rt_kprintf if RT_USING_CONSOLE is not defined. + * 2013-09-24 aozima make sure the device is in STREAM mode when used by rt_kprintf. + * 2015-07-06 Bernard Add rt_assert_handler routine. + */ + +#include +#include + +#ifdef RT_USING_MODULE +#include +#endif + +/* use precision */ +#define RT_PRINTF_PRECISION + +/** + * @addtogroup KernelService + */ + +/**@{*/ + +/* global errno in RT-Thread */ +static volatile int __rt_errno; + +#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE) +static rt_device_t _console_device = RT_NULL; +#endif + +/* + * This function will get errno + * + * @return errno + */ +rt_err_t rt_get_errno(void) +{ + rt_thread_t tid; + + if (rt_interrupt_get_nest() != 0) + { + /* it's in interrupt context */ + return __rt_errno; + } + + tid = rt_thread_self(); + if (tid == RT_NULL) + return __rt_errno; + + return tid->error; +} +RTM_EXPORT(rt_get_errno); + +/* + * This function will set errno + * + * @param error the errno shall be set + */ +void rt_set_errno(rt_err_t error) +{ + rt_thread_t tid; + + if (rt_interrupt_get_nest() != 0) + { + /* it's in interrupt context */ + __rt_errno = error; + + return; + } + + tid = rt_thread_self(); + if (tid == RT_NULL) + { + __rt_errno = error; + + return; + } + + tid->error = error; +} +RTM_EXPORT(rt_set_errno); + +/** + * This function returns errno. + * + * @return the errno in the system + */ +int *_rt_errno(void) +{ + rt_thread_t tid; + + if (rt_interrupt_get_nest() != 0) + return (int *)&__rt_errno; + + tid = rt_thread_self(); + if (tid != RT_NULL) + return (int *) & (tid->error); + + return (int *)&__rt_errno; +} +RTM_EXPORT(_rt_errno); + +/** + * This function will set the content of memory to specified value + * + * @param s the address of source memory + * @param c the value shall be set in content + * @param count the copied length + * + * @return the address of source memory + */ +void *rt_memset(void *s, int c, rt_ubase_t count) +{ +#ifdef RT_USING_TINY_SIZE + char *xs = (char *)s; + + while (count--) + *xs++ = c; + + return s; +#else +#define LBLOCKSIZE (sizeof(long)) +#define UNALIGNED(X) ((long)X & (LBLOCKSIZE - 1)) +#define TOO_SMALL(LEN) ((LEN) < LBLOCKSIZE) + + unsigned int i; + char *m = (char *)s; + unsigned long buffer; + unsigned long *aligned_addr; + unsigned int d = c & 0xff; /* To avoid sign extension, copy C to an + unsigned variable. */ + + if (!TOO_SMALL(count) && !UNALIGNED(s)) + { + /* If we get this far, we know that n is large and m is word-aligned. */ + aligned_addr = (unsigned long *)s; + + /* Store D into each char sized location in BUFFER so that + * we can set large blocks quickly. + */ + if (LBLOCKSIZE == 4) + { + buffer = (d << 8) | d; + buffer |= (buffer << 16); + } + else + { + buffer = 0; + for (i = 0; i < LBLOCKSIZE; i ++) + buffer = (buffer << 8) | d; + } + + while (count >= LBLOCKSIZE * 4) + { + *aligned_addr++ = buffer; + *aligned_addr++ = buffer; + *aligned_addr++ = buffer; + *aligned_addr++ = buffer; + count -= 4 * LBLOCKSIZE; + } + + while (count >= LBLOCKSIZE) + { + *aligned_addr++ = buffer; + count -= LBLOCKSIZE; + } + + /* Pick up the remainder with a bytewise loop. */ + m = (char *)aligned_addr; + } + + while (count--) + { + *m++ = (char)d; + } + + return s; + +#undef LBLOCKSIZE +#undef UNALIGNED +#undef TOO_SMALL +#endif +} +RTM_EXPORT(rt_memset); + +/** + * This function will copy memory content from source address to destination + * address. + * + * @param dst the address of destination memory + * @param src the address of source memory + * @param count the copied length + * + * @return the address of destination memory + */ +void *rt_memcpy(void *dst, const void *src, rt_ubase_t count) +{ +#ifdef RT_USING_TINY_SIZE + char *tmp = (char *)dst, *s = (char *)src; + rt_ubase_t len; + + if (tmp <= s || tmp > (s + count)) + { + while (count--) + *tmp ++ = *s ++; + } + else + { + for (len = count; len > 0; len --) + tmp[len - 1] = s[len - 1]; + } + + return dst; +#else + +#define UNALIGNED(X, Y) \ + (((long)X & (sizeof (long) - 1)) | ((long)Y & (sizeof (long) - 1))) +#define BIGBLOCKSIZE (sizeof (long) << 2) +#define LITTLEBLOCKSIZE (sizeof (long)) +#define TOO_SMALL(LEN) ((LEN) < BIGBLOCKSIZE) + + char *dst_ptr = (char *)dst; + char *src_ptr = (char *)src; + long *aligned_dst; + long *aligned_src; + int len = count; + + /* If the size is small, or either SRC or DST is unaligned, + then punt into the byte copy loop. This should be rare. */ + if (!TOO_SMALL(len) && !UNALIGNED(src_ptr, dst_ptr)) + { + aligned_dst = (long *)dst_ptr; + aligned_src = (long *)src_ptr; + + /* Copy 4X long words at a time if possible. */ + while (len >= BIGBLOCKSIZE) + { + *aligned_dst++ = *aligned_src++; + *aligned_dst++ = *aligned_src++; + *aligned_dst++ = *aligned_src++; + *aligned_dst++ = *aligned_src++; + len -= BIGBLOCKSIZE; + } + + /* Copy one long word at a time if possible. */ + while (len >= LITTLEBLOCKSIZE) + { + *aligned_dst++ = *aligned_src++; + len -= LITTLEBLOCKSIZE; + } + + /* Pick up any residual with a byte copier. */ + dst_ptr = (char *)aligned_dst; + src_ptr = (char *)aligned_src; + } + + while (len--) + *dst_ptr++ = *src_ptr++; + + return dst; +#undef UNALIGNED +#undef BIGBLOCKSIZE +#undef LITTLEBLOCKSIZE +#undef TOO_SMALL +#endif +} +RTM_EXPORT(rt_memcpy); + +/** + * This function will move memory content from source address to destination + * address. + * + * @param dest the address of destination memory + * @param src the address of source memory + * @param n the copied length + * + * @return the address of destination memory + */ +void *rt_memmove(void *dest, const void *src, rt_ubase_t n) +{ + char *tmp = (char *)dest, *s = (char *)src; + + if (s < tmp && tmp < s + n) + { + tmp += n; + s += n; + + while (n--) + *(--tmp) = *(--s); + } + else + { + while (n--) + *tmp++ = *s++; + } + + return dest; +} +RTM_EXPORT(rt_memmove); + +/** + * This function will compare two areas of memory + * + * @param cs one area of memory + * @param ct znother area of memory + * @param count the size of the area + * + * @return the result + */ +rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_ubase_t count) +{ + const unsigned char *su1, *su2; + int res = 0; + + for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + + return res; +} +RTM_EXPORT(rt_memcmp); + +/** + * This function will return the first occurrence of a string. + * + * @param s1 the source string + * @param s2 the find string + * + * @return the first occurrence of a s2 in s1, or RT_NULL if no found. + */ +char *rt_strstr(const char *s1, const char *s2) +{ + int l1, l2; + + l2 = rt_strlen(s2); + if (!l2) + return (char *)s1; + l1 = rt_strlen(s1); + while (l1 >= l2) + { + l1 --; + if (!rt_memcmp(s1, s2, l2)) + return (char *)s1; + s1 ++; + } + + return RT_NULL; +} +RTM_EXPORT(rt_strstr); + +/** + * This function will compare two strings while ignoring differences in case + * + * @param a the string to be compared + * @param b the string to be compared + * + * @return the result + */ +rt_uint32_t rt_strcasecmp(const char *a, const char *b) +{ + int ca, cb; + + do + { + ca = *a++ & 0xff; + cb = *b++ & 0xff; + if (ca >= 'A' && ca <= 'Z') + ca += 'a' - 'A'; + if (cb >= 'A' && cb <= 'Z') + cb += 'a' - 'A'; + } + while (ca == cb && ca != '\0'); + + return ca - cb; +} +RTM_EXPORT(rt_strcasecmp); + +/** + * This function will copy string no more than n bytes. + * + * @param dst the string to copy + * @param src the string to be copied + * @param n the maximum copied length + * + * @return the result + */ +char *rt_strncpy(char *dst, const char *src, rt_ubase_t n) +{ + if (n != 0) + { + char *d = dst; + const char *s = src; + + do + { + if ((*d++ = *s++) == 0) + { + /* NUL pad the remaining n-1 bytes */ + while (--n != 0) + *d++ = 0; + break; + } + } while (--n != 0); + } + + return (dst); +} +RTM_EXPORT(rt_strncpy); + +/** + * This function will compare two strings with specified maximum length + * + * @param cs the string to be compared + * @param ct the string to be compared + * @param count the maximum compare length + * + * @return the result + */ +rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_ubase_t count) +{ + register signed char __res = 0; + + while (count) + { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count --; + } + + return __res; +} +RTM_EXPORT(rt_strncmp); + +/** + * This function will compare two strings without specified length + * + * @param cs the string to be compared + * @param ct the string to be compared + * + * @return the result + */ +rt_int32_t rt_strcmp(const char *cs, const char *ct) +{ + while (*cs && *cs == *ct) + cs++, ct++; + + return (*cs - *ct); +} +RTM_EXPORT(rt_strcmp); + +/** + * The strnlen() function returns the number of characters in the + * string pointed to by s, excluding the terminating null byte ('\0'), + * but at most maxlen. In doing this, strnlen() looks only at the + * first maxlen characters in the string pointed to by s and never + * beyond s+maxlen. + * + * @param s the string + * @param maxlen the max size + * @return the length of string + */ +rt_size_t rt_strnlen(const char *s, rt_ubase_t maxlen) +{ + const char *sc; + + for (sc = s; *sc != '\0' && (rt_ubase_t)(sc - s) < maxlen; ++sc) /* nothing */ + ; + + return sc - s; +} +RTM_EXPORT(rt_strnlen); + +/** + * This function will return the length of a string, which terminate will + * null character. + * + * @param s the string + * + * @return the length of string + */ +rt_size_t rt_strlen(const char *s) +{ + const char *sc; + + for (sc = s; *sc != '\0'; ++sc) /* nothing */ + ; + + return sc - s; +} +RTM_EXPORT(rt_strlen); + +#ifdef RT_USING_HEAP +/** + * This function will duplicate a string. + * + * @param s the string to be duplicated + * + * @return the duplicated string pointer + */ +char *rt_strdup(const char *s) +{ + rt_size_t len = rt_strlen(s) + 1; + char *tmp = (char *)rt_malloc(len); + + if (!tmp) + return RT_NULL; + + rt_memcpy(tmp, s, len); + + return tmp; +} +RTM_EXPORT(rt_strdup); +#if defined(__CC_ARM) || defined(__CLANG_ARM) +char *strdup(const char *s) __attribute__((alias("rt_strdup"))); +#endif +#endif + +/** + * This function will show the version of rt-thread rtos + */ +void rt_show_version(void) +{ + rt_kprintf("\n \\ | /\n"); + rt_kprintf("- RT - Thread Operating System\n"); + rt_kprintf(" / | \\ %d.%d.%d build %s\n", + RT_VERSION, RT_SUBVERSION, RT_REVISION, __DATE__); + rt_kprintf(" 2006 - 2019 Copyright by rt-thread team\n"); +} +RTM_EXPORT(rt_show_version); + +/* private function */ +#define isdigit(c) ((unsigned)((c) - '0') < 10) + +#ifdef RT_PRINTF_LONGLONG +rt_inline int divide(long long *n, int base) +{ + int res; + + /* optimized for processor which does not support divide instructions. */ + if (base == 10) + { + res = (int)(((unsigned long long)*n) % 10U); + *n = (long long)(((unsigned long long)*n) / 10U); + } + else + { + res = (int)(((unsigned long long)*n) % 16U); + *n = (long long)(((unsigned long long)*n) / 16U); + } + + return res; +} +#else +rt_inline int divide(long *n, int base) +{ + int res; + + /* optimized for processor which does not support divide instructions. */ + if (base == 10) + { + res = (int)(((unsigned long)*n) % 10U); + *n = (long)(((unsigned long)*n) / 10U); + } + else + { + res = (int)(((unsigned long)*n) % 16U); + *n = (long)(((unsigned long)*n) / 16U); + } + + return res; +} +#endif + +rt_inline int skip_atoi(const char **s) +{ + register int i = 0; + while (isdigit(**s)) + i = i * 10 + *((*s)++) - '0'; + + return i; +} + +#define ZEROPAD (1 << 0) /* pad with zero */ +#define SIGN (1 << 1) /* unsigned/signed long */ +#define PLUS (1 << 2) /* show plus */ +#define SPACE (1 << 3) /* space if plus */ +#define LEFT (1 << 4) /* left justified */ +#define SPECIAL (1 << 5) /* 0x */ +#define LARGE (1 << 6) /* use 'ABCDEF' instead of 'abcdef' */ + +#ifdef RT_PRINTF_PRECISION +static char *print_number(char *buf, + char *end, +#ifdef RT_PRINTF_LONGLONG + long long num, +#else + long num, +#endif + int base, + int s, + int precision, + int type) +#else +static char *print_number(char *buf, + char *end, +#ifdef RT_PRINTF_LONGLONG + long long num, +#else + long num, +#endif + int base, + int s, + int type) +#endif +{ + char c, sign; +#ifdef RT_PRINTF_LONGLONG + char tmp[32]; +#else + char tmp[16]; +#endif + int precision_bak = precision; + const char *digits; + static const char small_digits[] = "0123456789abcdef"; + static const char large_digits[] = "0123456789ABCDEF"; + register int i; + register int size; + + size = s; + + digits = (type & LARGE) ? large_digits : small_digits; + if (type & LEFT) + type &= ~ZEROPAD; + + c = (type & ZEROPAD) ? '0' : ' '; + + /* get sign */ + sign = 0; + if (type & SIGN) + { + if (num < 0) + { + sign = '-'; + num = -num; + } + else if (type & PLUS) + sign = '+'; + else if (type & SPACE) + sign = ' '; + } + +#ifdef RT_PRINTF_SPECIAL + if (type & SPECIAL) + { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } +#endif + + i = 0; + if (num == 0) + tmp[i++] = '0'; + else + { + while (num != 0) + tmp[i++] = digits[divide(&num, base)]; + } + +#ifdef RT_PRINTF_PRECISION + if (i > precision) + precision = i; + size -= precision; +#else + size -= i; +#endif + + if (!(type & (ZEROPAD | LEFT))) + { + if ((sign) && (size > 0)) + size--; + + while (size-- > 0) + { + if (buf < end) + *buf = ' '; + ++ buf; + } + } + + if (sign) + { + if (buf < end) + { + *buf = sign; + } + -- size; + ++ buf; + } + +#ifdef RT_PRINTF_SPECIAL + if (type & SPECIAL) + { + if (base == 8) + { + if (buf < end) + *buf = '0'; + ++ buf; + } + else if (base == 16) + { + if (buf < end) + *buf = '0'; + ++ buf; + if (buf < end) + { + *buf = type & LARGE ? 'X' : 'x'; + } + ++ buf; + } + } +#endif + + /* no align to the left */ + if (!(type & LEFT)) + { + while (size-- > 0) + { + if (buf < end) + *buf = c; + ++ buf; + } + } + +#ifdef RT_PRINTF_PRECISION + while (i < precision--) + { + if (buf < end) + *buf = '0'; + ++ buf; + } +#endif + + /* put number in the temporary buffer */ + while (i-- > 0 && (precision_bak != 0)) + { + if (buf < end) + *buf = tmp[i]; + ++ buf; + } + + while (size-- > 0) + { + if (buf < end) + *buf = ' '; + ++ buf; + } + + return buf; +} + +rt_int32_t rt_vsnprintf(char *buf, + rt_size_t size, + const char *fmt, + va_list args) +{ +#ifdef RT_PRINTF_LONGLONG + unsigned long long num; +#else + rt_uint32_t num; +#endif + int i, len; + char *str, *end, c; + const char *s; + + rt_uint8_t base; /* the base of number */ + rt_uint8_t flags; /* flags to print number */ + rt_uint8_t qualifier; /* 'h', 'l', or 'L' for integer fields */ + rt_int32_t field_width; /* width of output field */ + +#ifdef RT_PRINTF_PRECISION + int precision; /* min. # of digits for integers and max for a string */ +#endif + + str = buf; + end = buf + size; + + /* Make sure end is always >= buf */ + if (end < buf) + { + end = ((char *) - 1); + size = end - buf; + } + + for (; *fmt ; ++fmt) + { + if (*fmt != '%') + { + if (str < end) + *str = *fmt; + ++ str; + continue; + } + + /* process flags */ + flags = 0; + + while (1) + { + /* skips the first '%' also */ + ++ fmt; + if (*fmt == '-') flags |= LEFT; + else if (*fmt == '+') flags |= PLUS; + else if (*fmt == ' ') flags |= SPACE; + else if (*fmt == '#') flags |= SPECIAL; + else if (*fmt == '0') flags |= ZEROPAD; + else break; + } + + /* get field width */ + field_width = -1; + if (isdigit(*fmt)) field_width = skip_atoi(&fmt); + else if (*fmt == '*') + { + ++ fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) + { + field_width = -field_width; + flags |= LEFT; + } + } + +#ifdef RT_PRINTF_PRECISION + /* get the precision */ + precision = -1; + if (*fmt == '.') + { + ++ fmt; + if (isdigit(*fmt)) precision = skip_atoi(&fmt); + else if (*fmt == '*') + { + ++ fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) precision = 0; + } +#endif + /* get the conversion qualifier */ + qualifier = 0; +#ifdef RT_PRINTF_LONGLONG + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') +#else + if (*fmt == 'h' || *fmt == 'l') +#endif + { + qualifier = *fmt; + ++ fmt; +#ifdef RT_PRINTF_LONGLONG + if (qualifier == 'l' && *fmt == 'l') + { + qualifier = 'L'; + ++ fmt; + } +#endif + } + + /* the default base */ + base = 10; + + switch (*fmt) + { + case 'c': + if (!(flags & LEFT)) + { + while (--field_width > 0) + { + if (str < end) *str = ' '; + ++ str; + } + } + + /* get character */ + c = (rt_uint8_t)va_arg(args, int); + if (str < end) *str = c; + ++ str; + + /* put width */ + while (--field_width > 0) + { + if (str < end) *str = ' '; + ++ str; + } + continue; + + case 's': + s = va_arg(args, char *); + if (!s) s = "(NULL)"; + + len = rt_strlen(s); +#ifdef RT_PRINTF_PRECISION + if (precision > 0 && len > precision) len = precision; +#endif + + if (!(flags & LEFT)) + { + while (len < field_width--) + { + if (str < end) *str = ' '; + ++ str; + } + } + + for (i = 0; i < len; ++i) + { + if (str < end) *str = *s; + ++ str; + ++ s; + } + + while (len < field_width--) + { + if (str < end) *str = ' '; + ++ str; + } + continue; + + case 'p': + if (field_width == -1) + { + field_width = sizeof(void *) << 1; + flags |= ZEROPAD; + } +#ifdef RT_PRINTF_PRECISION + str = print_number(str, end, + (long)va_arg(args, void *), + 16, field_width, precision, flags); +#else + str = print_number(str, end, + (long)va_arg(args, void *), + 16, field_width, flags); +#endif + continue; + + case '%': + if (str < end) *str = '%'; + ++ str; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + if (str < end) *str = '%'; + ++ str; + + if (*fmt) + { + if (str < end) *str = *fmt; + ++ str; + } + else + { + -- fmt; + } + continue; + } + +#ifdef RT_PRINTF_LONGLONG + if (qualifier == 'L') num = va_arg(args, long long); + else if (qualifier == 'l') +#else + if (qualifier == 'l') +#endif + { + num = va_arg(args, rt_uint32_t); + if (flags & SIGN) num = (rt_int32_t)num; + } + else if (qualifier == 'h') + { + num = (rt_uint16_t)va_arg(args, rt_int32_t); + if (flags & SIGN) num = (rt_int16_t)num; + } + else + { + num = va_arg(args, rt_uint32_t); + if (flags & SIGN) num = (rt_int32_t)num; + } +#ifdef RT_PRINTF_PRECISION + str = print_number(str, end, num, base, field_width, precision, flags); +#else + str = print_number(str, end, num, base, field_width, flags); +#endif + } + + if (size > 0) + { + if (str < end) *str = '\0'; + else + { + end[-1] = '\0'; + } + } + + /* the trailing null byte doesn't count towards the total + * ++str; + */ + return str - buf; +} +RTM_EXPORT(rt_vsnprintf); + +/** + * This function will fill a formatted string to buffer + * + * @param buf the buffer to save formatted string + * @param size the size of buffer + * @param fmt the format + */ +rt_int32_t rt_snprintf(char *buf, rt_size_t size, const char *fmt, ...) +{ + rt_int32_t n; + va_list args; + + va_start(args, fmt); + n = rt_vsnprintf(buf, size, fmt, args); + va_end(args); + + return n; +} +RTM_EXPORT(rt_snprintf); + +/** + * This function will fill a formatted string to buffer + * + * @param buf the buffer to save formatted string + * @param arg_ptr the arg_ptr + * @param format the format + */ +rt_int32_t rt_vsprintf(char *buf, const char *format, va_list arg_ptr) +{ + return rt_vsnprintf(buf, (rt_size_t) - 1, format, arg_ptr); +} +RTM_EXPORT(rt_vsprintf); + +/** + * This function will fill a formatted string to buffer + * + * @param buf the buffer to save formatted string + * @param format the format + */ +rt_int32_t rt_sprintf(char *buf, const char *format, ...) +{ + rt_int32_t n; + va_list arg_ptr; + + va_start(arg_ptr, format); + n = rt_vsprintf(buf, format, arg_ptr); + va_end(arg_ptr); + + return n; +} +RTM_EXPORT(rt_sprintf); + +#ifdef RT_USING_CONSOLE + +#ifdef RT_USING_DEVICE +/** + * This function returns the device using in console. + * + * @return the device using in console or RT_NULL + */ +rt_device_t rt_console_get_device(void) +{ + return _console_device; +} +RTM_EXPORT(rt_console_get_device); + +/** + * This function will set a device as console device. + * After set a device to console, all output of rt_kprintf will be + * redirected to this new device. + * + * @param name the name of new console device + * + * @return the old console device handler + */ +rt_device_t rt_console_set_device(const char *name) +{ + rt_device_t new, old; + + /* save old device */ + old = _console_device; + + /* find new console device */ + new = rt_device_find(name); + if (new != RT_NULL) + { + if (_console_device != RT_NULL) + { + /* close old console device */ + rt_device_close(_console_device); + } + + /* set new console device */ + rt_device_open(new, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM); + _console_device = new; + } + + return old; +} +RTM_EXPORT(rt_console_set_device); +#endif + +RT_WEAK void rt_hw_console_output(const char *str) +{ + /* empty console output */ +} +RTM_EXPORT(rt_hw_console_output); + +/** + * This function will put string to the console. + * + * @param str the string output to the console. + */ +void rt_kputs(const char *str) +{ + if (!str) return; + +#ifdef RT_USING_DEVICE + if (_console_device == RT_NULL) + { + rt_hw_console_output(str); + } + else + { + rt_uint16_t old_flag = _console_device->open_flag; + + _console_device->open_flag |= RT_DEVICE_FLAG_STREAM; + rt_device_write(_console_device, 0, str, rt_strlen(str)); + _console_device->open_flag = old_flag; + } +#else + rt_hw_console_output(str); +#endif +} + +/** + * This function will print a formatted string on system console + * + * @param fmt the format + */ +void rt_kprintf(const char *fmt, ...) +{ + va_list args; + rt_size_t length; + static char rt_log_buf[RT_CONSOLEBUF_SIZE]; + + va_start(args, fmt); + /* the return value of vsnprintf is the number of bytes that would be + * written to buffer had if the size of the buffer been sufficiently + * large excluding the terminating null byte. If the output string + * would be larger than the rt_log_buf, we have to adjust the output + * length. */ + length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); + if (length > RT_CONSOLEBUF_SIZE - 1) + length = RT_CONSOLEBUF_SIZE - 1; +#ifdef RT_USING_DEVICE + if (_console_device == RT_NULL) + { + rt_hw_console_output(rt_log_buf); + } + else + { + rt_uint16_t old_flag = _console_device->open_flag; + + _console_device->open_flag |= RT_DEVICE_FLAG_STREAM; + rt_device_write(_console_device, 0, rt_log_buf, length); + _console_device->open_flag = old_flag; + } +#else + rt_hw_console_output(rt_log_buf); +#endif + va_end(args); +} +RTM_EXPORT(rt_kprintf); +#endif + +#ifdef RT_USING_HEAP +/** + * This function allocates a memory block, which address is aligned to the + * specified alignment size. + * + * @param size the allocated memory block size + * @param align the alignment size + * + * @return the allocated memory block on successful, otherwise returns RT_NULL + */ +void *rt_malloc_align(rt_size_t size, rt_size_t align) +{ + void *align_ptr; + void *ptr; + rt_size_t align_size; + + /* align the alignment size to 4 byte */ + align = ((align + 0x03) & ~0x03); + + /* get total aligned size */ + align_size = ((size + 0x03) & ~0x03) + align; + /* allocate memory block from heap */ + ptr = rt_malloc(align_size); + if (ptr != RT_NULL) + { + /* the allocated memory block is aligned */ + if (((rt_uint32_t)ptr & (align - 1)) == 0) + { + align_ptr = (void *)((rt_uint32_t)ptr + align); + } + else + { + align_ptr = (void *)(((rt_uint32_t)ptr + (align - 1)) & ~(align - 1)); + } + + /* set the pointer before alignment pointer to the real pointer */ + *((rt_uint32_t *)((rt_uint32_t)align_ptr - sizeof(void *))) = (rt_uint32_t)ptr; + + ptr = align_ptr; + } + + return ptr; +} +RTM_EXPORT(rt_malloc_align); + +/** + * This function release the memory block, which is allocated by + * rt_malloc_align function and address is aligned. + * + * @param ptr the memory block pointer + */ +void rt_free_align(void *ptr) +{ + void *real_ptr; + + real_ptr = (void *) * (rt_uint32_t *)((rt_uint32_t)ptr - sizeof(void *)); + rt_free(real_ptr); +} +RTM_EXPORT(rt_free_align); +#endif + +#ifndef RT_USING_CPU_FFS +const rt_uint8_t __lowest_bit_bitmap[] = +{ + /* 00 */ 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 10 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 20 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 30 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 40 */ 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 50 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 60 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 70 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 80 */ 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 90 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* A0 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* B0 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* C0 */ 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* D0 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* E0 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* F0 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 +}; + +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +int __rt_ffs(int value) +{ + if (value == 0) return 0; + + if (value & 0xff) + return __lowest_bit_bitmap[value & 0xff] + 1; + + if (value & 0xff00) + return __lowest_bit_bitmap[(value & 0xff00) >> 8] + 9; + + if (value & 0xff0000) + return __lowest_bit_bitmap[(value & 0xff0000) >> 16] + 17; + + return __lowest_bit_bitmap[(value & 0xff000000) >> 24] + 25; +} +#endif + +#ifdef RT_DEBUG +/* RT_ASSERT(EX)'s hook */ +void (*rt_assert_hook)(const char *ex, const char *func, rt_size_t line); +/** + * This function will set a hook function to RT_ASSERT(EX). It will run when the expression is false. + * + * @param hook the hook function + */ +void rt_assert_set_hook(void (*hook)(const char *ex, const char *func, rt_size_t line)) +{ + rt_assert_hook = hook; +} + +/** + * The RT_ASSERT function. + * + * @param ex the assertion condition string + * @param func the function name when assertion. + * @param line the file line number when assertion. + */ +void rt_assert_handler(const char *ex_string, const char *func, rt_size_t line) +{ + volatile char dummy = 0; + + if (rt_assert_hook == RT_NULL) + { +#ifdef RT_USING_MODULE + if (dlmodule_self()) + { + /* close assertion module */ + dlmodule_exit(-1); + } + else +#endif + { + rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line); + while (dummy == 0); + } + } + else + { + rt_assert_hook(ex_string, func, line); + } +} +RTM_EXPORT(rt_assert_handler); +#endif /* RT_DEBUG */ + +#if !defined (RT_USING_NEWLIB) && defined (RT_USING_MINILIBC) && defined (__GNUC__) +#include +void *memcpy(void *dest, const void *src, size_t n) __attribute__((weak, alias("rt_memcpy"))); +void *memset(void *s, int c, size_t n) __attribute__((weak, alias("rt_memset"))); +void *memmove(void *dest, const void *src, size_t n) __attribute__((weak, alias("rt_memmove"))); +int memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("rt_memcmp"))); + +size_t strlen(const char *s) __attribute__((weak, alias("rt_strlen"))); +char *strstr(const char *s1, const char *s2) __attribute__((weak, alias("rt_strstr"))); +int strcasecmp(const char *a, const char *b) __attribute__((weak, alias("rt_strcasecmp"))); +char *strncpy(char *dest, const char *src, size_t n) __attribute__((weak, alias("rt_strncpy"))); +int strncmp(const char *cs, const char *ct, size_t count) __attribute__((weak, alias("rt_strncmp"))); +#ifdef RT_USING_HEAP +char *strdup(const char *s) __attribute__((weak, alias("rt_strdup"))); +#endif + +int sprintf(char *buf, const char *format, ...) __attribute__((weak, alias("rt_sprintf"))); +int snprintf(char *buf, rt_size_t size, const char *fmt, ...) __attribute__((weak, alias("rt_snprintf"))); +int vsprintf(char *buf, const char *format, va_list arg_ptr) __attribute__((weak, alias("rt_vsprintf"))); + +#endif + +/**@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/mem.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/mem.c new file mode 100644 index 0000000000..2fefb48b67 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/mem.c @@ -0,0 +1,698 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2008-7-12 Bernard the first version + * 2010-06-09 Bernard fix the end stub of heap + * fix memory check in rt_realloc function + * 2010-07-13 Bernard fix RT_ALIGN issue found by kuronca + * 2010-10-14 Bernard fix rt_realloc issue when realloc a NULL pointer. + * 2017-07-14 armink fix rt_realloc issue when new size is 0 + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ + +#include +#include + +#ifndef RT_USING_MEMHEAP_AS_HEAP + +/* #define RT_MEM_DEBUG */ +#define RT_MEM_STATS + +#if defined (RT_USING_HEAP) && defined (RT_USING_SMALL_MEM) +#ifdef RT_USING_HOOK +static void (*rt_malloc_hook)(void *ptr, rt_size_t size); +static void (*rt_free_hook)(void *ptr); + +/** + * @addtogroup Hook + */ + +/**@{*/ + +/** + * This function will set a hook function, which will be invoked when a memory + * block is allocated from heap memory. + * + * @param hook the hook function + */ +void rt_malloc_sethook(void (*hook)(void *ptr, rt_size_t size)) +{ + rt_malloc_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when a memory + * block is released to heap memory. + * + * @param hook the hook function + */ +void rt_free_sethook(void (*hook)(void *ptr)) +{ + rt_free_hook = hook; +} + +/**@}*/ + +#endif + +#define HEAP_MAGIC 0x1ea0 +struct heap_mem +{ + /* magic and used flag */ + rt_uint16_t magic; + rt_uint16_t used; + + rt_size_t next, prev; + +#ifdef RT_USING_MEMTRACE + rt_uint8_t thread[4]; /* thread name */ +#endif +}; + +/** pointer to the heap: for alignment, heap_ptr is now a pointer instead of an array */ +static rt_uint8_t *heap_ptr; + +/** the last entry, always unused! */ +static struct heap_mem *heap_end; + +#define MIN_SIZE 12 +#define MIN_SIZE_ALIGNED RT_ALIGN(MIN_SIZE, RT_ALIGN_SIZE) +#define SIZEOF_STRUCT_MEM RT_ALIGN(sizeof(struct heap_mem), RT_ALIGN_SIZE) + +static struct heap_mem *lfree; /* pointer to the lowest free block */ + +static struct rt_semaphore heap_sem; +static rt_size_t mem_size_aligned; + +#ifdef RT_MEM_STATS +static rt_size_t used_mem, max_mem; +#endif +#ifdef RT_USING_MEMTRACE +rt_inline void rt_mem_setname(struct heap_mem *mem, const char *name) +{ + int index; + for (index = 0; index < sizeof(mem->thread); index ++) + { + if (name[index] == '\0') break; + mem->thread[index] = name[index]; + } + + for (; index < sizeof(mem->thread); index ++) + { + mem->thread[index] = ' '; + } +} +#endif + +static void plug_holes(struct heap_mem *mem) +{ + struct heap_mem *nmem; + struct heap_mem *pmem; + + RT_ASSERT((rt_uint8_t *)mem >= heap_ptr); + RT_ASSERT((rt_uint8_t *)mem < (rt_uint8_t *)heap_end); + RT_ASSERT(mem->used == 0); + + /* plug hole forward */ + nmem = (struct heap_mem *)&heap_ptr[mem->next]; + if (mem != nmem && + nmem->used == 0 && + (rt_uint8_t *)nmem != (rt_uint8_t *)heap_end) + { + /* if mem->next is unused and not end of heap_ptr, + * combine mem and mem->next + */ + if (lfree == nmem) + { + lfree = mem; + } + mem->next = nmem->next; + ((struct heap_mem *)&heap_ptr[nmem->next])->prev = (rt_uint8_t *)mem - heap_ptr; + } + + /* plug hole backward */ + pmem = (struct heap_mem *)&heap_ptr[mem->prev]; + if (pmem != mem && pmem->used == 0) + { + /* if mem->prev is unused, combine mem and mem->prev */ + if (lfree == mem) + { + lfree = pmem; + } + pmem->next = mem->next; + ((struct heap_mem *)&heap_ptr[mem->next])->prev = (rt_uint8_t *)pmem - heap_ptr; + } +} + +/** + * @ingroup SystemInit + * + * This function will initialize system heap memory. + * + * @param begin_addr the beginning address of system heap memory. + * @param end_addr the end address of system heap memory. + */ +void rt_system_heap_init(void *begin_addr, void *end_addr) +{ + struct heap_mem *mem; + rt_uint32_t begin_align = RT_ALIGN((rt_uint32_t)begin_addr, RT_ALIGN_SIZE); + rt_uint32_t end_align = RT_ALIGN_DOWN((rt_uint32_t)end_addr, RT_ALIGN_SIZE); + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* alignment addr */ + if ((end_align > (2 * SIZEOF_STRUCT_MEM)) && + ((end_align - 2 * SIZEOF_STRUCT_MEM) >= begin_align)) + { + /* calculate the aligned memory size */ + mem_size_aligned = end_align - begin_align - 2 * SIZEOF_STRUCT_MEM; + } + else + { + rt_kprintf("mem init, error begin address 0x%x, and end address 0x%x\n", + (rt_uint32_t)begin_addr, (rt_uint32_t)end_addr); + + return; + } + + /* point to begin address of heap */ + heap_ptr = (rt_uint8_t *)begin_align; + + RT_DEBUG_LOG(RT_DEBUG_MEM, ("mem init, heap begin address 0x%x, size %d\n", + (rt_uint32_t)heap_ptr, mem_size_aligned)); + + /* initialize the start of the heap */ + mem = (struct heap_mem *)heap_ptr; + mem->magic = HEAP_MAGIC; + mem->next = mem_size_aligned + SIZEOF_STRUCT_MEM; + mem->prev = 0; + mem->used = 0; +#ifdef RT_USING_MEMTRACE + rt_mem_setname(mem, "INIT"); +#endif + + /* initialize the end of the heap */ + heap_end = (struct heap_mem *)&heap_ptr[mem->next]; + heap_end->magic = HEAP_MAGIC; + heap_end->used = 1; + heap_end->next = mem_size_aligned + SIZEOF_STRUCT_MEM; + heap_end->prev = mem_size_aligned + SIZEOF_STRUCT_MEM; +#ifdef RT_USING_MEMTRACE + rt_mem_setname(heap_end, "INIT"); +#endif + + rt_sem_init(&heap_sem, "heap", 1, RT_IPC_FLAG_FIFO); + + /* initialize the lowest-free pointer to the start of the heap */ + lfree = (struct heap_mem *)heap_ptr; +} + +/** + * @addtogroup MM + */ + +/**@{*/ + +/** + * Allocate a block of memory with a minimum of 'size' bytes. + * + * @param size is the minimum size of the requested block in bytes. + * + * @return pointer to allocated memory or NULL if no free memory was found. + */ +void *rt_malloc(rt_size_t size) +{ + rt_size_t ptr, ptr2; + struct heap_mem *mem, *mem2; + + if (size == 0) + return RT_NULL; + + RT_DEBUG_NOT_IN_INTERRUPT; + + if (size != RT_ALIGN(size, RT_ALIGN_SIZE)) + RT_DEBUG_LOG(RT_DEBUG_MEM, ("malloc size %d, but align to %d\n", + size, RT_ALIGN(size, RT_ALIGN_SIZE))); + else + RT_DEBUG_LOG(RT_DEBUG_MEM, ("malloc size %d\n", size)); + + /* alignment size */ + size = RT_ALIGN(size, RT_ALIGN_SIZE); + + if (size > mem_size_aligned) + { + RT_DEBUG_LOG(RT_DEBUG_MEM, ("no memory\n")); + + return RT_NULL; + } + + /* every data block must be at least MIN_SIZE_ALIGNED long */ + if (size < MIN_SIZE_ALIGNED) + size = MIN_SIZE_ALIGNED; + + /* take memory semaphore */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + for (ptr = (rt_uint8_t *)lfree - heap_ptr; + ptr < mem_size_aligned - size; + ptr = ((struct heap_mem *)&heap_ptr[ptr])->next) + { + mem = (struct heap_mem *)&heap_ptr[ptr]; + + if ((!mem->used) && (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) + { + /* mem is not used and at least perfect fit is possible: + * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ + + if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= + (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) + { + /* (in addition to the above, we test if another struct heap_mem (SIZEOF_STRUCT_MEM) containing + * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem') + * -> split large block, create empty remainder, + * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if + * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size, + * struct heap_mem would fit in but no data between mem2 and mem2->next + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory + */ + ptr2 = ptr + SIZEOF_STRUCT_MEM + size; + + /* create mem2 struct */ + mem2 = (struct heap_mem *)&heap_ptr[ptr2]; + mem2->magic = HEAP_MAGIC; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; +#ifdef RT_USING_MEMTRACE + rt_mem_setname(mem2, " "); +#endif + + /* and insert it between mem and mem->next */ + mem->next = ptr2; + mem->used = 1; + + if (mem2->next != mem_size_aligned + SIZEOF_STRUCT_MEM) + { + ((struct heap_mem *)&heap_ptr[mem2->next])->prev = ptr2; + } +#ifdef RT_MEM_STATS + used_mem += (size + SIZEOF_STRUCT_MEM); + if (max_mem < used_mem) + max_mem = used_mem; +#endif + } + else + { + /* (a mem2 struct does no fit into the user data space of mem and mem->next will always + * be used at this point: if not we have 2 unused structs in a row, plug_holes should have + * take care of this). + * -> near fit or excact fit: do not split, no mem2 creation + * also can't move mem->next directly behind mem, since mem->next + * will always be used at this point! + */ + mem->used = 1; +#ifdef RT_MEM_STATS + used_mem += mem->next - ((rt_uint8_t *)mem - heap_ptr); + if (max_mem < used_mem) + max_mem = used_mem; +#endif + } + /* set memory block magic */ + mem->magic = HEAP_MAGIC; +#ifdef RT_USING_MEMTRACE + if (rt_thread_self()) + rt_mem_setname(mem, rt_thread_self()->name); + else + rt_mem_setname(mem, "NONE"); +#endif + + if (mem == lfree) + { + /* Find next free block after mem and update lowest free pointer */ + while (lfree->used && lfree != heap_end) + lfree = (struct heap_mem *)&heap_ptr[lfree->next]; + + RT_ASSERT(((lfree == heap_end) || (!lfree->used))); + } + + rt_sem_release(&heap_sem); + RT_ASSERT((rt_uint32_t)mem + SIZEOF_STRUCT_MEM + size <= (rt_uint32_t)heap_end); + RT_ASSERT((rt_uint32_t)((rt_uint8_t *)mem + SIZEOF_STRUCT_MEM) % RT_ALIGN_SIZE == 0); + RT_ASSERT((((rt_uint32_t)mem) & (RT_ALIGN_SIZE - 1)) == 0); + + RT_DEBUG_LOG(RT_DEBUG_MEM, + ("allocate memory at 0x%x, size: %d\n", + (rt_uint32_t)((rt_uint8_t *)mem + SIZEOF_STRUCT_MEM), + (rt_uint32_t)(mem->next - ((rt_uint8_t *)mem - heap_ptr)))); + + RT_OBJECT_HOOK_CALL(rt_malloc_hook, + (((void *)((rt_uint8_t *)mem + SIZEOF_STRUCT_MEM)), size)); + + /* return the memory data except mem struct */ + return (rt_uint8_t *)mem + SIZEOF_STRUCT_MEM; + } + } + + rt_sem_release(&heap_sem); + + return RT_NULL; +} +RTM_EXPORT(rt_malloc); + +/** + * This function will change the previously allocated memory block. + * + * @param rmem pointer to memory allocated by rt_malloc + * @param newsize the required new size + * + * @return the changed memory block address + */ +void *rt_realloc(void *rmem, rt_size_t newsize) +{ + rt_size_t size; + rt_size_t ptr, ptr2; + struct heap_mem *mem, *mem2; + void *nmem; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* alignment size */ + newsize = RT_ALIGN(newsize, RT_ALIGN_SIZE); + if (newsize > mem_size_aligned) + { + RT_DEBUG_LOG(RT_DEBUG_MEM, ("realloc: out of memory\n")); + + return RT_NULL; + } + else if (newsize == 0) + { + rt_free(rmem); + return RT_NULL; + } + + /* allocate a new memory block */ + if (rmem == RT_NULL) + return rt_malloc(newsize); + + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + if ((rt_uint8_t *)rmem < (rt_uint8_t *)heap_ptr || + (rt_uint8_t *)rmem >= (rt_uint8_t *)heap_end) + { + /* illegal memory */ + rt_sem_release(&heap_sem); + + return rmem; + } + + mem = (struct heap_mem *)((rt_uint8_t *)rmem - SIZEOF_STRUCT_MEM); + + ptr = (rt_uint8_t *)mem - heap_ptr; + size = mem->next - ptr - SIZEOF_STRUCT_MEM; + if (size == newsize) + { + /* the size is the same as */ + rt_sem_release(&heap_sem); + + return rmem; + } + + if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) + { + /* split memory block */ +#ifdef RT_MEM_STATS + used_mem -= (size - newsize); +#endif + + ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; + mem2 = (struct heap_mem *)&heap_ptr[ptr2]; + mem2->magic = HEAP_MAGIC; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; +#ifdef RT_USING_MEMTRACE + rt_mem_setname(mem2, " "); +#endif + mem->next = ptr2; + if (mem2->next != mem_size_aligned + SIZEOF_STRUCT_MEM) + { + ((struct heap_mem *)&heap_ptr[mem2->next])->prev = ptr2; + } + + plug_holes(mem2); + + rt_sem_release(&heap_sem); + + return rmem; + } + rt_sem_release(&heap_sem); + + /* expand memory */ + nmem = rt_malloc(newsize); + if (nmem != RT_NULL) /* check memory */ + { + rt_memcpy(nmem, rmem, size < newsize ? size : newsize); + rt_free(rmem); + } + + return nmem; +} +RTM_EXPORT(rt_realloc); + +/** + * This function will contiguously allocate enough space for count objects + * that are size bytes of memory each and returns a pointer to the allocated + * memory. + * + * The allocated memory is filled with bytes of value zero. + * + * @param count number of objects to allocate + * @param size size of the objects to allocate + * + * @return pointer to allocated memory / NULL pointer if there is an error + */ +void *rt_calloc(rt_size_t count, rt_size_t size) +{ + void *p; + + /* allocate 'count' objects of size 'size' */ + p = rt_malloc(count * size); + + /* zero the memory */ + if (p) + rt_memset(p, 0, count * size); + + return p; +} +RTM_EXPORT(rt_calloc); + +/** + * This function will release the previously allocated memory block by + * rt_malloc. The released memory block is taken back to system heap. + * + * @param rmem the address of memory which will be released + */ +void rt_free(void *rmem) +{ + struct heap_mem *mem; + + if (rmem == RT_NULL) + return; + + RT_DEBUG_NOT_IN_INTERRUPT; + + RT_ASSERT((((rt_uint32_t)rmem) & (RT_ALIGN_SIZE - 1)) == 0); + RT_ASSERT((rt_uint8_t *)rmem >= (rt_uint8_t *)heap_ptr && + (rt_uint8_t *)rmem < (rt_uint8_t *)heap_end); + + RT_OBJECT_HOOK_CALL(rt_free_hook, (rmem)); + + if ((rt_uint8_t *)rmem < (rt_uint8_t *)heap_ptr || + (rt_uint8_t *)rmem >= (rt_uint8_t *)heap_end) + { + RT_DEBUG_LOG(RT_DEBUG_MEM, ("illegal memory\n")); + + return; + } + + /* Get the corresponding struct heap_mem ... */ + mem = (struct heap_mem *)((rt_uint8_t *)rmem - SIZEOF_STRUCT_MEM); + + RT_DEBUG_LOG(RT_DEBUG_MEM, + ("release memory 0x%x, size: %d\n", + (rt_uint32_t)rmem, + (rt_uint32_t)(mem->next - ((rt_uint8_t *)mem - heap_ptr)))); + + + /* protect the heap from concurrent access */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + /* ... which has to be in a used state ... */ + if (!mem->used || mem->magic != HEAP_MAGIC) + { + rt_kprintf("to free a bad data block:\n"); + rt_kprintf("mem: 0x%08x, used flag: %d, magic code: 0x%04x\n", mem, mem->used, mem->magic); + } + RT_ASSERT(mem->used); + RT_ASSERT(mem->magic == HEAP_MAGIC); + /* ... and is now unused. */ + mem->used = 0; + mem->magic = HEAP_MAGIC; +#ifdef RT_USING_MEMTRACE + rt_mem_setname(mem, " "); +#endif + + if (mem < lfree) + { + /* the newly freed struct is now the lowest */ + lfree = mem; + } + +#ifdef RT_MEM_STATS + used_mem -= (mem->next - ((rt_uint8_t *)mem - heap_ptr)); +#endif + + /* finally, see if prev or next are free also */ + plug_holes(mem); + rt_sem_release(&heap_sem); +} +RTM_EXPORT(rt_free); + +#ifdef RT_MEM_STATS +void rt_memory_info(rt_uint32_t *total, + rt_uint32_t *used, + rt_uint32_t *max_used) +{ + if (total != RT_NULL) + *total = mem_size_aligned; + if (used != RT_NULL) + *used = used_mem; + if (max_used != RT_NULL) + *max_used = max_mem; +} + +#ifdef RT_USING_FINSH +#include + +void list_mem(void) +{ + rt_kprintf("total memory: %d\n", mem_size_aligned); + rt_kprintf("used memory : %d\n", used_mem); + rt_kprintf("maximum allocated memory: %d\n", max_mem); +} +FINSH_FUNCTION_EXPORT(list_mem, list memory usage information) + +#ifdef RT_USING_MEMTRACE +int memcheck(void) +{ + int position; + rt_uint32_t level; + struct heap_mem *mem; + level = rt_hw_interrupt_disable(); + for (mem = (struct heap_mem *)heap_ptr; mem != heap_end; mem = (struct heap_mem *)&heap_ptr[mem->next]) + { + position = (rt_uint32_t)mem - (rt_uint32_t)heap_ptr; + if (position < 0) goto __exit; + if (position > mem_size_aligned) goto __exit; + if (mem->magic != HEAP_MAGIC) goto __exit; + if (mem->used != 0 && mem->used != 1) goto __exit; + } + rt_hw_interrupt_enable(level); + + return 0; +__exit: + rt_kprintf("Memory block wrong:\n"); + rt_kprintf("address: 0x%08x\n", mem); + rt_kprintf(" magic: 0x%04x\n", mem->magic); + rt_kprintf(" used: %d\n", mem->used); + rt_kprintf(" size: %d\n", mem->next - position - SIZEOF_STRUCT_MEM); + rt_hw_interrupt_enable(level); + + return 0; +} +MSH_CMD_EXPORT(memcheck, check memory data); + +int memtrace(int argc, char **argv) +{ + struct heap_mem *mem; + + list_mem(); + + rt_kprintf("\nmemory heap address:\n"); + rt_kprintf("heap_ptr: 0x%08x\n", heap_ptr); + rt_kprintf("lfree : 0x%08x\n", lfree); + rt_kprintf("heap_end: 0x%08x\n", heap_end); + + rt_kprintf("\n--memory item information --\n"); + for (mem = (struct heap_mem *)heap_ptr; mem != heap_end; mem = (struct heap_mem *)&heap_ptr[mem->next]) + { + int position = (rt_uint32_t)mem - (rt_uint32_t)heap_ptr; + int size; + + rt_kprintf("[0x%08x - ", mem); + + size = mem->next - position - SIZEOF_STRUCT_MEM; + if (size < 1024) + rt_kprintf("%5d", size); + else if (size < 1024 * 1024) + rt_kprintf("%4dK", size / 1024); + else + rt_kprintf("%4dM", size / (1024 * 1024)); + + rt_kprintf("] %c%c%c%c", mem->thread[0], mem->thread[1], mem->thread[2], mem->thread[3]); + if (mem->magic != HEAP_MAGIC) + rt_kprintf(": ***\n"); + else + rt_kprintf("\n"); + } + + return 0; +} +MSH_CMD_EXPORT(memtrace, dump memory trace information); +#endif /* end of RT_USING_MEMTRACE */ +#endif /* end of RT_USING_FINSH */ + +#endif + +/**@}*/ + +#endif /* end of RT_USING_HEAP */ +#endif /* end of RT_USING_MEMHEAP_AS_HEAP */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/memheap.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/memheap.c new file mode 100644 index 0000000000..eb5d710029 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/memheap.c @@ -0,0 +1,717 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * File : memheap.c + * + * Change Logs: + * Date Author Notes + * 2012-04-10 Bernard first implementation + * 2012-10-16 Bernard add the mutex lock for heap object. + * 2012-12-29 Bernard memheap can be used as system heap. + * change mutex lock to semaphore lock. + * 2013-04-10 Bernard add rt_memheap_realloc function. + * 2013-05-24 Bernard fix the rt_memheap_realloc issue. + * 2013-07-11 Grissiom fix the memory block splitting issue. + * 2013-07-15 Grissiom optimize rt_memheap_realloc + */ + +#include +#include + +#ifdef RT_USING_MEMHEAP + +/* dynamic pool magic and mask */ +#define RT_MEMHEAP_MAGIC 0x1ea01ea0 +#define RT_MEMHEAP_MASK 0xfffffffe +#define RT_MEMHEAP_USED 0x01 +#define RT_MEMHEAP_FREED 0x00 + +#define RT_MEMHEAP_IS_USED(i) ((i)->magic & RT_MEMHEAP_USED) +#define RT_MEMHEAP_MINIALLOC 12 + +#define RT_MEMHEAP_SIZE RT_ALIGN(sizeof(struct rt_memheap_item), RT_ALIGN_SIZE) +#define MEMITEM_SIZE(item) ((rt_uint32_t)item->next - (rt_uint32_t)item - RT_MEMHEAP_SIZE) + +/* + * The initialized memory pool will be: + * +-----------------------------------+--------------------------+ + * | whole freed memory block | Used Memory Block Tailer | + * +-----------------------------------+--------------------------+ + * + * block_list --> whole freed memory block + * + * The length of Used Memory Block Tailer is 0, + * which is prevents block merging across list + */ +rt_err_t rt_memheap_init(struct rt_memheap *memheap, + const char *name, + void *start_addr, + rt_size_t size) +{ + struct rt_memheap_item *item; + + RT_ASSERT(memheap != RT_NULL); + + /* initialize pool object */ + rt_object_init(&(memheap->parent), RT_Object_Class_MemHeap, name); + + memheap->start_addr = start_addr; + memheap->pool_size = RT_ALIGN_DOWN(size, RT_ALIGN_SIZE); + memheap->available_size = memheap->pool_size - (2 * RT_MEMHEAP_SIZE); + memheap->max_used_size = memheap->pool_size - memheap->available_size; + + /* initialize the free list header */ + item = &(memheap->free_header); + item->magic = RT_MEMHEAP_MAGIC; + item->pool_ptr = memheap; + item->next = RT_NULL; + item->prev = RT_NULL; + item->next_free = item; + item->prev_free = item; + + /* set the free list to free list header */ + memheap->free_list = item; + + /* initialize the first big memory block */ + item = (struct rt_memheap_item *)start_addr; + item->magic = RT_MEMHEAP_MAGIC; + item->pool_ptr = memheap; + item->next = RT_NULL; + item->prev = RT_NULL; + item->next_free = item; + item->prev_free = item; + + item->next = (struct rt_memheap_item *) + ((rt_uint8_t *)item + memheap->available_size + RT_MEMHEAP_SIZE); + item->prev = item->next; + + /* block list header */ + memheap->block_list = item; + + /* place the big memory block to free list */ + item->next_free = memheap->free_list->next_free; + item->prev_free = memheap->free_list; + memheap->free_list->next_free->prev_free = item; + memheap->free_list->next_free = item; + + /* move to the end of memory pool to build a small tailer block, + * which prevents block merging + */ + item = item->next; + /* it's a used memory block */ + item->magic = RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED; + item->pool_ptr = memheap; + item->next = (struct rt_memheap_item *)start_addr; + item->prev = (struct rt_memheap_item *)start_addr; + /* not in free list */ + item->next_free = item->prev_free = RT_NULL; + + /* initialize semaphore lock */ + rt_sem_init(&(memheap->lock), name, 1, RT_IPC_FLAG_FIFO); + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("memory heap: start addr 0x%08x, size %d, free list header 0x%08x\n", + start_addr, size, &(memheap->free_header))); + + return RT_EOK; +} +RTM_EXPORT(rt_memheap_init); + +rt_err_t rt_memheap_detach(struct rt_memheap *heap) +{ + RT_ASSERT(heap); + RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); + RT_ASSERT(rt_object_is_systemobject(&heap->parent)); + + rt_object_detach(&(heap->lock.parent.parent)); + rt_object_detach(&(heap->parent)); + + /* Return a successful completion. */ + return RT_EOK; +} +RTM_EXPORT(rt_memheap_detach); + +void *rt_memheap_alloc(struct rt_memheap *heap, rt_size_t size) +{ + rt_err_t result; + rt_uint32_t free_size; + struct rt_memheap_item *header_ptr; + + RT_ASSERT(heap != RT_NULL); + RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); + + /* align allocated size */ + size = RT_ALIGN(size, RT_ALIGN_SIZE); + if (size < RT_MEMHEAP_MINIALLOC) + size = RT_MEMHEAP_MINIALLOC; + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("allocate %d on heap:%8.*s", + size, RT_NAME_MAX, heap->parent.name)); + + if (size < heap->available_size) + { + /* search on free list */ + free_size = 0; + + /* lock memheap */ + result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); + if (result != RT_EOK) + { + rt_set_errno(result); + + return RT_NULL; + } + + /* get the first free memory block */ + header_ptr = heap->free_list->next_free; + while (header_ptr != heap->free_list && free_size < size) + { + /* get current freed memory block size */ + free_size = MEMITEM_SIZE(header_ptr); + if (free_size < size) + { + /* move to next free memory block */ + header_ptr = header_ptr->next_free; + } + } + + /* determine if the memory is available. */ + if (free_size >= size) + { + /* a block that satisfies the request has been found. */ + + /* determine if the block needs to be split. */ + if (free_size >= (size + RT_MEMHEAP_SIZE + RT_MEMHEAP_MINIALLOC)) + { + struct rt_memheap_item *new_ptr; + + /* split the block. */ + new_ptr = (struct rt_memheap_item *) + (((rt_uint8_t *)header_ptr) + size + RT_MEMHEAP_SIZE); + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("split: block[0x%08x] nextm[0x%08x] prevm[0x%08x] to new[0x%08x]\n", + header_ptr, + header_ptr->next, + header_ptr->prev, + new_ptr)); + + /* mark the new block as a memory block and freed. */ + new_ptr->magic = RT_MEMHEAP_MAGIC; + + /* put the pool pointer into the new block. */ + new_ptr->pool_ptr = heap; + + /* break down the block list */ + new_ptr->prev = header_ptr; + new_ptr->next = header_ptr->next; + header_ptr->next->prev = new_ptr; + header_ptr->next = new_ptr; + + /* remove header ptr from free list */ + header_ptr->next_free->prev_free = header_ptr->prev_free; + header_ptr->prev_free->next_free = header_ptr->next_free; + header_ptr->next_free = RT_NULL; + header_ptr->prev_free = RT_NULL; + + /* insert new_ptr to free list */ + new_ptr->next_free = heap->free_list->next_free; + new_ptr->prev_free = heap->free_list; + heap->free_list->next_free->prev_free = new_ptr; + heap->free_list->next_free = new_ptr; + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new ptr: next_free 0x%08x, prev_free 0x%08x\n", + new_ptr->next_free, + new_ptr->prev_free)); + + /* decrement the available byte count. */ + heap->available_size = heap->available_size - + size - + RT_MEMHEAP_SIZE; + if (heap->pool_size - heap->available_size > heap->max_used_size) + heap->max_used_size = heap->pool_size - heap->available_size; + } + else + { + /* decrement the entire free size from the available bytes count. */ + heap->available_size = heap->available_size - free_size; + if (heap->pool_size - heap->available_size > heap->max_used_size) + heap->max_used_size = heap->pool_size - heap->available_size; + + /* remove header_ptr from free list */ + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("one block: block[0x%08x], next_free 0x%08x, prev_free 0x%08x\n", + header_ptr, + header_ptr->next_free, + header_ptr->prev_free)); + + header_ptr->next_free->prev_free = header_ptr->prev_free; + header_ptr->prev_free->next_free = header_ptr->next_free; + header_ptr->next_free = RT_NULL; + header_ptr->prev_free = RT_NULL; + } + + /* Mark the allocated block as not available. */ + header_ptr->magic |= RT_MEMHEAP_USED; + + /* release lock */ + rt_sem_release(&(heap->lock)); + + /* Return a memory address to the caller. */ + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("alloc mem: memory[0x%08x], heap[0x%08x], size: %d\n", + (void *)((rt_uint8_t *)header_ptr + RT_MEMHEAP_SIZE), + header_ptr, + size)); + + return (void *)((rt_uint8_t *)header_ptr + RT_MEMHEAP_SIZE); + } + + /* release lock */ + rt_sem_release(&(heap->lock)); + } + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("allocate memory: failed\n")); + + /* Return the completion status. */ + return RT_NULL; +} +RTM_EXPORT(rt_memheap_alloc); + +void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize) +{ + rt_err_t result; + rt_size_t oldsize; + struct rt_memheap_item *header_ptr; + struct rt_memheap_item *new_ptr; + + RT_ASSERT(heap); + RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); + + if (newsize == 0) + { + rt_memheap_free(ptr); + + return RT_NULL; + } + /* align allocated size */ + newsize = RT_ALIGN(newsize, RT_ALIGN_SIZE); + if (newsize < RT_MEMHEAP_MINIALLOC) + newsize = RT_MEMHEAP_MINIALLOC; + + if (ptr == RT_NULL) + { + return rt_memheap_alloc(heap, newsize); + } + + /* get memory block header and get the size of memory block */ + header_ptr = (struct rt_memheap_item *) + ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE); + oldsize = MEMITEM_SIZE(header_ptr); + /* re-allocate memory */ + if (newsize > oldsize) + { + void *new_ptr; + struct rt_memheap_item *next_ptr; + + /* lock memheap */ + result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); + if (result != RT_EOK) + { + rt_set_errno(result); + return RT_NULL; + } + + next_ptr = header_ptr->next; + + /* header_ptr should not be the tail */ + RT_ASSERT(next_ptr > header_ptr); + + /* check whether the following free space is enough to expand */ + if (!RT_MEMHEAP_IS_USED(next_ptr)) + { + rt_int32_t nextsize; + + nextsize = MEMITEM_SIZE(next_ptr); + RT_ASSERT(next_ptr > 0); + + /* Here is the ASCII art of the situation that we can make use of + * the next free node without alloc/memcpy, |*| is the control + * block: + * + * oldsize free node + * |*|-----------|*|----------------------|*| + * newsize >= minialloc + * |*|----------------|*|-----------------|*| + */ + if (nextsize + oldsize > newsize + RT_MEMHEAP_MINIALLOC) + { + /* decrement the entire free size from the available bytes count. */ + heap->available_size = heap->available_size - (newsize - oldsize); + if (heap->pool_size - heap->available_size > heap->max_used_size) + heap->max_used_size = heap->pool_size - heap->available_size; + + /* remove next_ptr from free list */ + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("remove block: block[0x%08x], next_free 0x%08x, prev_free 0x%08x", + next_ptr, + next_ptr->next_free, + next_ptr->prev_free)); + + next_ptr->next_free->prev_free = next_ptr->prev_free; + next_ptr->prev_free->next_free = next_ptr->next_free; + next_ptr->next->prev = next_ptr->prev; + next_ptr->prev->next = next_ptr->next; + + /* build a new one on the right place */ + next_ptr = (struct rt_memheap_item *)((char *)ptr + newsize); + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("new free block: block[0x%08x] nextm[0x%08x] prevm[0x%08x]", + next_ptr, + next_ptr->next, + next_ptr->prev)); + + /* mark the new block as a memory block and freed. */ + next_ptr->magic = RT_MEMHEAP_MAGIC; + + /* put the pool pointer into the new block. */ + next_ptr->pool_ptr = heap; + + next_ptr->prev = header_ptr; + next_ptr->next = header_ptr->next; + header_ptr->next->prev = next_ptr; + header_ptr->next = next_ptr; + + /* insert next_ptr to free list */ + next_ptr->next_free = heap->free_list->next_free; + next_ptr->prev_free = heap->free_list; + heap->free_list->next_free->prev_free = next_ptr; + heap->free_list->next_free = next_ptr; + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new ptr: next_free 0x%08x, prev_free 0x%08x", + next_ptr->next_free, + next_ptr->prev_free)); + + /* release lock */ + rt_sem_release(&(heap->lock)); + + return ptr; + } + } + + /* release lock */ + rt_sem_release(&(heap->lock)); + + /* re-allocate a memory block */ + new_ptr = (void *)rt_memheap_alloc(heap, newsize); + if (new_ptr != RT_NULL) + { + rt_memcpy(new_ptr, ptr, oldsize < newsize ? oldsize : newsize); + rt_memheap_free(ptr); + } + + return new_ptr; + } + + /* don't split when there is less than one node space left */ + if (newsize + RT_MEMHEAP_SIZE + RT_MEMHEAP_MINIALLOC >= oldsize) + return ptr; + + /* lock memheap */ + result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); + if (result != RT_EOK) + { + rt_set_errno(result); + + return RT_NULL; + } + + /* split the block. */ + new_ptr = (struct rt_memheap_item *) + (((rt_uint8_t *)header_ptr) + newsize + RT_MEMHEAP_SIZE); + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("split: block[0x%08x] nextm[0x%08x] prevm[0x%08x] to new[0x%08x]\n", + header_ptr, + header_ptr->next, + header_ptr->prev, + new_ptr)); + + /* mark the new block as a memory block and freed. */ + new_ptr->magic = RT_MEMHEAP_MAGIC; + /* put the pool pointer into the new block. */ + new_ptr->pool_ptr = heap; + + /* break down the block list */ + new_ptr->prev = header_ptr; + new_ptr->next = header_ptr->next; + header_ptr->next->prev = new_ptr; + header_ptr->next = new_ptr; + + /* determine if the block can be merged with the next neighbor. */ + if (!RT_MEMHEAP_IS_USED(new_ptr->next)) + { + struct rt_memheap_item *free_ptr; + + /* merge block with next neighbor. */ + free_ptr = new_ptr->next; + heap->available_size = heap->available_size - MEMITEM_SIZE(free_ptr); + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("merge: right node 0x%08x, next_free 0x%08x, prev_free 0x%08x\n", + header_ptr, header_ptr->next_free, header_ptr->prev_free)); + + free_ptr->next->prev = new_ptr; + new_ptr->next = free_ptr->next; + + /* remove free ptr from free list */ + free_ptr->next_free->prev_free = free_ptr->prev_free; + free_ptr->prev_free->next_free = free_ptr->next_free; + } + + /* insert the split block to free list */ + new_ptr->next_free = heap->free_list->next_free; + new_ptr->prev_free = heap->free_list; + heap->free_list->next_free->prev_free = new_ptr; + heap->free_list->next_free = new_ptr; + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("new free ptr: next_free 0x%08x, prev_free 0x%08x\n", + new_ptr->next_free, + new_ptr->prev_free)); + + /* increment the available byte count. */ + heap->available_size = heap->available_size + MEMITEM_SIZE(new_ptr); + + /* release lock */ + rt_sem_release(&(heap->lock)); + + /* return the old memory block */ + return ptr; +} +RTM_EXPORT(rt_memheap_realloc); + +void rt_memheap_free(void *ptr) +{ + rt_err_t result; + struct rt_memheap *heap; + struct rt_memheap_item *header_ptr, *new_ptr; + rt_uint32_t insert_header; + + /* NULL check */ + if (ptr == RT_NULL) return; + + /* set initial status as OK */ + insert_header = 1; + new_ptr = RT_NULL; + header_ptr = (struct rt_memheap_item *) + ((rt_uint8_t *)ptr - RT_MEMHEAP_SIZE); + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("free memory: memory[0x%08x], block[0x%08x]\n", + ptr, header_ptr)); + + /* check magic */ + RT_ASSERT((header_ptr->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC); + RT_ASSERT(header_ptr->magic & RT_MEMHEAP_USED); + /* check whether this block of memory has been over-written. */ + RT_ASSERT((header_ptr->next->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC); + + /* get pool ptr */ + heap = header_ptr->pool_ptr; + + RT_ASSERT(heap); + RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); + + /* lock memheap */ + result = rt_sem_take(&(heap->lock), RT_WAITING_FOREVER); + if (result != RT_EOK) + { + rt_set_errno(result); + + return ; + } + + /* Mark the memory as available. */ + header_ptr->magic &= ~RT_MEMHEAP_USED; + /* Adjust the available number of bytes. */ + heap->available_size = heap->available_size + MEMITEM_SIZE(header_ptr); + + /* Determine if the block can be merged with the previous neighbor. */ + if (!RT_MEMHEAP_IS_USED(header_ptr->prev)) + { + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("merge: left node 0x%08x\n", + header_ptr->prev)); + + /* adjust the available number of bytes. */ + heap->available_size = heap->available_size + RT_MEMHEAP_SIZE; + + /* yes, merge block with previous neighbor. */ + (header_ptr->prev)->next = header_ptr->next; + (header_ptr->next)->prev = header_ptr->prev; + + /* move header pointer to previous. */ + header_ptr = header_ptr->prev; + /* don't insert header to free list */ + insert_header = 0; + } + + /* determine if the block can be merged with the next neighbor. */ + if (!RT_MEMHEAP_IS_USED(header_ptr->next)) + { + /* adjust the available number of bytes. */ + heap->available_size = heap->available_size + RT_MEMHEAP_SIZE; + + /* merge block with next neighbor. */ + new_ptr = header_ptr->next; + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("merge: right node 0x%08x, next_free 0x%08x, prev_free 0x%08x\n", + new_ptr, new_ptr->next_free, new_ptr->prev_free)); + + new_ptr->next->prev = header_ptr; + header_ptr->next = new_ptr->next; + + /* remove new ptr from free list */ + new_ptr->next_free->prev_free = new_ptr->prev_free; + new_ptr->prev_free->next_free = new_ptr->next_free; + } + + if (insert_header) + { + /* no left merge, insert to free list */ + header_ptr->next_free = heap->free_list->next_free; + header_ptr->prev_free = heap->free_list; + heap->free_list->next_free->prev_free = header_ptr; + heap->free_list->next_free = header_ptr; + + RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, + ("insert to free list: next_free 0x%08x, prev_free 0x%08x\n", + header_ptr->next_free, header_ptr->prev_free)); + } + + /* release lock */ + rt_sem_release(&(heap->lock)); +} +RTM_EXPORT(rt_memheap_free); + +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap _heap; + +void rt_system_heap_init(void *begin_addr, void *end_addr) +{ + /* initialize a default heap in the system */ + rt_memheap_init(&_heap, + "heap", + begin_addr, + (rt_uint32_t)end_addr - (rt_uint32_t)begin_addr); +} + +void *rt_malloc(rt_size_t size) +{ + void *ptr; + + /* try to allocate in system heap */ + ptr = rt_memheap_alloc(&_heap, size); + if (ptr == RT_NULL) + { + struct rt_object *object; + struct rt_list_node *node; + struct rt_memheap *heap; + struct rt_object_information *information; + + /* try to allocate on other memory heap */ + information = rt_object_get_information(RT_Object_Class_MemHeap); + RT_ASSERT(information != RT_NULL); + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + object = rt_list_entry(node, struct rt_object, list); + heap = (struct rt_memheap *)object; + + RT_ASSERT(heap); + RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); + + /* not allocate in the default system heap */ + if (heap == &_heap) + continue; + + ptr = rt_memheap_alloc(heap, size); + if (ptr != RT_NULL) + break; + } + } + + return ptr; +} +RTM_EXPORT(rt_malloc); + +void rt_free(void *rmem) +{ + rt_memheap_free(rmem); +} +RTM_EXPORT(rt_free); + +void *rt_realloc(void *rmem, rt_size_t newsize) +{ + void *new_ptr; + struct rt_memheap_item *header_ptr; + + if (rmem == RT_NULL) + return rt_malloc(newsize); + + if (newsize == 0) + { + rt_free(rmem); + return RT_NULL; + } + + /* get old memory item */ + header_ptr = (struct rt_memheap_item *) + ((rt_uint8_t *)rmem - RT_MEMHEAP_SIZE); + + new_ptr = rt_memheap_realloc(header_ptr->pool_ptr, rmem, newsize); + if (new_ptr == RT_NULL && newsize != 0) + { + /* allocate memory block from other memheap */ + new_ptr = rt_malloc(newsize); + if (new_ptr != RT_NULL && rmem != RT_NULL) + { + rt_size_t oldsize; + + /* get the size of old memory block */ + oldsize = MEMITEM_SIZE(header_ptr); + if (newsize > oldsize) + rt_memcpy(new_ptr, rmem, oldsize); + else + rt_memcpy(new_ptr, rmem, newsize); + + rt_free(rmem); + } + } + + return new_ptr; +} +RTM_EXPORT(rt_realloc); + +void *rt_calloc(rt_size_t count, rt_size_t size) +{ + void *ptr; + rt_size_t total_size; + + total_size = count * size; + ptr = rt_malloc(total_size); + if (ptr != RT_NULL) + { + /* clean memory */ + rt_memset(ptr, 0, total_size); + } + + return ptr; +} +RTM_EXPORT(rt_calloc); + +#endif + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/mempool.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/mempool.c new file mode 100644 index 0000000000..2184586aba --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/mempool.c @@ -0,0 +1,454 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-05-27 Bernard implement memory pool + * 2006-06-03 Bernard fix the thread timer init bug + * 2006-06-30 Bernard fix the allocate/free block bug + * 2006-08-04 Bernard add hook support + * 2006-08-10 Bernard fix interrupt bug in rt_mp_alloc + * 2010-07-13 Bernard fix RT_ALIGN issue found by kuronca + * 2010-10-26 yi.qiu add module support in rt_mp_delete + * 2011-01-24 Bernard add object allocation check. + * 2012-03-22 Bernard fix align issue in rt_mp_init and rt_mp_create. + */ + +#include +#include + +#ifdef RT_USING_MEMPOOL + +#ifdef RT_USING_HOOK +static void (*rt_mp_alloc_hook)(struct rt_mempool *mp, void *block); +static void (*rt_mp_free_hook)(struct rt_mempool *mp, void *block); + +/** + * @addtogroup Hook + */ + +/**@{*/ + +/** + * This function will set a hook function, which will be invoked when a memory + * block is allocated from memory pool. + * + * @param hook the hook function + */ +void rt_mp_alloc_sethook(void (*hook)(struct rt_mempool *mp, void *block)) +{ + rt_mp_alloc_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when a memory + * block is released to memory pool. + * + * @param hook the hook function + */ +void rt_mp_free_sethook(void (*hook)(struct rt_mempool *mp, void *block)) +{ + rt_mp_free_hook = hook; +} + +/**@}*/ +#endif + +/** + * @addtogroup MM + */ + +/**@{*/ + +/** + * This function will initialize a memory pool object, normally which is used + * for static object. + * + * @param mp the memory pool object + * @param name the name of memory pool + * @param start the star address of memory pool + * @param size the total size of memory pool + * @param block_size the size for each block + * + * @return RT_EOK + */ +rt_err_t rt_mp_init(struct rt_mempool *mp, + const char *name, + void *start, + rt_size_t size, + rt_size_t block_size) +{ + rt_uint8_t *block_ptr; + register rt_size_t offset; + + /* parameter check */ + RT_ASSERT(mp != RT_NULL); + + /* initialize object */ + rt_object_init(&(mp->parent), RT_Object_Class_MemPool, name); + + /* initialize memory pool */ + mp->start_address = start; + mp->size = RT_ALIGN_DOWN(size, RT_ALIGN_SIZE); + + /* align the block size */ + block_size = RT_ALIGN(block_size, RT_ALIGN_SIZE); + mp->block_size = block_size; + + /* align to align size byte */ + mp->block_total_count = mp->size / (mp->block_size + sizeof(rt_uint8_t *)); + mp->block_free_count = mp->block_total_count; + + /* initialize suspended thread list */ + rt_list_init(&(mp->suspend_thread)); + mp->suspend_thread_count = 0; + + /* initialize free block list */ + block_ptr = (rt_uint8_t *)mp->start_address; + for (offset = 0; offset < mp->block_total_count; offset ++) + { + *(rt_uint8_t **)(block_ptr + offset * (block_size + sizeof(rt_uint8_t *))) = + (rt_uint8_t *)(block_ptr + (offset + 1) * (block_size + sizeof(rt_uint8_t *))); + } + + *(rt_uint8_t **)(block_ptr + (offset - 1) * (block_size + sizeof(rt_uint8_t *))) = + RT_NULL; + + mp->block_list = block_ptr; + + return RT_EOK; +} +RTM_EXPORT(rt_mp_init); + +/** + * This function will detach a memory pool from system object management. + * + * @param mp the memory pool object + * + * @return RT_EOK + */ +rt_err_t rt_mp_detach(struct rt_mempool *mp) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + + /* parameter check */ + RT_ASSERT(mp != RT_NULL); + RT_ASSERT(rt_object_get_type(&mp->parent) == RT_Object_Class_MemPool); + RT_ASSERT(rt_object_is_systemobject(&mp->parent)); + + /* wake up all suspended threads */ + while (!rt_list_isempty(&(mp->suspend_thread))) + { + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* get next suspend thread */ + thread = rt_list_entry(mp->suspend_thread.next, struct rt_thread, tlist); + /* set error code to RT_ERROR */ + thread->error = -RT_ERROR; + + /* + * resume thread + * In rt_thread_resume function, it will remove current thread from + * suspend list + */ + rt_thread_resume(thread); + + /* decrease suspended thread count */ + mp->suspend_thread_count --; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + } + + /* detach object */ + rt_object_detach(&(mp->parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mp_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a mempool object and allocate the memory pool from + * heap. + * + * @param name the name of memory pool + * @param block_count the count of blocks in memory pool + * @param block_size the size for each block + * + * @return the created mempool object + */ +rt_mp_t rt_mp_create(const char *name, + rt_size_t block_count, + rt_size_t block_size) +{ + rt_uint8_t *block_ptr; + struct rt_mempool *mp; + register rt_size_t offset; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* allocate object */ + mp = (struct rt_mempool *)rt_object_allocate(RT_Object_Class_MemPool, name); + /* allocate object failed */ + if (mp == RT_NULL) + return RT_NULL; + + /* initialize memory pool */ + block_size = RT_ALIGN(block_size, RT_ALIGN_SIZE); + mp->block_size = block_size; + mp->size = (block_size + sizeof(rt_uint8_t *)) * block_count; + + /* allocate memory */ + mp->start_address = rt_malloc((block_size + sizeof(rt_uint8_t *)) * + block_count); + if (mp->start_address == RT_NULL) + { + /* no memory, delete memory pool object */ + rt_object_delete(&(mp->parent)); + + return RT_NULL; + } + + mp->block_total_count = block_count; + mp->block_free_count = mp->block_total_count; + + /* initialize suspended thread list */ + rt_list_init(&(mp->suspend_thread)); + mp->suspend_thread_count = 0; + + /* initialize free block list */ + block_ptr = (rt_uint8_t *)mp->start_address; + for (offset = 0; offset < mp->block_total_count; offset ++) + { + *(rt_uint8_t **)(block_ptr + offset * (block_size + sizeof(rt_uint8_t *))) + = block_ptr + (offset + 1) * (block_size + sizeof(rt_uint8_t *)); + } + + *(rt_uint8_t **)(block_ptr + (offset - 1) * (block_size + sizeof(rt_uint8_t *))) + = RT_NULL; + + mp->block_list = block_ptr; + + return mp; +} +RTM_EXPORT(rt_mp_create); + +/** + * This function will delete a memory pool and release the object memory. + * + * @param mp the memory pool object + * + * @return RT_EOK + */ +rt_err_t rt_mp_delete(rt_mp_t mp) +{ + struct rt_thread *thread; + register rt_ubase_t temp; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* parameter check */ + RT_ASSERT(mp != RT_NULL); + RT_ASSERT(rt_object_get_type(&mp->parent) == RT_Object_Class_MemPool); + RT_ASSERT(rt_object_is_systemobject(&mp->parent) == RT_FALSE); + + /* wake up all suspended threads */ + while (!rt_list_isempty(&(mp->suspend_thread))) + { + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* get next suspend thread */ + thread = rt_list_entry(mp->suspend_thread.next, struct rt_thread, tlist); + /* set error code to RT_ERROR */ + thread->error = -RT_ERROR; + + /* + * resume thread + * In rt_thread_resume function, it will remove current thread from + * suspend list + */ + rt_thread_resume(thread); + + /* decrease suspended thread count */ + mp->suspend_thread_count --; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + } + + /* release allocated room */ + rt_free(mp->start_address); + + /* detach object */ + rt_object_delete(&(mp->parent)); + + return RT_EOK; +} +RTM_EXPORT(rt_mp_delete); +#endif + +/** + * This function will allocate a block from memory pool + * + * @param mp the memory pool object + * @param time the waiting time + * + * @return the allocated memory block or RT_NULL on allocated failed + */ +void *rt_mp_alloc(rt_mp_t mp, rt_int32_t time) +{ + rt_uint8_t *block_ptr; + register rt_base_t level; + struct rt_thread *thread; + rt_uint32_t before_sleep = 0; + + /* get current thread */ + thread = rt_thread_self(); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + while (mp->block_free_count == 0) + { + /* memory block is unavailable. */ + if (time == 0) + { + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_set_errno(-RT_ETIMEOUT); + + return RT_NULL; + } + + RT_DEBUG_NOT_IN_INTERRUPT; + + thread->error = RT_EOK; + + /* need suspend thread */ + rt_thread_suspend(thread); + rt_list_insert_after(&(mp->suspend_thread), &(thread->tlist)); + mp->suspend_thread_count++; + + if (time > 0) + { + /* get the start tick of timer */ + before_sleep = rt_tick_get(); + + /* init thread timer and start it */ + rt_timer_control(&(thread->thread_timer), + RT_TIMER_CTRL_SET_TIME, + &time); + rt_timer_start(&(thread->thread_timer)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* do a schedule */ + rt_schedule(); + + if (thread->error != RT_EOK) + return RT_NULL; + + if (time > 0) + { + time -= rt_tick_get() - before_sleep; + if (time < 0) + time = 0; + } + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + } + + /* memory block is available. decrease the free block counter */ + mp->block_free_count--; + + /* get block from block list */ + block_ptr = mp->block_list; + RT_ASSERT(block_ptr != RT_NULL); + + /* Setup the next free node. */ + mp->block_list = *(rt_uint8_t **)block_ptr; + + /* point to memory pool */ + *(rt_uint8_t **)block_ptr = (rt_uint8_t *)mp; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + RT_OBJECT_HOOK_CALL(rt_mp_alloc_hook, + (mp, (rt_uint8_t *)(block_ptr + sizeof(rt_uint8_t *)))); + + return (rt_uint8_t *)(block_ptr + sizeof(rt_uint8_t *)); +} +RTM_EXPORT(rt_mp_alloc); + +/** + * This function will release a memory block + * + * @param block the address of memory block to be released + */ +void rt_mp_free(void *block) +{ + rt_uint8_t **block_ptr; + struct rt_mempool *mp; + struct rt_thread *thread; + register rt_base_t level; + + /* get the control block of pool which the block belongs to */ + block_ptr = (rt_uint8_t **)((rt_uint8_t *)block - sizeof(rt_uint8_t *)); + mp = (struct rt_mempool *)*block_ptr; + + RT_OBJECT_HOOK_CALL(rt_mp_free_hook, (mp, block)); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* increase the free block count */ + mp->block_free_count ++; + + /* link the block into the block list */ + *block_ptr = mp->block_list; + mp->block_list = (rt_uint8_t *)block_ptr; + + if (mp->suspend_thread_count > 0) + { + /* get the suspended thread */ + thread = rt_list_entry(mp->suspend_thread.next, + struct rt_thread, + tlist); + + /* set error */ + thread->error = RT_EOK; + + /* resume thread */ + rt_thread_resume(thread); + + /* decrease suspended thread count */ + mp->suspend_thread_count --; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* do a schedule */ + rt_schedule(); + + return; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} +RTM_EXPORT(rt_mp_free); + +/**@}*/ + +#endif + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/object.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/object.c new file mode 100644 index 0000000000..e85737ce8f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/object.c @@ -0,0 +1,518 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-14 Bernard the first version + * 2006-04-21 Bernard change the scheduler lock to interrupt lock + * 2006-05-18 Bernard fix the object init bug + * 2006-08-03 Bernard add hook support + * 2007-01-28 Bernard rename RT_OBJECT_Class_Static to RT_Object_Class_Static + * 2010-10-26 yi.qiu add module support in rt_object_allocate and rt_object_free + * 2017-12-10 Bernard Add object_info enum. + * 2018-01-25 Bernard Fix the object find issue when enable MODULE. + */ + +#include +#include + +#ifdef RT_USING_MODULE +#include +#endif + +/* + * define object_info for the number of rt_object_container items. + */ +enum rt_object_info_type +{ + RT_Object_Info_Thread = 0, /**< The object is a thread. */ +#ifdef RT_USING_SEMAPHORE + RT_Object_Info_Semaphore, /**< The object is a semaphore. */ +#endif +#ifdef RT_USING_MUTEX + RT_Object_Info_Mutex, /**< The object is a mutex. */ +#endif +#ifdef RT_USING_EVENT + RT_Object_Info_Event, /**< The object is a event. */ +#endif +#ifdef RT_USING_MAILBOX + RT_Object_Info_MailBox, /**< The object is a mail box. */ +#endif +#ifdef RT_USING_MESSAGEQUEUE + RT_Object_Info_MessageQueue, /**< The object is a message queue. */ +#endif +#ifdef RT_USING_MEMHEAP + RT_Object_Info_MemHeap, /**< The object is a memory heap */ +#endif +#ifdef RT_USING_MEMPOOL + RT_Object_Info_MemPool, /**< The object is a memory pool. */ +#endif +#ifdef RT_USING_DEVICE + RT_Object_Info_Device, /**< The object is a device */ +#endif + RT_Object_Info_Timer, /**< The object is a timer. */ +#ifdef RT_USING_MODULE + RT_Object_Info_Module, /**< The object is a module. */ +#endif + RT_Object_Info_Unknown, /**< The object is unknown. */ +}; + +#define _OBJ_CONTAINER_LIST_INIT(c) \ + {&(rt_object_container[c].object_list), &(rt_object_container[c].object_list)} +static struct rt_object_information rt_object_container[RT_Object_Info_Unknown] = +{ + /* initialize object container - thread */ + {RT_Object_Class_Thread, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Thread), sizeof(struct rt_thread)}, +#ifdef RT_USING_SEMAPHORE + /* initialize object container - semaphore */ + {RT_Object_Class_Semaphore, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Semaphore), sizeof(struct rt_semaphore)}, +#endif +#ifdef RT_USING_MUTEX + /* initialize object container - mutex */ + {RT_Object_Class_Mutex, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Mutex), sizeof(struct rt_mutex)}, +#endif +#ifdef RT_USING_EVENT + /* initialize object container - event */ + {RT_Object_Class_Event, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Event), sizeof(struct rt_event)}, +#endif +#ifdef RT_USING_MAILBOX + /* initialize object container - mailbox */ + {RT_Object_Class_MailBox, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_MailBox), sizeof(struct rt_mailbox)}, +#endif +#ifdef RT_USING_MESSAGEQUEUE + /* initialize object container - message queue */ + {RT_Object_Class_MessageQueue, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_MessageQueue), sizeof(struct rt_messagequeue)}, +#endif +#ifdef RT_USING_MEMHEAP + /* initialize object container - memory heap */ + {RT_Object_Class_MemHeap, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_MemHeap), sizeof(struct rt_memheap)}, +#endif +#ifdef RT_USING_MEMPOOL + /* initialize object container - memory pool */ + {RT_Object_Class_MemPool, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_MemPool), sizeof(struct rt_mempool)}, +#endif +#ifdef RT_USING_DEVICE + /* initialize object container - device */ + {RT_Object_Class_Device, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Device), sizeof(struct rt_device)}, +#endif + /* initialize object container - timer */ + {RT_Object_Class_Timer, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Timer), sizeof(struct rt_timer)}, +#ifdef RT_USING_MODULE + /* initialize object container - module */ + {RT_Object_Class_Module, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Module), sizeof(struct rt_dlmodule)}, +#endif +}; + +#ifdef RT_USING_HOOK +static void (*rt_object_attach_hook)(struct rt_object *object); +static void (*rt_object_detach_hook)(struct rt_object *object); +void (*rt_object_trytake_hook)(struct rt_object *object); +void (*rt_object_take_hook)(struct rt_object *object); +void (*rt_object_put_hook)(struct rt_object *object); + +/** + * @addtogroup Hook + */ + +/**@{*/ + +/** + * This function will set a hook function, which will be invoked when object + * attaches to kernel object system. + * + * @param hook the hook function + */ +void rt_object_attach_sethook(void (*hook)(struct rt_object *object)) +{ + rt_object_attach_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when object + * detaches from kernel object system. + * + * @param hook the hook function + */ +void rt_object_detach_sethook(void (*hook)(struct rt_object *object)) +{ + rt_object_detach_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when object + * is taken from kernel object system. + * + * The object is taken means: + * semaphore - semaphore is taken by thread + * mutex - mutex is taken by thread + * event - event is received by thread + * mailbox - mail is received by thread + * message queue - message is received by thread + * + * @param hook the hook function + */ +void rt_object_trytake_sethook(void (*hook)(struct rt_object *object)) +{ + rt_object_trytake_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when object + * have been taken from kernel object system. + * + * The object have been taken means: + * semaphore - semaphore have been taken by thread + * mutex - mutex have been taken by thread + * event - event have been received by thread + * mailbox - mail have been received by thread + * message queue - message have been received by thread + * timer - timer is started + * + * @param hook the hook function + */ +void rt_object_take_sethook(void (*hook)(struct rt_object *object)) +{ + rt_object_take_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when object + * is put to kernel object system. + * + * @param hook the hook function + */ +void rt_object_put_sethook(void (*hook)(struct rt_object *object)) +{ + rt_object_put_hook = hook; +} + +/**@}*/ +#endif + +/** + * @ingroup SystemInit + * + * This function will initialize system object management. + * + * @deprecated since 0.3.0, this function does not need to be invoked + * in the system initialization. + */ +void rt_system_object_init(void) +{ +} + +/** + * @addtogroup KernelObject + */ + +/**@{*/ + +/** + * This function will return the specified type of object information. + * + * @param type the type of object + * @return the object type information or RT_NULL + */ +struct rt_object_information * +rt_object_get_information(enum rt_object_class_type type) +{ + int index; + + for (index = 0; index < RT_Object_Info_Unknown; index ++) + if (rt_object_container[index].type == type) return &rt_object_container[index]; + + return RT_NULL; +} +RTM_EXPORT(rt_object_get_information); + +/** + * This function will initialize an object and add it to object system + * management. + * + * @param object the specified object to be initialized. + * @param type the object type. + * @param name the object name. In system, the object's name must be unique. + */ +void rt_object_init(struct rt_object *object, + enum rt_object_class_type type, + const char *name) +{ + register rt_base_t temp; + struct rt_list_node *node = RT_NULL; + struct rt_object_information *information; +#ifdef RT_USING_MODULE + struct rt_dlmodule *module = dlmodule_self(); +#endif + + /* get object information */ + information = rt_object_get_information(type); + RT_ASSERT(information != RT_NULL); + + /* check object type to avoid re-initialization */ + + /* enter critical */ + rt_enter_critical(); + /* try to find object */ + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + struct rt_object *obj; + + obj = rt_list_entry(node, struct rt_object, list); + RT_ASSERT(obj != object); + } + /* leave critical */ + rt_exit_critical(); + + /* initialize object's parameters */ + /* set object type to static */ + object->type = type | RT_Object_Class_Static; + /* copy name */ + rt_strncpy(object->name, name, RT_NAME_MAX); + + RT_OBJECT_HOOK_CALL(rt_object_attach_hook, (object)); + + /* lock interrupt */ + temp = rt_hw_interrupt_disable(); + +#ifdef RT_USING_MODULE + if (module) + { + rt_list_insert_after(&(module->object_list), &(object->list)); + object->module_id = (void *)module; + } + else +#endif + { + /* insert object into information object list */ + rt_list_insert_after(&(information->object_list), &(object->list)); + } + + /* unlock interrupt */ + rt_hw_interrupt_enable(temp); +} + +/** + * This function will detach a static object from object system, + * and the memory of static object is not freed. + * + * @param object the specified object to be detached. + */ +void rt_object_detach(rt_object_t object) +{ + register rt_base_t temp; + + /* object check */ + RT_ASSERT(object != RT_NULL); + + RT_OBJECT_HOOK_CALL(rt_object_detach_hook, (object)); + + /* reset object type */ + object->type = 0; + + /* lock interrupt */ + temp = rt_hw_interrupt_disable(); + + /* remove from old list */ + rt_list_remove(&(object->list)); + + /* unlock interrupt */ + rt_hw_interrupt_enable(temp); +} + +#ifdef RT_USING_HEAP +/** + * This function will allocate an object from object system + * + * @param type the type of object + * @param name the object name. In system, the object's name must be unique. + * + * @return object + */ +rt_object_t rt_object_allocate(enum rt_object_class_type type, const char *name) +{ + struct rt_object *object; + register rt_base_t temp; + struct rt_object_information *information; +#ifdef RT_USING_MODULE + struct rt_dlmodule *module = dlmodule_self(); +#endif + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* get object information */ + information = rt_object_get_information(type); + RT_ASSERT(information != RT_NULL); + + object = (struct rt_object *)RT_KERNEL_MALLOC(information->object_size); + if (object == RT_NULL) + { + /* no memory can be allocated */ + return RT_NULL; + } + + /* clean memory data of object */ + rt_memset(object, 0x0, information->object_size); + + /* initialize object's parameters */ + + /* set object type */ + object->type = type; + + /* set object flag */ + object->flag = 0; + + /* copy name */ + rt_strncpy(object->name, name, RT_NAME_MAX); + + RT_OBJECT_HOOK_CALL(rt_object_attach_hook, (object)); + + /* lock interrupt */ + temp = rt_hw_interrupt_disable(); + +#ifdef RT_USING_MODULE + if (module) + { + rt_list_insert_after(&(module->object_list), &(object->list)); + object->module_id = (void *)module; + } + else +#endif + { + /* insert object into information object list */ + rt_list_insert_after(&(information->object_list), &(object->list)); + } + + /* unlock interrupt */ + rt_hw_interrupt_enable(temp); + + /* return object */ + return object; +} + +/** + * This function will delete an object and release object memory. + * + * @param object the specified object to be deleted. + */ +void rt_object_delete(rt_object_t object) +{ + register rt_base_t temp; + + /* object check */ + RT_ASSERT(object != RT_NULL); + RT_ASSERT(!(object->type & RT_Object_Class_Static)); + + RT_OBJECT_HOOK_CALL(rt_object_detach_hook, (object)); + + /* reset object type */ + object->type = 0; + + /* lock interrupt */ + temp = rt_hw_interrupt_disable(); + + /* remove from old list */ + rt_list_remove(&(object->list)); + + /* unlock interrupt */ + rt_hw_interrupt_enable(temp); + + /* free the memory of object */ + RT_KERNEL_FREE(object); +} +#endif + +/** + * This function will judge the object is system object or not. + * Normally, the system object is a static object and the type + * of object set to RT_Object_Class_Static. + * + * @param object the specified object to be judged. + * + * @return RT_TRUE if a system object, RT_FALSE for others. + */ +rt_bool_t rt_object_is_systemobject(rt_object_t object) +{ + /* object check */ + RT_ASSERT(object != RT_NULL); + + if (object->type & RT_Object_Class_Static) + return RT_TRUE; + + return RT_FALSE; +} + +/** + * This function will return the type of object without + * RT_Object_Class_Static flag. + * + * @param object the specified object to be get type. + * + * @return the type of object. + */ +rt_uint8_t rt_object_get_type(rt_object_t object) +{ + /* object check */ + RT_ASSERT(object != RT_NULL); + + return object->type & ~RT_Object_Class_Static; +} + +/** + * This function will find specified name object from object + * container. + * + * @param name the specified name of object. + * @param type the type of object + * + * @return the found object or RT_NULL if there is no this object + * in object container. + * + * @note this function shall not be invoked in interrupt status. + */ +rt_object_t rt_object_find(const char *name, rt_uint8_t type) +{ + struct rt_object *object = RT_NULL; + struct rt_list_node *node = RT_NULL; + struct rt_object_information *information = RT_NULL; + + /* parameter check */ + if ((name == RT_NULL) || (type > RT_Object_Class_Unknown)) + return RT_NULL; + + /* which is invoke in interrupt status */ + RT_DEBUG_NOT_IN_INTERRUPT; + + /* enter critical */ + rt_enter_critical(); + + /* try to find object */ + if (information == RT_NULL) + { + information = rt_object_get_information((enum rt_object_class_type)type); + RT_ASSERT(information != RT_NULL); + } + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + object = rt_list_entry(node, struct rt_object, list); + if (rt_strncmp(object->name, name, RT_NAME_MAX) == 0) + { + /* leave critical */ + rt_exit_critical(); + + return object; + } + } + + /* leave critical */ + rt_exit_critical(); + + return RT_NULL; +} + +/**@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/scheduler.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/scheduler.c new file mode 100644 index 0000000000..513c5a70eb --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/scheduler.c @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-17 Bernard the first version + * 2006-04-28 Bernard fix the scheduler algorthm + * 2006-04-30 Bernard add SCHEDULER_DEBUG + * 2006-05-27 Bernard fix the scheduler algorthm for same priority + * thread schedule + * 2006-06-04 Bernard rewrite the scheduler algorithm + * 2006-08-03 Bernard add hook support + * 2006-09-05 Bernard add 32 priority level support + * 2006-09-24 Bernard add rt_system_scheduler_start function + * 2009-09-16 Bernard fix _rt_scheduler_stack_check + * 2010-04-11 yi.qiu add module feature + * 2010-07-13 Bernard fix the maximal number of rt_scheduler_lock_nest + * issue found by kuronca + * 2010-12-13 Bernard add defunct list initialization even if not use heap. + * 2011-05-10 Bernard clean scheduler debug log. + * 2013-12-21 Grissiom add rt_critical_level + */ + +#include +#include + +static rt_int16_t rt_scheduler_lock_nest; +extern volatile rt_uint8_t rt_interrupt_nest; + +rt_list_t rt_thread_priority_table[RT_THREAD_PRIORITY_MAX]; +struct rt_thread *rt_current_thread; + +rt_uint8_t rt_current_priority; + +#if RT_THREAD_PRIORITY_MAX > 32 +/* Maximum priority level, 256 */ +rt_uint32_t rt_thread_ready_priority_group; +rt_uint8_t rt_thread_ready_table[32]; +#else +/* Maximum priority level, 32 */ +rt_uint32_t rt_thread_ready_priority_group; +#endif + +rt_list_t rt_thread_defunct; + +#ifdef RT_USING_HOOK +static void (*rt_scheduler_hook)(struct rt_thread *from, struct rt_thread *to); + +/** + * @addtogroup Hook + */ + +/**@{*/ + +/** + * This function will set a hook function, which will be invoked when thread + * switch happens. + * + * @param hook the hook function + */ +void +rt_scheduler_sethook(void (*hook)(struct rt_thread *from, struct rt_thread *to)) +{ + rt_scheduler_hook = hook; +} + +/**@}*/ +#endif + +#ifdef RT_USING_OVERFLOW_CHECK +static void _rt_scheduler_stack_check(struct rt_thread *thread) +{ + RT_ASSERT(thread != RT_NULL); + +#if defined(ARCH_CPU_STACK_GROWS_UPWARD) + if (*((rt_uint8_t *)((rt_ubase_t)thread->stack_addr + thread->stack_size - 1)) != '#' || +#else + if (*((rt_uint8_t *)thread->stack_addr) != '#' || +#endif + (rt_uint32_t)thread->sp <= (rt_uint32_t)thread->stack_addr || + (rt_uint32_t)thread->sp > + (rt_uint32_t)thread->stack_addr + (rt_uint32_t)thread->stack_size) + { + rt_uint32_t level; + + rt_kprintf("thread:%s stack overflow\n", thread->name); +#ifdef RT_USING_FINSH + { + extern long list_thread(void); + list_thread(); + } +#endif + level = rt_hw_interrupt_disable(); + while (level); + } +#if defined(ARCH_CPU_STACK_GROWS_UPWARD) + else if ((rt_uint32_t)thread->sp > ((rt_uint32_t)thread->stack_addr + thread->stack_size)) + { + rt_kprintf("warning: %s stack is close to the top of stack address.\n", + thread->name); + } +#else + else if ((rt_uint32_t)thread->sp <= ((rt_uint32_t)thread->stack_addr + 32)) + { + rt_kprintf("warning: %s stack is close to the bottom of stack address.\n", + thread->name); + } +#endif +} +#endif + +/** + * @ingroup SystemInit + * This function will initialize the system scheduler + */ +void rt_system_scheduler_init(void) +{ + register rt_base_t offset; + + rt_scheduler_lock_nest = 0; + + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, ("start scheduler: max priority 0x%02x\n", + RT_THREAD_PRIORITY_MAX)); + + for (offset = 0; offset < RT_THREAD_PRIORITY_MAX; offset ++) + { + rt_list_init(&rt_thread_priority_table[offset]); + } + + rt_current_priority = RT_THREAD_PRIORITY_MAX - 1; + rt_current_thread = RT_NULL; + + /* initialize ready priority group */ + rt_thread_ready_priority_group = 0; + +#if RT_THREAD_PRIORITY_MAX > 32 + /* initialize ready table */ + rt_memset(rt_thread_ready_table, 0, sizeof(rt_thread_ready_table)); +#endif + + /* initialize thread defunct */ + rt_list_init(&rt_thread_defunct); +} + +/** + * @ingroup SystemInit + * This function will startup scheduler. It will select one thread + * with the highest priority level, then switch to it. + */ +void rt_system_scheduler_start(void) +{ + register struct rt_thread *to_thread; + register rt_ubase_t highest_ready_priority; + +#if RT_THREAD_PRIORITY_MAX > 32 + register rt_ubase_t number; + + number = __rt_ffs(rt_thread_ready_priority_group) - 1; + highest_ready_priority = (number << 3) + __rt_ffs(rt_thread_ready_table[number]) - 1; +#else + highest_ready_priority = __rt_ffs(rt_thread_ready_priority_group) - 1; +#endif + + /* get switch to thread */ + to_thread = rt_list_entry(rt_thread_priority_table[highest_ready_priority].next, + struct rt_thread, + tlist); + + rt_current_thread = to_thread; + + /* switch to new thread */ + rt_hw_context_switch_to((rt_uint32_t)&to_thread->sp); + + /* never come back */ +} + +/** + * @addtogroup Thread + */ + +/**@{*/ + +/** + * This function will perform one schedule. It will select one thread + * with the highest priority level, then switch to it. + */ +void rt_schedule(void) +{ + rt_base_t level; + struct rt_thread *to_thread; + struct rt_thread *from_thread; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* check the scheduler is enabled or not */ + if (rt_scheduler_lock_nest == 0) + { + register rt_ubase_t highest_ready_priority; + +#if RT_THREAD_PRIORITY_MAX <= 32 + highest_ready_priority = __rt_ffs(rt_thread_ready_priority_group) - 1; +#else + register rt_ubase_t number; + + number = __rt_ffs(rt_thread_ready_priority_group) - 1; + highest_ready_priority = (number << 3) + __rt_ffs(rt_thread_ready_table[number]) - 1; +#endif + + /* get switch to thread */ + to_thread = rt_list_entry(rt_thread_priority_table[highest_ready_priority].next, + struct rt_thread, + tlist); + + /* if the destination thread is not the same as current thread */ + if (to_thread != rt_current_thread) + { + rt_current_priority = (rt_uint8_t)highest_ready_priority; + from_thread = rt_current_thread; + rt_current_thread = to_thread; + + RT_OBJECT_HOOK_CALL(rt_scheduler_hook, (from_thread, to_thread)); + + /* switch to new thread */ + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, + ("[%d]switch to priority#%d " + "thread:%.*s(sp:0x%p), " + "from thread:%.*s(sp: 0x%p)\n", + rt_interrupt_nest, highest_ready_priority, + RT_NAME_MAX, to_thread->name, to_thread->sp, + RT_NAME_MAX, from_thread->name, from_thread->sp)); + +#ifdef RT_USING_OVERFLOW_CHECK + _rt_scheduler_stack_check(to_thread); +#endif + + if (rt_interrupt_nest == 0) + { + rt_hw_context_switch((rt_uint32_t)&from_thread->sp, + (rt_uint32_t)&to_thread->sp); + +#ifdef RT_USING_SIGNALS + if (rt_current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING) + { + extern void rt_thread_handle_sig(rt_bool_t clean_state); + + rt_current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING; + + rt_hw_interrupt_enable(level); + + /* check signal status */ + rt_thread_handle_sig(RT_TRUE); + } + else +#endif + { + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + return ; + } + else + { + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, ("switch in interrupt\n")); + + rt_hw_context_switch_interrupt((rt_uint32_t)&from_thread->sp, + (rt_uint32_t)&to_thread->sp); + } + } + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +/* + * This function will insert a thread to system ready queue. The state of + * thread will be set as READY and remove from suspend queue. + * + * @param thread the thread to be inserted + * @note Please do not invoke this function in user application. + */ +void rt_schedule_insert_thread(struct rt_thread *thread) +{ + register rt_base_t temp; + + RT_ASSERT(thread != RT_NULL); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* change stat */ + thread->stat = RT_THREAD_READY | (thread->stat & ~RT_THREAD_STAT_MASK); + + /* insert thread to ready list */ + rt_list_insert_before(&(rt_thread_priority_table[thread->current_priority]), + &(thread->tlist)); + + /* set priority mask */ +#if RT_THREAD_PRIORITY_MAX <= 32 + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, ("insert thread[%.*s], the priority: %d\n", + RT_NAME_MAX, thread->name, thread->current_priority)); +#else + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, + ("insert thread[%.*s], the priority: %d 0x%x %d\n", + RT_NAME_MAX, + thread->name, + thread->number, + thread->number_mask, + thread->high_mask)); +#endif + +#if RT_THREAD_PRIORITY_MAX > 32 + rt_thread_ready_table[thread->number] |= thread->high_mask; +#endif + rt_thread_ready_priority_group |= thread->number_mask; + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); +} + +/* + * This function will remove a thread from system ready queue. + * + * @param thread the thread to be removed + * + * @note Please do not invoke this function in user application. + */ +void rt_schedule_remove_thread(struct rt_thread *thread) +{ + register rt_base_t temp; + + RT_ASSERT(thread != RT_NULL); + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + +#if RT_THREAD_PRIORITY_MAX <= 32 + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, ("remove thread[%.*s], the priority: %d\n", + RT_NAME_MAX, thread->name, + thread->current_priority)); +#else + RT_DEBUG_LOG(RT_DEBUG_SCHEDULER, + ("remove thread[%.*s], the priority: %d 0x%x %d\n", + RT_NAME_MAX, + thread->name, + thread->number, + thread->number_mask, + thread->high_mask)); +#endif + + /* remove thread from ready list */ + rt_list_remove(&(thread->tlist)); + if (rt_list_isempty(&(rt_thread_priority_table[thread->current_priority]))) + { +#if RT_THREAD_PRIORITY_MAX > 32 + rt_thread_ready_table[thread->number] &= ~thread->high_mask; + if (rt_thread_ready_table[thread->number] == 0) + { + rt_thread_ready_priority_group &= ~thread->number_mask; + } +#else + rt_thread_ready_priority_group &= ~thread->number_mask; +#endif + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); +} + +/** + * This function will lock the thread scheduler. + */ +void rt_enter_critical(void) +{ + register rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* + * the maximal number of nest is RT_UINT16_MAX, which is big + * enough and does not check here + */ + rt_scheduler_lock_nest ++; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} +RTM_EXPORT(rt_enter_critical); + +/** + * This function will unlock the thread scheduler. + */ +void rt_exit_critical(void) +{ + register rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + rt_scheduler_lock_nest --; + if (rt_scheduler_lock_nest <= 0) + { + rt_scheduler_lock_nest = 0; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (rt_current_thread) + { + /* if scheduler is started, do a schedule */ + rt_schedule(); + } + } + else + { + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } +} +RTM_EXPORT(rt_exit_critical); + +/** + * Get the scheduler lock level + * + * @return the level of the scheduler lock. 0 means unlocked. + */ +rt_uint16_t rt_critical_level(void) +{ + return rt_scheduler_lock_nest; +} +RTM_EXPORT(rt_critical_level); +/**@}*/ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/slab.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/slab.c new file mode 100644 index 0000000000..f4806ddb60 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/slab.c @@ -0,0 +1,937 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * File : slab.c + * + * Change Logs: + * Date Author Notes + * 2008-07-12 Bernard the first version + * 2010-07-13 Bernard fix RT_ALIGN issue found by kuronca + * 2010-10-23 yi.qiu add module memory allocator + * 2010-12-18 yi.qiu fix zone release bug + */ + +/* + * KERN_SLABALLOC.C - Kernel SLAB memory allocator + * + * Copyright (c) 2003,2004 The DragonFly Project. All rights reserved. + * + * This code is derived from software contributed to The DragonFly Project + * by Matthew Dillon + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name of The DragonFly Project nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific, prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +#include + +#define RT_MEM_STATS + +#if defined (RT_USING_HEAP) && defined (RT_USING_SLAB) +/* some statistical variable */ +#ifdef RT_MEM_STATS +static rt_size_t used_mem, max_mem; +#endif + +#ifdef RT_USING_HOOK +static void (*rt_malloc_hook)(void *ptr, rt_size_t size); +static void (*rt_free_hook)(void *ptr); + +/** + * @addtogroup Hook + */ + +/**@{*/ + +/** + * This function will set a hook function, which will be invoked when a memory + * block is allocated from heap memory. + * + * @param hook the hook function + */ +void rt_malloc_sethook(void (*hook)(void *ptr, rt_size_t size)) +{ + rt_malloc_hook = hook; +} +RTM_EXPORT(rt_malloc_sethook); + +/** + * This function will set a hook function, which will be invoked when a memory + * block is released to heap memory. + * + * @param hook the hook function + */ +void rt_free_sethook(void (*hook)(void *ptr)) +{ + rt_free_hook = hook; +} +RTM_EXPORT(rt_free_sethook); + +/**@}*/ + +#endif + +/* + * slab allocator implementation + * + * A slab allocator reserves a ZONE for each chunk size, then lays the + * chunks out in an array within the zone. Allocation and deallocation + * is nearly instantanious, and fragmentation/overhead losses are limited + * to a fixed worst-case amount. + * + * The downside of this slab implementation is in the chunk size + * multiplied by the number of zones. ~80 zones * 128K = 10MB of VM per cpu. + * In a kernel implementation all this memory will be physical so + * the zone size is adjusted downward on machines with less physical + * memory. The upside is that overhead is bounded... this is the *worst* + * case overhead. + * + * Slab management is done on a per-cpu basis and no locking or mutexes + * are required, only a critical section. When one cpu frees memory + * belonging to another cpu's slab manager an asynchronous IPI message + * will be queued to execute the operation. In addition, both the + * high level slab allocator and the low level zone allocator optimize + * M_ZERO requests, and the slab allocator does not have to pre initialize + * the linked list of chunks. + * + * XXX Balancing is needed between cpus. Balance will be handled through + * asynchronous IPIs primarily by reassigning the z_Cpu ownership of chunks. + * + * XXX If we have to allocate a new zone and M_USE_RESERVE is set, use of + * the new zone should be restricted to M_USE_RESERVE requests only. + * + * Alloc Size Chunking Number of zones + * 0-127 8 16 + * 128-255 16 8 + * 256-511 32 8 + * 512-1023 64 8 + * 1024-2047 128 8 + * 2048-4095 256 8 + * 4096-8191 512 8 + * 8192-16383 1024 8 + * 16384-32767 2048 8 + * (if RT_MM_PAGE_SIZE is 4K the maximum zone allocation is 16383) + * + * Allocations >= zone_limit go directly to kmem. + * + * API REQUIREMENTS AND SIDE EFFECTS + * + * To operate as a drop-in replacement to the FreeBSD-4.x malloc() we + * have remained compatible with the following API requirements: + * + * + small power-of-2 sized allocations are power-of-2 aligned (kern_tty) + * + all power-of-2 sized allocations are power-of-2 aligned (twe) + * + malloc(0) is allowed and returns non-RT_NULL (ahc driver) + * + ability to allocate arbitrarily large chunks of memory + */ + +/* + * Chunk structure for free elements + */ +typedef struct slab_chunk +{ + struct slab_chunk *c_next; +} slab_chunk; + +/* + * The IN-BAND zone header is placed at the beginning of each zone. + */ +typedef struct slab_zone +{ + rt_int32_t z_magic; /* magic number for sanity check */ + rt_int32_t z_nfree; /* total free chunks / ualloc space in zone */ + rt_int32_t z_nmax; /* maximum free chunks */ + + struct slab_zone *z_next; /* zoneary[] link if z_nfree non-zero */ + rt_uint8_t *z_baseptr; /* pointer to start of chunk array */ + + rt_int32_t z_uindex; /* current initial allocation index */ + rt_int32_t z_chunksize; /* chunk size for validation */ + + rt_int32_t z_zoneindex; /* zone index */ + slab_chunk *z_freechunk; /* free chunk list */ +} slab_zone; + +#define ZALLOC_SLAB_MAGIC 0x51ab51ab +#define ZALLOC_ZONE_LIMIT (16 * 1024) /* max slab-managed alloc */ +#define ZALLOC_MIN_ZONE_SIZE (32 * 1024) /* minimum zone size */ +#define ZALLOC_MAX_ZONE_SIZE (128 * 1024) /* maximum zone size */ +#define NZONES 72 /* number of zones */ +#define ZONE_RELEASE_THRESH 2 /* threshold number of zones */ + +static slab_zone *zone_array[NZONES]; /* linked list of zones NFree > 0 */ +static slab_zone *zone_free; /* whole zones that have become free */ + +static int zone_free_cnt; +static int zone_size; +static int zone_limit; +static int zone_page_cnt; + +/* + * Misc constants. Note that allocations that are exact multiples of + * RT_MM_PAGE_SIZE, or exceed the zone limit, fall through to the kmem module. + */ +#define MIN_CHUNK_SIZE 8 /* in bytes */ +#define MIN_CHUNK_MASK (MIN_CHUNK_SIZE - 1) + +/* + * Array of descriptors that describe the contents of each page + */ +#define PAGE_TYPE_FREE 0x00 +#define PAGE_TYPE_SMALL 0x01 +#define PAGE_TYPE_LARGE 0x02 +struct memusage +{ + rt_uint32_t type: 2 ; /* page type */ + rt_uint32_t size: 30; /* pages allocated or offset from zone */ +}; +static struct memusage *memusage = RT_NULL; +#define btokup(addr) \ + (&memusage[((rt_uint32_t)(addr) - heap_start) >> RT_MM_PAGE_BITS]) + +static rt_uint32_t heap_start, heap_end; + +/* page allocator */ +struct rt_page_head +{ + struct rt_page_head *next; /* next valid page */ + rt_size_t page; /* number of page */ + + /* dummy */ + char dummy[RT_MM_PAGE_SIZE - (sizeof(struct rt_page_head *) + sizeof(rt_size_t))]; +}; +static struct rt_page_head *rt_page_list; +static struct rt_semaphore heap_sem; + +void *rt_page_alloc(rt_size_t npages) +{ + struct rt_page_head *b, *n; + struct rt_page_head **prev; + + if (npages == 0) + return RT_NULL; + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + for (prev = &rt_page_list; (b = *prev) != RT_NULL; prev = &(b->next)) + { + if (b->page > npages) + { + /* splite pages */ + n = b + npages; + n->next = b->next; + n->page = b->page - npages; + *prev = n; + break; + } + + if (b->page == npages) + { + /* this node fit, remove this node */ + *prev = b->next; + break; + } + } + + /* unlock heap */ + rt_sem_release(&heap_sem); + + return b; +} + +void rt_page_free(void *addr, rt_size_t npages) +{ + struct rt_page_head *b, *n; + struct rt_page_head **prev; + + RT_ASSERT(addr != RT_NULL); + RT_ASSERT((rt_uint32_t)addr % RT_MM_PAGE_SIZE == 0); + RT_ASSERT(npages != 0); + + n = (struct rt_page_head *)addr; + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + for (prev = &rt_page_list; (b = *prev) != RT_NULL; prev = &(b->next)) + { + RT_ASSERT(b->page > 0); + RT_ASSERT(b > n || b + b->page <= n); + + if (b + b->page == n) + { + if (b + (b->page += npages) == b->next) + { + b->page += b->next->page; + b->next = b->next->next; + } + + goto _return; + } + + if (b == n + npages) + { + n->page = b->page + npages; + n->next = b->next; + *prev = n; + + goto _return; + } + + if (b > n + npages) + break; + } + + n->page = npages; + n->next = b; + *prev = n; + +_return: + /* unlock heap */ + rt_sem_release(&heap_sem); +} + +/* + * Initialize the page allocator + */ +static void rt_page_init(void *addr, rt_size_t npages) +{ + RT_ASSERT(addr != RT_NULL); + RT_ASSERT(npages != 0); + + rt_page_list = RT_NULL; + rt_page_free(addr, npages); +} + +/** + * @ingroup SystemInit + * + * This function will init system heap + * + * @param begin_addr the beginning address of system page + * @param end_addr the end address of system page + */ +void rt_system_heap_init(void *begin_addr, void *end_addr) +{ + rt_uint32_t limsize, npages; + + RT_DEBUG_NOT_IN_INTERRUPT; + + /* align begin and end addr to page */ + heap_start = RT_ALIGN((rt_uint32_t)begin_addr, RT_MM_PAGE_SIZE); + heap_end = RT_ALIGN_DOWN((rt_uint32_t)end_addr, RT_MM_PAGE_SIZE); + + if (heap_start >= heap_end) + { + rt_kprintf("rt_system_heap_init, wrong address[0x%x - 0x%x]\n", + (rt_uint32_t)begin_addr, (rt_uint32_t)end_addr); + + return; + } + + limsize = heap_end - heap_start; + npages = limsize / RT_MM_PAGE_SIZE; + + /* initialize heap semaphore */ + rt_sem_init(&heap_sem, "heap", 1, RT_IPC_FLAG_FIFO); + + RT_DEBUG_LOG(RT_DEBUG_SLAB, ("heap[0x%x - 0x%x], size 0x%x, 0x%x pages\n", + heap_start, heap_end, limsize, npages)); + + /* init pages */ + rt_page_init((void *)heap_start, npages); + + /* calculate zone size */ + zone_size = ZALLOC_MIN_ZONE_SIZE; + while (zone_size < ZALLOC_MAX_ZONE_SIZE && (zone_size << 1) < (limsize / 1024)) + zone_size <<= 1; + + zone_limit = zone_size / 4; + if (zone_limit > ZALLOC_ZONE_LIMIT) + zone_limit = ZALLOC_ZONE_LIMIT; + + zone_page_cnt = zone_size / RT_MM_PAGE_SIZE; + + RT_DEBUG_LOG(RT_DEBUG_SLAB, ("zone size 0x%x, zone page count 0x%x\n", + zone_size, zone_page_cnt)); + + /* allocate memusage array */ + limsize = npages * sizeof(struct memusage); + limsize = RT_ALIGN(limsize, RT_MM_PAGE_SIZE); + memusage = rt_page_alloc(limsize / RT_MM_PAGE_SIZE); + + RT_DEBUG_LOG(RT_DEBUG_SLAB, ("memusage 0x%x, size 0x%x\n", + (rt_uint32_t)memusage, limsize)); +} + +/* + * Calculate the zone index for the allocation request size and set the + * allocation request size to that particular zone's chunk size. + */ +rt_inline int zoneindex(rt_size_t *bytes) +{ + /* unsigned for shift opt */ + rt_uint32_t n = (rt_uint32_t)(*bytes); + + if (n < 128) + { + *bytes = n = (n + 7) & ~7; + + /* 8 byte chunks, 16 zones */ + return (n / 8 - 1); + } + if (n < 256) + { + *bytes = n = (n + 15) & ~15; + + return (n / 16 + 7); + } + if (n < 8192) + { + if (n < 512) + { + *bytes = n = (n + 31) & ~31; + + return (n / 32 + 15); + } + if (n < 1024) + { + *bytes = n = (n + 63) & ~63; + + return (n / 64 + 23); + } + if (n < 2048) + { + *bytes = n = (n + 127) & ~127; + + return (n / 128 + 31); + } + if (n < 4096) + { + *bytes = n = (n + 255) & ~255; + + return (n / 256 + 39); + } + *bytes = n = (n + 511) & ~511; + + return (n / 512 + 47); + } + if (n < 16384) + { + *bytes = n = (n + 1023) & ~1023; + + return (n / 1024 + 55); + } + + rt_kprintf("Unexpected byte count %d", n); + + return 0; +} + +/** + * @addtogroup MM + */ + +/**@{*/ + +/** + * This function will allocate a block from system heap memory. + * - If the nbytes is less than zero, + * or + * - If there is no nbytes sized memory valid in system, + * the RT_NULL is returned. + * + * @param size the size of memory to be allocated + * + * @return the allocated memory + */ +void *rt_malloc(rt_size_t size) +{ + slab_zone *z; + rt_int32_t zi; + slab_chunk *chunk; + struct memusage *kup; + + /* zero size, return RT_NULL */ + if (size == 0) + return RT_NULL; + + /* + * Handle large allocations directly. There should not be very many of + * these so performance is not a big issue. + */ + if (size >= zone_limit) + { + size = RT_ALIGN(size, RT_MM_PAGE_SIZE); + + chunk = rt_page_alloc(size >> RT_MM_PAGE_BITS); + if (chunk == RT_NULL) + return RT_NULL; + + /* set kup */ + kup = btokup(chunk); + kup->type = PAGE_TYPE_LARGE; + kup->size = size >> RT_MM_PAGE_BITS; + + RT_DEBUG_LOG(RT_DEBUG_SLAB, + ("malloc a large memory 0x%x, page cnt %d, kup %d\n", + size, + size >> RT_MM_PAGE_BITS, + ((rt_uint32_t)chunk - heap_start) >> RT_MM_PAGE_BITS)); + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + +#ifdef RT_MEM_STATS + used_mem += size; + if (used_mem > max_mem) + max_mem = used_mem; +#endif + goto done; + } + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + /* + * Attempt to allocate out of an existing zone. First try the free list, + * then allocate out of unallocated space. If we find a good zone move + * it to the head of the list so later allocations find it quickly + * (we might have thousands of zones in the list). + * + * Note: zoneindex() will panic of size is too large. + */ + zi = zoneindex(&size); + RT_ASSERT(zi < NZONES); + + RT_DEBUG_LOG(RT_DEBUG_SLAB, ("try to malloc 0x%x on zone: %d\n", size, zi)); + + if ((z = zone_array[zi]) != RT_NULL) + { + RT_ASSERT(z->z_nfree > 0); + + /* Remove us from the zone_array[] when we become empty */ + if (--z->z_nfree == 0) + { + zone_array[zi] = z->z_next; + z->z_next = RT_NULL; + } + + /* + * No chunks are available but nfree said we had some memory, so + * it must be available in the never-before-used-memory area + * governed by uindex. The consequences are very serious if our zone + * got corrupted so we use an explicit rt_kprintf rather then a KASSERT. + */ + if (z->z_uindex + 1 != z->z_nmax) + { + z->z_uindex = z->z_uindex + 1; + chunk = (slab_chunk *)(z->z_baseptr + z->z_uindex * size); + } + else + { + /* find on free chunk list */ + chunk = z->z_freechunk; + + /* remove this chunk from list */ + z->z_freechunk = z->z_freechunk->c_next; + } + +#ifdef RT_MEM_STATS + used_mem += z->z_chunksize; + if (used_mem > max_mem) + max_mem = used_mem; +#endif + + goto done; + } + + /* + * If all zones are exhausted we need to allocate a new zone for this + * index. + * + * At least one subsystem, the tty code (see CROUND) expects power-of-2 + * allocations to be power-of-2 aligned. We maintain compatibility by + * adjusting the base offset below. + */ + { + rt_int32_t off; + + if ((z = zone_free) != RT_NULL) + { + /* remove zone from free zone list */ + zone_free = z->z_next; + -- zone_free_cnt; + } + else + { + /* unlock heap, since page allocator will think about lock */ + rt_sem_release(&heap_sem); + + /* allocate a zone from page */ + z = rt_page_alloc(zone_size / RT_MM_PAGE_SIZE); + if (z == RT_NULL) + { + chunk = RT_NULL; + goto __exit; + } + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + RT_DEBUG_LOG(RT_DEBUG_SLAB, ("alloc a new zone: 0x%x\n", + (rt_uint32_t)z)); + + /* set message usage */ + for (off = 0, kup = btokup(z); off < zone_page_cnt; off ++) + { + kup->type = PAGE_TYPE_SMALL; + kup->size = off; + + kup ++; + } + } + + /* clear to zero */ + rt_memset(z, 0, sizeof(slab_zone)); + + /* offset of slab zone struct in zone */ + off = sizeof(slab_zone); + + /* + * Guarentee power-of-2 alignment for power-of-2-sized chunks. + * Otherwise just 8-byte align the data. + */ + if ((size | (size - 1)) + 1 == (size << 1)) + off = (off + size - 1) & ~(size - 1); + else + off = (off + MIN_CHUNK_MASK) & ~MIN_CHUNK_MASK; + + z->z_magic = ZALLOC_SLAB_MAGIC; + z->z_zoneindex = zi; + z->z_nmax = (zone_size - off) / size; + z->z_nfree = z->z_nmax - 1; + z->z_baseptr = (rt_uint8_t *)z + off; + z->z_uindex = 0; + z->z_chunksize = size; + + chunk = (slab_chunk *)(z->z_baseptr + z->z_uindex * size); + + /* link to zone array */ + z->z_next = zone_array[zi]; + zone_array[zi] = z; + +#ifdef RT_MEM_STATS + used_mem += z->z_chunksize; + if (used_mem > max_mem) + max_mem = used_mem; +#endif + } + +done: + rt_sem_release(&heap_sem); + RT_OBJECT_HOOK_CALL(rt_malloc_hook, ((char *)chunk, size)); + +__exit: + return chunk; +} +RTM_EXPORT(rt_malloc); + +/** + * This function will change the size of previously allocated memory block. + * + * @param ptr the previously allocated memory block + * @param size the new size of memory block + * + * @return the allocated memory + */ +void *rt_realloc(void *ptr, rt_size_t size) +{ + void *nptr; + slab_zone *z; + struct memusage *kup; + + if (ptr == RT_NULL) + return rt_malloc(size); + if (size == 0) + { + rt_free(ptr); + + return RT_NULL; + } + + /* + * Get the original allocation's zone. If the new request winds up + * using the same chunk size we do not have to do anything. + */ + kup = btokup((rt_uint32_t)ptr & ~RT_MM_PAGE_MASK); + if (kup->type == PAGE_TYPE_LARGE) + { + rt_size_t osize; + + osize = kup->size << RT_MM_PAGE_BITS; + if ((nptr = rt_malloc(size)) == RT_NULL) + return RT_NULL; + rt_memcpy(nptr, ptr, size > osize ? osize : size); + rt_free(ptr); + + return nptr; + } + else if (kup->type == PAGE_TYPE_SMALL) + { + z = (slab_zone *)(((rt_uint32_t)ptr & ~RT_MM_PAGE_MASK) - + kup->size * RT_MM_PAGE_SIZE); + RT_ASSERT(z->z_magic == ZALLOC_SLAB_MAGIC); + + zoneindex(&size); + if (z->z_chunksize == size) + return (ptr); /* same chunk */ + + /* + * Allocate memory for the new request size. Note that zoneindex has + * already adjusted the request size to the appropriate chunk size, which + * should optimize our bcopy(). Then copy and return the new pointer. + */ + if ((nptr = rt_malloc(size)) == RT_NULL) + return RT_NULL; + + rt_memcpy(nptr, ptr, size > z->z_chunksize ? z->z_chunksize : size); + rt_free(ptr); + + return nptr; + } + + return RT_NULL; +} +RTM_EXPORT(rt_realloc); + +/** + * This function will contiguously allocate enough space for count objects + * that are size bytes of memory each and returns a pointer to the allocated + * memory. + * + * The allocated memory is filled with bytes of value zero. + * + * @param count number of objects to allocate + * @param size size of the objects to allocate + * + * @return pointer to allocated memory / NULL pointer if there is an error + */ +void *rt_calloc(rt_size_t count, rt_size_t size) +{ + void *p; + + /* allocate 'count' objects of size 'size' */ + p = rt_malloc(count * size); + + /* zero the memory */ + if (p) + rt_memset(p, 0, count * size); + + return p; +} +RTM_EXPORT(rt_calloc); + +/** + * This function will release the previous allocated memory block by rt_malloc. + * The released memory block is taken back to system heap. + * + * @param ptr the address of memory which will be released + */ +void rt_free(void *ptr) +{ + slab_zone *z; + slab_chunk *chunk; + struct memusage *kup; + + /* free a RT_NULL pointer */ + if (ptr == RT_NULL) + return ; + + RT_OBJECT_HOOK_CALL(rt_free_hook, (ptr)); + + /* get memory usage */ +#if RT_DEBUG_SLAB + { + rt_uint32_t addr = ((rt_uint32_t)ptr & ~RT_MM_PAGE_MASK); + RT_DEBUG_LOG(RT_DEBUG_SLAB, + ("free a memory 0x%x and align to 0x%x, kup index %d\n", + (rt_uint32_t)ptr, + (rt_uint32_t)addr, + ((rt_uint32_t)(addr) - heap_start) >> RT_MM_PAGE_BITS)); + } +#endif + + kup = btokup((rt_uint32_t)ptr & ~RT_MM_PAGE_MASK); + /* release large allocation */ + if (kup->type == PAGE_TYPE_LARGE) + { + rt_uint32_t size; + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + /* clear page counter */ + size = kup->size; + kup->size = 0; + +#ifdef RT_MEM_STATS + used_mem -= size * RT_MM_PAGE_SIZE; +#endif + rt_sem_release(&heap_sem); + + RT_DEBUG_LOG(RT_DEBUG_SLAB, + ("free large memory block 0x%x, page count %d\n", + (rt_uint32_t)ptr, size)); + + /* free this page */ + rt_page_free(ptr, size); + + return; + } + + /* lock heap */ + rt_sem_take(&heap_sem, RT_WAITING_FOREVER); + + /* zone case. get out zone. */ + z = (slab_zone *)(((rt_uint32_t)ptr & ~RT_MM_PAGE_MASK) - + kup->size * RT_MM_PAGE_SIZE); + RT_ASSERT(z->z_magic == ZALLOC_SLAB_MAGIC); + + chunk = (slab_chunk *)ptr; + chunk->c_next = z->z_freechunk; + z->z_freechunk = chunk; + +#ifdef RT_MEM_STATS + used_mem -= z->z_chunksize; +#endif + + /* + * Bump the number of free chunks. If it becomes non-zero the zone + * must be added back onto the appropriate list. + */ + if (z->z_nfree++ == 0) + { + z->z_next = zone_array[z->z_zoneindex]; + zone_array[z->z_zoneindex] = z; + } + + /* + * If the zone becomes totally free, and there are other zones we + * can allocate from, move this zone to the FreeZones list. Since + * this code can be called from an IPI callback, do *NOT* try to mess + * with kernel_map here. Hysteresis will be performed at malloc() time. + */ + if (z->z_nfree == z->z_nmax && + (z->z_next || zone_array[z->z_zoneindex] != z)) + { + slab_zone **pz; + + RT_DEBUG_LOG(RT_DEBUG_SLAB, ("free zone 0x%x\n", + (rt_uint32_t)z, z->z_zoneindex)); + + /* remove zone from zone array list */ + for (pz = &zone_array[z->z_zoneindex]; z != *pz; pz = &(*pz)->z_next) + ; + *pz = z->z_next; + + /* reset zone */ + z->z_magic = -1; + + /* insert to free zone list */ + z->z_next = zone_free; + zone_free = z; + + ++ zone_free_cnt; + + /* release zone to page allocator */ + if (zone_free_cnt > ZONE_RELEASE_THRESH) + { + register rt_base_t i; + + z = zone_free; + zone_free = z->z_next; + -- zone_free_cnt; + + /* set message usage */ + for (i = 0, kup = btokup(z); i < zone_page_cnt; i ++) + { + kup->type = PAGE_TYPE_FREE; + kup->size = 0; + kup ++; + } + + /* unlock heap */ + rt_sem_release(&heap_sem); + + /* release pages */ + rt_page_free(z, zone_size / RT_MM_PAGE_SIZE); + + return; + } + } + /* unlock heap */ + rt_sem_release(&heap_sem); +} +RTM_EXPORT(rt_free); + +#ifdef RT_MEM_STATS +void rt_memory_info(rt_uint32_t *total, + rt_uint32_t *used, + rt_uint32_t *max_used) +{ + if (total != RT_NULL) + *total = heap_end - heap_start; + + if (used != RT_NULL) + *used = used_mem; + + if (max_used != RT_NULL) + *max_used = max_mem; +} + +#ifdef RT_USING_FINSH +#include + +void list_mem(void) +{ + rt_kprintf("total memory: %d\n", heap_end - heap_start); + rt_kprintf("used memory : %d\n", used_mem); + rt_kprintf("maximum allocated memory: %d\n", max_mem); +} +FINSH_FUNCTION_EXPORT(list_mem, list memory usage information) +#endif +#endif + +/**@}*/ + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/thread.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/thread.c new file mode 100644 index 0000000000..940d24e6f2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/thread.c @@ -0,0 +1,802 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-28 Bernard first version + * 2006-04-29 Bernard implement thread timer + * 2006-04-30 Bernard added THREAD_DEBUG + * 2006-05-27 Bernard fixed the rt_thread_yield bug + * 2006-06-03 Bernard fixed the thread timer init bug + * 2006-08-10 Bernard fixed the timer bug in thread_sleep + * 2006-09-03 Bernard changed rt_timer_delete to rt_timer_detach + * 2006-09-03 Bernard implement rt_thread_detach + * 2008-02-16 Bernard fixed the rt_thread_timeout bug + * 2010-03-21 Bernard change the errno of rt_thread_delay/sleep to + * RT_EOK. + * 2010-11-10 Bernard add cleanup callback function in thread exit. + * 2011-09-01 Bernard fixed rt_thread_exit issue when the current + * thread preempted, which reported by Jiaxing Lee. + * 2011-09-08 Bernard fixed the scheduling issue in rt_thread_startup. + * 2012-12-29 Bernard fixed compiling warning. + * 2016-08-09 ArdaFu add thread suspend and resume hook. + * 2017-04-10 armink fixed the rt_thread_delete and rt_thread_detach + bug when thread has not startup. + */ + +#include +#include + +extern rt_list_t rt_thread_priority_table[RT_THREAD_PRIORITY_MAX]; +extern struct rt_thread *rt_current_thread; +extern rt_list_t rt_thread_defunct; + +#ifdef RT_USING_HOOK + +static void (*rt_thread_suspend_hook)(rt_thread_t thread); +static void (*rt_thread_resume_hook) (rt_thread_t thread); +static void (*rt_thread_inited_hook) (rt_thread_t thread); + +/** + * @ingroup Hook + * This function sets a hook function when the system suspend a thread. + * + * @param hook the specified hook function + * + * @note the hook function must be simple and never be blocked or suspend. + */ +void rt_thread_suspend_sethook(void (*hook)(rt_thread_t thread)) +{ + rt_thread_suspend_hook = hook; +} + +/** + * @ingroup Hook + * This function sets a hook function when the system resume a thread. + * + * @param hook the specified hook function + * + * @note the hook function must be simple and never be blocked or suspend. + */ +void rt_thread_resume_sethook(void (*hook)(rt_thread_t thread)) +{ + rt_thread_resume_hook = hook; +} + +/** + * @ingroup Hook + * This function sets a hook function when a thread is initialized. + * + * @param hook the specified hook function + */ +void rt_thread_inited_sethook(void (*hook)(rt_thread_t thread)) +{ + rt_thread_inited_hook = hook; +} + +#endif + +void rt_thread_exit(void) +{ + struct rt_thread *thread; + register rt_base_t level; + + /* get current thread */ + thread = rt_current_thread; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* remove from schedule */ + rt_schedule_remove_thread(thread); + /* change stat */ + thread->stat = RT_THREAD_CLOSE; + + /* remove it from timer list */ + rt_timer_detach(&thread->thread_timer); + + if ((rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE) && + thread->cleanup == RT_NULL) + { + rt_object_detach((rt_object_t)thread); + } + else + { + /* insert to defunct thread list */ + rt_list_insert_after(&rt_thread_defunct, &(thread->tlist)); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* switch to next task */ + rt_schedule(); +} + +static rt_err_t _rt_thread_init(struct rt_thread *thread, + const char *name, + void (*entry)(void *parameter), + void *parameter, + void *stack_start, + rt_uint32_t stack_size, + rt_uint8_t priority, + rt_uint32_t tick) +{ + /* init thread list */ + rt_list_init(&(thread->tlist)); + + thread->entry = (void *)entry; + thread->parameter = parameter; + + /* stack init */ + thread->stack_addr = stack_start; + thread->stack_size = stack_size; + + /* init thread stack */ + rt_memset(thread->stack_addr, '#', thread->stack_size); +#ifdef ARCH_CPU_STACK_GROWS_UPWARD + thread->sp = (void *)rt_hw_stack_init(thread->entry, thread->parameter, + (void *)((char *)thread->stack_addr), + (void *)rt_thread_exit); +#else + thread->sp = (void *)rt_hw_stack_init(thread->entry, thread->parameter, + (void *)((char *)thread->stack_addr + thread->stack_size - 4), + (void *)rt_thread_exit); +#endif + + /* priority init */ + RT_ASSERT(priority < RT_THREAD_PRIORITY_MAX); + thread->init_priority = priority; + thread->current_priority = priority; + + thread->number_mask = 0; +#if RT_THREAD_PRIORITY_MAX > 32 + thread->number = 0; + thread->high_mask = 0; +#endif + + /* tick init */ + thread->init_tick = tick; + thread->remaining_tick = tick; + + /* error and flags */ + thread->error = RT_EOK; + thread->stat = RT_THREAD_INIT; + + /* initialize cleanup function and user data */ + thread->cleanup = 0; + thread->user_data = 0; + + /* init thread timer */ + rt_timer_init(&(thread->thread_timer), + thread->name, + rt_thread_timeout, + thread, + 0, + RT_TIMER_FLAG_ONE_SHOT); + + /* initialize signal */ +#ifdef RT_USING_SIGNALS + thread->sig_mask = 0x00; + thread->sig_pending = 0x00; + + thread->sig_ret = RT_NULL; + thread->sig_vectors = RT_NULL; + thread->si_list = RT_NULL; +#endif + +#ifdef RT_USING_LWP + thread->lwp = RT_NULL; +#endif + + RT_OBJECT_HOOK_CALL(rt_thread_inited_hook, (thread)); + + return RT_EOK; +} + +/** + * @addtogroup Thread + */ + +/**@{*/ + +/** + * This function will initialize a thread, normally it's used to initialize a + * static thread object. + * + * @param thread the static thread object + * @param name the name of thread, which shall be unique + * @param entry the entry function of thread + * @param parameter the parameter of thread enter function + * @param stack_start the start address of thread stack + * @param stack_size the size of thread stack + * @param priority the priority of thread + * @param tick the time slice if there are same priority thread + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_thread_init(struct rt_thread *thread, + const char *name, + void (*entry)(void *parameter), + void *parameter, + void *stack_start, + rt_uint32_t stack_size, + rt_uint8_t priority, + rt_uint32_t tick) +{ + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(stack_start != RT_NULL); + + /* init thread object */ + rt_object_init((rt_object_t)thread, RT_Object_Class_Thread, name); + + return _rt_thread_init(thread, + name, + entry, + parameter, + stack_start, + stack_size, + priority, + tick); +} +RTM_EXPORT(rt_thread_init); + +/** + * This function will return self thread object + * + * @return the self thread object + */ +rt_thread_t rt_thread_self(void) +{ + return rt_current_thread; +} +RTM_EXPORT(rt_thread_self); + +/** + * This function will start a thread and put it to system ready queue + * + * @param thread the thread to be started + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_thread_startup(rt_thread_t thread) +{ + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_INIT); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + /* set current priority to init priority */ + thread->current_priority = thread->init_priority; + + /* calculate priority attribute */ +#if RT_THREAD_PRIORITY_MAX > 32 + thread->number = thread->current_priority >> 3; /* 5bit */ + thread->number_mask = 1L << thread->number; + thread->high_mask = 1L << (thread->current_priority & 0x07); /* 3bit */ +#else + thread->number_mask = 1L << thread->current_priority; +#endif + + RT_DEBUG_LOG(RT_DEBUG_THREAD, ("startup a thread:%s with priority:%d\n", + thread->name, thread->init_priority)); + /* change thread stat */ + thread->stat = RT_THREAD_SUSPEND; + /* then resume it */ + rt_thread_resume(thread); + if (rt_thread_self() != RT_NULL) + { + /* do a scheduling */ + rt_schedule(); + } + + return RT_EOK; +} +RTM_EXPORT(rt_thread_startup); + +/** + * This function will detach a thread. The thread object will be removed from + * thread queue and detached/deleted from system object management. + * + * @param thread the thread to be deleted + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_thread_detach(rt_thread_t thread) +{ + rt_base_t lock; + + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + RT_ASSERT(rt_object_is_systemobject((rt_object_t)thread)); + + if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT) + { + /* remove from schedule */ + rt_schedule_remove_thread(thread); + } + + /* release thread timer */ + rt_timer_detach(&(thread->thread_timer)); + + /* change stat */ + thread->stat = RT_THREAD_CLOSE; + + if ((rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE) && + thread->cleanup == RT_NULL) + { + rt_object_detach((rt_object_t)thread); + } + else + { + /* disable interrupt */ + lock = rt_hw_interrupt_disable(); + /* insert to defunct thread list */ + rt_list_insert_after(&rt_thread_defunct, &(thread->tlist)); + /* enable interrupt */ + rt_hw_interrupt_enable(lock); + } + + return RT_EOK; +} +RTM_EXPORT(rt_thread_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a thread object and allocate thread object memory + * and stack. + * + * @param name the name of thread, which shall be unique + * @param entry the entry function of thread + * @param parameter the parameter of thread enter function + * @param stack_size the size of thread stack + * @param priority the priority of thread + * @param tick the time slice if there are same priority thread + * + * @return the created thread object + */ +rt_thread_t rt_thread_create(const char *name, + void (*entry)(void *parameter), + void *parameter, + rt_uint32_t stack_size, + rt_uint8_t priority, + rt_uint32_t tick) +{ + struct rt_thread *thread; + void *stack_start; + + thread = (struct rt_thread *)rt_object_allocate(RT_Object_Class_Thread, + name); + if (thread == RT_NULL) + return RT_NULL; + + stack_start = (void *)RT_KERNEL_MALLOC(stack_size); + if (stack_start == RT_NULL) + { + /* allocate stack failure */ + rt_object_delete((rt_object_t)thread); + + return RT_NULL; + } + + _rt_thread_init(thread, + name, + entry, + parameter, + stack_start, + stack_size, + priority, + tick); + + return thread; +} +RTM_EXPORT(rt_thread_create); + +/** + * This function will delete a thread. The thread object will be removed from + * thread queue and deleted from system object management in the idle thread. + * + * @param thread the thread to be deleted + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_thread_delete(rt_thread_t thread) +{ + rt_base_t lock; + + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + RT_ASSERT(rt_object_is_systemobject((rt_object_t)thread) == RT_FALSE); + + if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT) + { + /* remove from schedule */ + rt_schedule_remove_thread(thread); + } + + /* release thread timer */ + rt_timer_detach(&(thread->thread_timer)); + + /* change stat */ + thread->stat = RT_THREAD_CLOSE; + + /* disable interrupt */ + lock = rt_hw_interrupt_disable(); + + /* insert to defunct thread list */ + rt_list_insert_after(&rt_thread_defunct, &(thread->tlist)); + + /* enable interrupt */ + rt_hw_interrupt_enable(lock); + + return RT_EOK; +} +RTM_EXPORT(rt_thread_delete); +#endif + +/** + * This function will let current thread yield processor, and scheduler will + * choose a highest thread to run. After yield processor, the current thread + * is still in READY state. + * + * @return RT_EOK + */ +rt_err_t rt_thread_yield(void) +{ + register rt_base_t level; + struct rt_thread *thread; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* set to current thread */ + thread = rt_current_thread; + + /* if the thread stat is READY and on ready queue list */ + if ((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_READY && + thread->tlist.next != thread->tlist.prev) + { + /* remove thread from thread list */ + rt_list_remove(&(thread->tlist)); + + /* put thread to end of ready queue */ + rt_list_insert_before(&(rt_thread_priority_table[thread->current_priority]), + &(thread->tlist)); + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_schedule(); + + return RT_EOK; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +RTM_EXPORT(rt_thread_yield); + +/** + * This function will let current thread sleep for some ticks. + * + * @param tick the sleep ticks + * + * @return RT_EOK + */ +rt_err_t rt_thread_sleep(rt_tick_t tick) +{ + register rt_base_t temp; + struct rt_thread *thread; + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + /* set to current thread */ + thread = rt_current_thread; + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + /* suspend thread */ + rt_thread_suspend(thread); + + /* reset the timeout of thread timer and start it */ + rt_timer_control(&(thread->thread_timer), RT_TIMER_CTRL_SET_TIME, &tick); + rt_timer_start(&(thread->thread_timer)); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + rt_schedule(); + + /* clear error number of this thread to RT_EOK */ + if (thread->error == -RT_ETIMEOUT) + thread->error = RT_EOK; + + return RT_EOK; +} + +/** + * This function will let current thread delay for some ticks. + * + * @param tick the delay ticks + * + * @return RT_EOK + */ +rt_err_t rt_thread_delay(rt_tick_t tick) +{ + return rt_thread_sleep(tick); +} +RTM_EXPORT(rt_thread_delay); + +/** + * This function will let current thread delay for some milliseconds. + * + * @param tick the delay time + * + * @return RT_EOK + */ +rt_err_t rt_thread_mdelay(rt_int32_t ms) +{ + rt_tick_t tick; + + tick = rt_tick_from_millisecond(ms); + + return rt_thread_sleep(tick); +} +RTM_EXPORT(rt_thread_mdelay); + +/** + * This function will control thread behaviors according to control command. + * + * @param thread the specified thread to be controlled + * @param cmd the control command, which includes + * RT_THREAD_CTRL_CHANGE_PRIORITY for changing priority level of thread; + * RT_THREAD_CTRL_STARTUP for starting a thread; + * RT_THREAD_CTRL_CLOSE for delete a thread. + * @param arg the argument of control command + * + * @return RT_EOK + */ +rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg) +{ + register rt_base_t temp; + + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + switch (cmd) + { + case RT_THREAD_CTRL_CHANGE_PRIORITY: + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* for ready thread, change queue */ + if ((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_READY) + { + /* remove thread from schedule queue first */ + rt_schedule_remove_thread(thread); + + /* change thread priority */ + thread->current_priority = *(rt_uint8_t *)arg; + + /* recalculate priority attribute */ +#if RT_THREAD_PRIORITY_MAX > 32 + thread->number = thread->current_priority >> 3; /* 5bit */ + thread->number_mask = 1 << thread->number; + thread->high_mask = 1 << (thread->current_priority & 0x07); /* 3bit */ +#else + thread->number_mask = 1 << thread->current_priority; +#endif + + /* insert thread to schedule queue again */ + rt_schedule_insert_thread(thread); + } + else + { + thread->current_priority = *(rt_uint8_t *)arg; + + /* recalculate priority attribute */ +#if RT_THREAD_PRIORITY_MAX > 32 + thread->number = thread->current_priority >> 3; /* 5bit */ + thread->number_mask = 1 << thread->number; + thread->high_mask = 1 << (thread->current_priority & 0x07); /* 3bit */ +#else + thread->number_mask = 1 << thread->current_priority; +#endif + } + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + break; + + case RT_THREAD_CTRL_STARTUP: + return rt_thread_startup(thread); + +#ifdef RT_USING_HEAP + case RT_THREAD_CTRL_CLOSE: + return rt_thread_delete(thread); +#endif + + default: + break; + } + + return RT_EOK; +} +RTM_EXPORT(rt_thread_control); + +/** + * This function will suspend the specified thread. + * + * @param thread the thread to be suspended + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + * + * @note if suspend self thread, after this function call, the + * rt_schedule() must be invoked. + */ +rt_err_t rt_thread_suspend(rt_thread_t thread) +{ + register rt_base_t temp; + + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + RT_DEBUG_LOG(RT_DEBUG_THREAD, ("thread suspend: %s\n", thread->name)); + + if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_READY) + { + RT_DEBUG_LOG(RT_DEBUG_THREAD, ("thread suspend: thread disorder, 0x%2x\n", + thread->stat)); + + return -RT_ERROR; + } + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* change thread stat */ + thread->stat = RT_THREAD_SUSPEND | (thread->stat & ~RT_THREAD_STAT_MASK); + rt_schedule_remove_thread(thread); + + /* stop thread timer anyway */ + rt_timer_stop(&(thread->thread_timer)); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + RT_OBJECT_HOOK_CALL(rt_thread_suspend_hook, (thread)); + return RT_EOK; +} +RTM_EXPORT(rt_thread_suspend); + +/** + * This function will resume a thread and put it to system ready queue. + * + * @param thread the thread to be resumed + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_thread_resume(rt_thread_t thread) +{ + register rt_base_t temp; + + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + RT_DEBUG_LOG(RT_DEBUG_THREAD, ("thread resume: %s\n", thread->name)); + + if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_SUSPEND) + { + RT_DEBUG_LOG(RT_DEBUG_THREAD, ("thread resume: thread disorder, %d\n", + thread->stat)); + + return -RT_ERROR; + } + + /* disable interrupt */ + temp = rt_hw_interrupt_disable(); + + /* remove from suspend list */ + rt_list_remove(&(thread->tlist)); + + rt_timer_stop(&thread->thread_timer); + + /* enable interrupt */ + rt_hw_interrupt_enable(temp); + + /* insert to schedule ready list */ + rt_schedule_insert_thread(thread); + + RT_OBJECT_HOOK_CALL(rt_thread_resume_hook, (thread)); + return RT_EOK; +} +RTM_EXPORT(rt_thread_resume); + +/** + * This function is the timeout function for thread, normally which is invoked + * when thread is timeout to wait some resource. + * + * @param parameter the parameter of thread timeout function + */ +void rt_thread_timeout(void *parameter) +{ + struct rt_thread *thread; + + thread = (struct rt_thread *)parameter; + + /* thread check */ + RT_ASSERT(thread != RT_NULL); + RT_ASSERT((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND); + RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); + + /* set error number */ + thread->error = -RT_ETIMEOUT; + + /* remove from suspend list */ + rt_list_remove(&(thread->tlist)); + + /* insert to schedule ready list */ + rt_schedule_insert_thread(thread); + + /* do schedule */ + rt_schedule(); +} +RTM_EXPORT(rt_thread_timeout); + +/** + * This function will find the specified thread. + * + * @param name the name of thread finding + * + * @return the found thread + * + * @note please don't invoke this function in interrupt status. + */ +rt_thread_t rt_thread_find(char *name) +{ + struct rt_object_information *information; + struct rt_object *object; + struct rt_list_node *node; + + /* enter critical */ + if (rt_thread_self() != RT_NULL) + rt_enter_critical(); + + /* try to find device object */ + information = rt_object_get_information(RT_Object_Class_Thread); + RT_ASSERT(information != RT_NULL); + for (node = information->object_list.next; + node != &(information->object_list); + node = node->next) + { + object = rt_list_entry(node, struct rt_object, list); + if (rt_strncmp(object->name, name, RT_NAME_MAX) == 0) + { + /* leave critical */ + if (rt_thread_self() != RT_NULL) + rt_exit_critical(); + + return (rt_thread_t)object; + } + } + + /* leave critical */ + if (rt_thread_self() != RT_NULL) + rt_exit_critical(); + + /* not found */ + return RT_NULL; +} +RTM_EXPORT(rt_thread_find); + +/**@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/timer.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/timer.c new file mode 100644 index 0000000000..fd938065db --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/rtthread/src/timer.c @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-03-12 Bernard first version + * 2006-04-29 Bernard implement thread timer + * 2006-06-04 Bernard implement rt_timer_control + * 2006-08-10 Bernard fix the periodic timer bug + * 2006-09-03 Bernard implement rt_timer_detach + * 2009-11-11 LiJin add soft timer + * 2010-05-12 Bernard fix the timer check bug. + * 2010-11-02 Charlie re-implement tick overflow issue + * 2012-12-15 Bernard fix the next timeout issue in soft timer + * 2014-07-12 Bernard does not lock scheduler when invoking soft-timer + * timeout function. + */ + +#include +#include + +/* hard timer list */ +static rt_list_t rt_timer_list[RT_TIMER_SKIP_LIST_LEVEL]; + +#ifdef RT_USING_TIMER_SOFT +#ifndef RT_TIMER_THREAD_STACK_SIZE +#define RT_TIMER_THREAD_STACK_SIZE 512 +#endif + +#ifndef RT_TIMER_THREAD_PRIO +#define RT_TIMER_THREAD_PRIO 0 +#endif + +/* soft timer list */ +static rt_list_t rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL]; +static struct rt_thread timer_thread; +ALIGN(RT_ALIGN_SIZE) +static rt_uint8_t timer_thread_stack[RT_TIMER_THREAD_STACK_SIZE]; +#endif + +#ifdef RT_USING_HOOK +extern void (*rt_object_take_hook)(struct rt_object *object); +extern void (*rt_object_put_hook)(struct rt_object *object); +static void (*rt_timer_enter_hook)(struct rt_timer *timer); +static void (*rt_timer_exit_hook)(struct rt_timer *timer); + +/** + * @addtogroup Hook + */ + +/**@{*/ + +/** + * This function will set a hook function, which will be invoked when enter + * timer timeout callback function. + * + * @param hook the hook function + */ +void rt_timer_enter_sethook(void (*hook)(struct rt_timer *timer)) +{ + rt_timer_enter_hook = hook; +} + +/** + * This function will set a hook function, which will be invoked when exit + * timer timeout callback function. + * + * @param hook the hook function + */ +void rt_timer_exit_sethook(void (*hook)(struct rt_timer *timer)) +{ + rt_timer_exit_hook = hook; +} + +/**@}*/ +#endif + +static void _rt_timer_init(rt_timer_t timer, + void (*timeout)(void *parameter), + void *parameter, + rt_tick_t time, + rt_uint8_t flag) +{ + int i; + + /* set flag */ + timer->parent.flag = flag; + + /* set deactivated */ + timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + + timer->timeout_func = timeout; + timer->parameter = parameter; + + timer->timeout_tick = 0; + timer->init_tick = time; + + /* initialize timer list */ + for (i = 0; i < RT_TIMER_SKIP_LIST_LEVEL; i++) + { + rt_list_init(&(timer->row[i])); + } +} + +/* the fist timer always in the last row */ +static rt_tick_t rt_timer_list_next_timeout(rt_list_t timer_list[]) +{ + struct rt_timer *timer; + + if (rt_list_isempty(&timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1])) + return RT_TICK_MAX; + + timer = rt_list_entry(timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next, + struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]); + + return timer->timeout_tick; +} + +rt_inline void _rt_timer_remove(rt_timer_t timer) +{ + int i; + + for (i = 0; i < RT_TIMER_SKIP_LIST_LEVEL; i++) + { + rt_list_remove(&timer->row[i]); + } +} + +#if RT_DEBUG_TIMER +static int rt_timer_count_height(struct rt_timer *timer) +{ + int i, cnt = 0; + + for (i = 0; i < RT_TIMER_SKIP_LIST_LEVEL; i++) + { + if (!rt_list_isempty(&timer->row[i])) + cnt++; + } + return cnt; +} + +void rt_timer_dump(rt_list_t timer_heads[]) +{ + rt_list_t *list; + + for (list = timer_heads[RT_TIMER_SKIP_LIST_LEVEL - 1].next; + list != &timer_heads[RT_TIMER_SKIP_LIST_LEVEL - 1]; + list = list->next) + { + struct rt_timer *timer = rt_list_entry(list, + struct rt_timer, + row[RT_TIMER_SKIP_LIST_LEVEL - 1]); + rt_kprintf("%d", rt_timer_count_height(timer)); + } + rt_kprintf("\n"); +} +#endif + +/** + * @addtogroup Clock + */ + +/**@{*/ + +/** + * This function will initialize a timer, normally this function is used to + * initialize a static timer object. + * + * @param timer the static timer object + * @param name the name of timer + * @param timeout the timeout function + * @param parameter the parameter of timeout function + * @param time the tick of timer + * @param flag the flag of timer + */ +void rt_timer_init(rt_timer_t timer, + const char *name, + void (*timeout)(void *parameter), + void *parameter, + rt_tick_t time, + rt_uint8_t flag) +{ + /* timer check */ + RT_ASSERT(timer != RT_NULL); + + /* timer object initialization */ + rt_object_init((rt_object_t)timer, RT_Object_Class_Timer, name); + + _rt_timer_init(timer, timeout, parameter, time, flag); +} +RTM_EXPORT(rt_timer_init); + +/** + * This function will detach a timer from timer management. + * + * @param timer the static timer object + * + * @return the operation status, RT_EOK on OK; RT_ERROR on error + */ +rt_err_t rt_timer_detach(rt_timer_t timer) +{ + register rt_base_t level; + + /* timer check */ + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer); + RT_ASSERT(rt_object_is_systemobject(&timer->parent)); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + _rt_timer_remove(timer); + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_object_detach((rt_object_t)timer); + + return RT_EOK; +} +RTM_EXPORT(rt_timer_detach); + +#ifdef RT_USING_HEAP +/** + * This function will create a timer + * + * @param name the name of timer + * @param timeout the timeout function + * @param parameter the parameter of timeout function + * @param time the tick of timer + * @param flag the flag of timer + * + * @return the created timer object + */ +rt_timer_t rt_timer_create(const char *name, + void (*timeout)(void *parameter), + void *parameter, + rt_tick_t time, + rt_uint8_t flag) +{ + struct rt_timer *timer; + + /* allocate a object */ + timer = (struct rt_timer *)rt_object_allocate(RT_Object_Class_Timer, name); + if (timer == RT_NULL) + { + return RT_NULL; + } + + _rt_timer_init(timer, timeout, parameter, time, flag); + + return timer; +} +RTM_EXPORT(rt_timer_create); + +/** + * This function will delete a timer and release timer memory + * + * @param timer the timer to be deleted + * + * @return the operation status, RT_EOK on OK; RT_ERROR on error + */ +rt_err_t rt_timer_delete(rt_timer_t timer) +{ + register rt_base_t level; + + /* timer check */ + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer); + RT_ASSERT(rt_object_is_systemobject(&timer->parent) == RT_FALSE); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + _rt_timer_remove(timer); + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + rt_object_delete((rt_object_t)timer); + + return RT_EOK; +} +RTM_EXPORT(rt_timer_delete); +#endif + +/** + * This function will start the timer + * + * @param timer the timer to be started + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_timer_start(rt_timer_t timer) +{ + unsigned int row_lvl; + rt_list_t *timer_list; + register rt_base_t level; + rt_list_t *row_head[RT_TIMER_SKIP_LIST_LEVEL]; + unsigned int tst_nr; + static unsigned int random_nr; + + /* timer check */ + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer); + + /* stop timer firstly */ + level = rt_hw_interrupt_disable(); + /* remove timer from list */ + _rt_timer_remove(timer); + /* change status of timer */ + timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + rt_hw_interrupt_enable(level); + + RT_OBJECT_HOOK_CALL(rt_object_take_hook, (&(timer->parent))); + + /* + * get timeout tick, + * the max timeout tick shall not great than RT_TICK_MAX/2 + */ + RT_ASSERT(timer->init_tick < RT_TICK_MAX / 2); + timer->timeout_tick = rt_tick_get() + timer->init_tick; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + +#ifdef RT_USING_TIMER_SOFT + if (timer->parent.flag & RT_TIMER_FLAG_SOFT_TIMER) + { + /* insert timer to soft timer list */ + timer_list = rt_soft_timer_list; + } + else +#endif + { + /* insert timer to system timer list */ + timer_list = rt_timer_list; + } + + row_head[0] = &timer_list[0]; + for (row_lvl = 0; row_lvl < RT_TIMER_SKIP_LIST_LEVEL; row_lvl++) + { + for (; row_head[row_lvl] != timer_list[row_lvl].prev; + row_head[row_lvl] = row_head[row_lvl]->next) + { + struct rt_timer *t; + rt_list_t *p = row_head[row_lvl]->next; + + /* fix up the entry pointer */ + t = rt_list_entry(p, struct rt_timer, row[row_lvl]); + + /* If we have two timers that timeout at the same time, it's + * preferred that the timer inserted early get called early. + * So insert the new timer to the end the the some-timeout timer + * list. + */ + if ((t->timeout_tick - timer->timeout_tick) == 0) + { + continue; + } + else if ((t->timeout_tick - timer->timeout_tick) < RT_TICK_MAX / 2) + { + break; + } + } + if (row_lvl != RT_TIMER_SKIP_LIST_LEVEL - 1) + row_head[row_lvl + 1] = row_head[row_lvl] + 1; + } + + /* Interestingly, this super simple timer insert counter works very very + * well on distributing the list height uniformly. By means of "very very + * well", I mean it beats the randomness of timer->timeout_tick very easily + * (actually, the timeout_tick is not random and easy to be attacked). */ + random_nr++; + tst_nr = random_nr; + + rt_list_insert_after(row_head[RT_TIMER_SKIP_LIST_LEVEL - 1], + &(timer->row[RT_TIMER_SKIP_LIST_LEVEL - 1])); + for (row_lvl = 2; row_lvl <= RT_TIMER_SKIP_LIST_LEVEL; row_lvl++) + { + if (!(tst_nr & RT_TIMER_SKIP_LIST_MASK)) + rt_list_insert_after(row_head[RT_TIMER_SKIP_LIST_LEVEL - row_lvl], + &(timer->row[RT_TIMER_SKIP_LIST_LEVEL - row_lvl])); + else + break; + /* Shift over the bits we have tested. Works well with 1 bit and 2 + * bits. */ + tst_nr >>= (RT_TIMER_SKIP_LIST_MASK + 1) >> 1; + } + + timer->parent.flag |= RT_TIMER_FLAG_ACTIVATED; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + +#ifdef RT_USING_TIMER_SOFT + if (timer->parent.flag & RT_TIMER_FLAG_SOFT_TIMER) + { + /* check whether timer thread is ready */ + if ((timer_thread.stat & RT_THREAD_STAT_MASK) != RT_THREAD_READY) + { + /* resume timer thread to check soft timer */ + rt_thread_resume(&timer_thread); + rt_schedule(); + } + } +#endif + + return RT_EOK; +} +RTM_EXPORT(rt_timer_start); + +/** + * This function will stop the timer + * + * @param timer the timer to be stopped + * + * @return the operation status, RT_EOK on OK, -RT_ERROR on error + */ +rt_err_t rt_timer_stop(rt_timer_t timer) +{ + register rt_base_t level; + + /* timer check */ + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer); + + if (!(timer->parent.flag & RT_TIMER_FLAG_ACTIVATED)) + return -RT_ERROR; + + RT_OBJECT_HOOK_CALL(rt_object_put_hook, (&(timer->parent))); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + _rt_timer_remove(timer); + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* change stat */ + timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + + return RT_EOK; +} +RTM_EXPORT(rt_timer_stop); + +/** + * This function will get or set some options of the timer + * + * @param timer the timer to be get or set + * @param cmd the control command + * @param arg the argument + * + * @return RT_EOK + */ +rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg) +{ + /* timer check */ + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(rt_object_get_type(&timer->parent) == RT_Object_Class_Timer); + + switch (cmd) + { + case RT_TIMER_CTRL_GET_TIME: + *(rt_tick_t *)arg = timer->init_tick; + break; + + case RT_TIMER_CTRL_SET_TIME: + timer->init_tick = *(rt_tick_t *)arg; + break; + + case RT_TIMER_CTRL_SET_ONESHOT: + timer->parent.flag &= ~RT_TIMER_FLAG_PERIODIC; + break; + + case RT_TIMER_CTRL_SET_PERIODIC: + timer->parent.flag |= RT_TIMER_FLAG_PERIODIC; + break; + } + + return RT_EOK; +} +RTM_EXPORT(rt_timer_control); + +/** + * This function will check timer list, if a timeout event happens, the + * corresponding timeout function will be invoked. + * + * @note this function shall be invoked in operating system timer interrupt. + */ +void rt_timer_check(void) +{ + struct rt_timer *t; + rt_tick_t current_tick; + register rt_base_t level; + + RT_DEBUG_LOG(RT_DEBUG_TIMER, ("timer check enter\n")); + + current_tick = rt_tick_get(); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + while (!rt_list_isempty(&rt_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1])) + { + t = rt_list_entry(rt_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next, + struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]); + + /* + * It supposes that the new tick shall less than the half duration of + * tick max. + */ + if ((current_tick - t->timeout_tick) < RT_TICK_MAX / 2) + { + RT_OBJECT_HOOK_CALL(rt_timer_enter_hook, (t)); + + /* remove timer from timer list firstly */ + _rt_timer_remove(t); + + /* call timeout function */ + t->timeout_func(t->parameter); + + /* re-get tick */ + current_tick = rt_tick_get(); + + RT_OBJECT_HOOK_CALL(rt_timer_exit_hook, (t)); + RT_DEBUG_LOG(RT_DEBUG_TIMER, ("current tick: %d\n", current_tick)); + + if ((t->parent.flag & RT_TIMER_FLAG_PERIODIC) && + (t->parent.flag & RT_TIMER_FLAG_ACTIVATED)) + { + /* start it */ + t->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + rt_timer_start(t); + } + else + { + /* stop timer */ + t->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + } + } + else + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + RT_DEBUG_LOG(RT_DEBUG_TIMER, ("timer check leave\n")); +} + +/** + * This function will return the next timeout tick in the system. + * + * @return the next timeout tick in the system + */ +rt_tick_t rt_timer_next_timeout_tick(void) +{ + return rt_timer_list_next_timeout(rt_timer_list); +} + +#ifdef RT_USING_TIMER_SOFT +/** + * This function will check timer list, if a timeout event happens, the + * corresponding timeout function will be invoked. + */ +void rt_soft_timer_check(void) +{ + rt_tick_t current_tick; + rt_list_t *n; + struct rt_timer *t; + + RT_DEBUG_LOG(RT_DEBUG_TIMER, ("software timer check enter\n")); + + current_tick = rt_tick_get(); + + /* lock scheduler */ + rt_enter_critical(); + + for (n = rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next; + n != &(rt_soft_timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1]);) + { + t = rt_list_entry(n, struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]); + + /* + * It supposes that the new tick shall less than the half duration of + * tick max. + */ + if ((current_tick - t->timeout_tick) < RT_TICK_MAX / 2) + { + RT_OBJECT_HOOK_CALL(rt_timer_enter_hook, (t)); + + /* move node to the next */ + n = n->next; + + /* remove timer from timer list firstly */ + _rt_timer_remove(t); + + /* not lock scheduler when performing timeout function */ + rt_exit_critical(); + /* call timeout function */ + t->timeout_func(t->parameter); + + /* re-get tick */ + current_tick = rt_tick_get(); + + RT_OBJECT_HOOK_CALL(rt_timer_exit_hook, (t)); + RT_DEBUG_LOG(RT_DEBUG_TIMER, ("current tick: %d\n", current_tick)); + + /* lock scheduler */ + rt_enter_critical(); + + if ((t->parent.flag & RT_TIMER_FLAG_PERIODIC) && + (t->parent.flag & RT_TIMER_FLAG_ACTIVATED)) + { + /* start it */ + t->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + rt_timer_start(t); + } + else + { + /* stop timer */ + t->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + } + } + else break; /* not check anymore */ + } + + /* unlock scheduler */ + rt_exit_critical(); + + RT_DEBUG_LOG(RT_DEBUG_TIMER, ("software timer check leave\n")); +} + +/* system timer thread entry */ +static void rt_thread_timer_entry(void *parameter) +{ + rt_tick_t next_timeout; + + while (1) + { + /* get the next timeout tick */ + next_timeout = rt_timer_list_next_timeout(rt_soft_timer_list); + if (next_timeout == RT_TICK_MAX) + { + /* no software timer exist, suspend self. */ + rt_thread_suspend(rt_thread_self()); + rt_schedule(); + } + else + { + rt_tick_t current_tick; + + /* get current tick */ + current_tick = rt_tick_get(); + + if ((next_timeout - current_tick) < RT_TICK_MAX / 2) + { + /* get the delta timeout tick */ + next_timeout = next_timeout - current_tick; + rt_thread_delay(next_timeout); + } + } + + /* check software timer */ + rt_soft_timer_check(); + } +} +#endif + +/** + * @ingroup SystemInit + * + * This function will initialize system timer + */ +void rt_system_timer_init(void) +{ + int i; + + for (i = 0; i < sizeof(rt_timer_list) / sizeof(rt_timer_list[0]); i++) + { + rt_list_init(rt_timer_list + i); + } +} + +/** + * @ingroup SystemInit + * + * This function will initialize system timer thread + */ +void rt_system_timer_thread_init(void) +{ +#ifdef RT_USING_TIMER_SOFT + int i; + + for (i = 0; + i < sizeof(rt_soft_timer_list) / sizeof(rt_soft_timer_list[0]); + i++) + { + rt_list_init(rt_soft_timer_list + i); + } + + /* start software timer thread */ + rt_thread_init(&timer_thread, + "timer", + rt_thread_timer_entry, + RT_NULL, + &timer_thread_stack[0], + sizeof(timer_thread_stack), + RT_TIMER_THREAD_PRIO, + 10); + + /* startup */ + rt_thread_startup(&timer_thread); +#endif +} + +/**@}*/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/startup_target.s new file mode 100644 index 0000000000..56a1163207 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/startup_target.s @@ -0,0 +1,500 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + +__CHIPINITIAL EQU 0 + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + IF (__CHIPINITIAL != 0) + PUBWEAK __CHIP_INIT + EXTERN SystemInit + ENDIF + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; PMU, IRQ0 + DCD RTC_IRQHandler ; RTC, IRQ1 + DCD U32K0_IRQHandler ; UART 32K 0, IRQ2 + DCD U32K1_IRQHandler ; UART 32K 1, IRQ3 + DCD I2C_IRQHandler ; I2C, IRQ4 + DCD SPI1_IRQHandler ; SPI1, IRQ5 + DCD UART0_IRQHandler ; UART0, IRQ6 + DCD UART1_IRQHandler ; UART1, IRQ7 + DCD UART2_IRQHandler ; UART2, IRQ8 + DCD UART3_IRQHandler ; UART3, IRQ9 + DCD UART4_IRQHandler ; UART4, IRQ10 + DCD UART5_IRQHandler ; UART5, IRQ11 + DCD ISO78160_IRQHandler ; ISO78160, IRQ12 + DCD ISO78161_IRQHandler ; ISO78161, IRQ13 + DCD TMR0_IRQHandler ; Timer 0, IRQ14 + DCD TMR1_IRQHandler ; Timer 1, IRQ15 + DCD TMR2_IRQHandler ; Timer 2, IRQ16 + DCD TMR3_IRQHandler ; Timer 3, IRQ17 + DCD PWM0_IRQHandler ; PWM0, IRQ18 + DCD PWM1_IRQHandler ; PWM1, IRQ19 + DCD PWM2_IRQHandler ; PWM2, IRQ20 + DCD PWM3_IRQHandler ; PWM3, IRQ21 + DCD DMA_IRQHandler ; DMA, IRQ22 + DCD FLASH_IRQHandler ; FLASH, IRQ23 + DCD ANA_IRQHandler ; ANA, IRQ24 + DCD 0 ; Reserved, IRQ25 + DCD 0 ; Reserved, IRQ26 + DCD SPI2_IRQHandler ; SPI2, IRQ27 + DCD SPI3_IRQHandler ; SPI3, IRQ28 + DCD 0 ; Reserved, IRQ29 + DCD 0 ; Reserved, IRQ30 + DCD 0 ; Reserved, IRQ31 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ELSE + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ENDIF + LDR R0, =__iar_program_start + BX R0 + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PMU_IRQHandler + B PMU_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK U32K0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K0_IRQHandler + B U32K0_IRQHandler + + + PUBWEAK U32K1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U32K1_IRQHandler + B U32K1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK ISO78160_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78160_IRQHandler + B ISO78160_IRQHandler + + + PUBWEAK ISO78161_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ISO78161_IRQHandler + B ISO78161_IRQHandler + + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM0_IRQHandler + B PWM0_IRQHandler + + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + + PUBWEAK PWM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM2_IRQHandler + B PWM2_IRQHandler + + + PUBWEAK PWM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PWM3_IRQHandler + B PWM3_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK ANA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ANA_IRQHandler + B ANA_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + SECTION .Reset_Handler_text:CODE:NOROOT(2) +__CHIP_INIT +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =000FFFE0H + LDR R1, =55AAAA55H + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =00080E00H + LDR R1, =20H + LDR R2, =000FFFE8H + LDR R3, =000FFFF0H + LDR R4, =0 + LDR R7, =0FFH +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =30H + LDR R7, =81FF81FFH +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =000FFFE0H + LDR R1, =0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =4001422CH + LDR R5, =40014230H + LDR R6, =40014234H + LDR R7, =40014238H + LDR R0, =80DC0H + LDR R0, [R0] + LDR R1, =80DC4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DCCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =80DD0H + LDR R0, [R0] + LDR R1, =80DD4H + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0FFFFFFFFH + MVNS R2, R2 + LDR R3, =80DDCH + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0FF00H + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0FF0000H + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0FF000000H + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =40014240H + LDR R0, =80DE0H + LDR R0, [R0] + LDR R1, =80DE4H + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =80DE8H + LDR R0, [R0] + LDR R1, =80DECH + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0FFH + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + ENDIF + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/target_flash.icf b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/target_flash.icf new file mode 100644 index 0000000000..77243f99f1 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/target_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/template.ewd b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/template.ewd new file mode 100644 index 0000000000..c94f8ac11c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/template.ewd 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$PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + $PROJ_DIR$\..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + + rtthread + + $PROJ_DIR$\rtthread\board.c + + + $PROJ_DIR$\rtthread\src\clock.c + + + $PROJ_DIR$\rtthread\src\components.c + + + $PROJ_DIR$\rtthread\libcpu\arm\cortex-m0\context_iar.S + + + $PROJ_DIR$\rtthread\src\cpu.c + + + $PROJ_DIR$\rtthread\libcpu\arm\cortex-m0\cpuport.c + + + $PROJ_DIR$\rtthread\src\idle.c + + + $PROJ_DIR$\rtthread\src\ipc.c + + + $PROJ_DIR$\rtthread\src\irq.c + + + $PROJ_DIR$\rtthread\src\kservice.c + + + $PROJ_DIR$\rtthread\src\mem.c + + + $PROJ_DIR$\rtthread\src\memheap.c + + + $PROJ_DIR$\rtthread\src\mempool.c + + + $PROJ_DIR$\rtthread\src\object.c + + + $PROJ_DIR$\rtthread\rtconfig.h + + + $PROJ_DIR$\rtthread\src\scheduler.c + + + $PROJ_DIR$\rtthread\src\slab.c + + + $PROJ_DIR$\rtthread\src\thread.c + + + $PROJ_DIR$\rtthread\src\timer.c + + + + User + + $PROJ_DIR$\..\Inc\lib_conf.h + + + $PROJ_DIR$\..\Src\main.c + + + $PROJ_DIR$\..\Src\target_isr.c + + + $PROJ_DIR$\..\Src\v_stdio.c + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/template.eww b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/EWARM/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/lib_conf.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/lib_conf.h new file mode 100644 index 0000000000..a25e3a5b20 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/lib_conf.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* ########################## DELAY_MS Configuration ############################## */ + +#define DELAY_MS(n) (26214400/1024*(n)-1) + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_cmp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/main.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/main.h new file mode 100644 index 0000000000..c61b96839d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/main.h @@ -0,0 +1,27 @@ +/** + * @file main.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program head. +******************************************************************************/ + +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" +#include "v_stdio.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/target_isr.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/target_isr.h new file mode 100644 index 0000000000..e0e4dc54bc --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/target_isr.h @@ -0,0 +1,63 @@ +/** + * @file target_isr.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief This file contains the headers of the interrupt handlers. +******************************************************************************/ + +#ifndef __TARGET_ISR_H +#define __TARGET_ISR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PMU_IRQHandler(void); +void RTC_IRQHandler(void); +void U32K0_IRQHandler(void); +void U32K1_IRQHandler(void); +void I2C_IRQHandler(void); +void SPI1_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void ISO78160_IRQHandler(void); +void ISO78161_IRQHandler(void); +void TMR0_IRQHandler(void); +void TMR1_IRQHandler(void); +void TMR2_IRQHandler(void); +void TMR3_IRQHandler(void); +void PWM0_IRQHandler(void); +void PWM1_IRQHandler(void); +void PWM2_IRQHandler(void); +void PWM3_IRQHandler(void); +void DMA_IRQHandler(void); +void FLASH_IRQHandler(void); +void ANA_IRQHandler(void); +void SPI2_IRQHandler(void); +void SPI3_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/v_stdio.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/v_stdio.h new file mode 100644 index 0000000000..3be6c23a6f --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Inc/v_stdio.h @@ -0,0 +1,19 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief 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y^a4&O#B_87PAtTLTo0U7h#BFBGPw|A!ZT+|AtvPva4NnIMC8=Q>q?~>CHfyYqA@@K literal 0 HcmV?d00001 diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.build_log.htm b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.build_log.htm new file mode 100644 index 0000000000..d530225ed6 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.build_log.htm @@ -0,0 +1,81 @@ + + +

+
µVision Build Log

+
Tool Versions:

+IDE-Version: ¦ÌVision V5.29.0.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: Z Z, VANGO, LIC=HF82M-XE05D-HREXN-YUSPE-IWFZX-WW2UF
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Professional  Version: 5.29.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.29.0.0
+Dialog DLL:      DARMCM1.DLL V1.19.2.0
+Target DLL:      CMSIS_AGDI.dll V1.32.0.0
+Dialog DLL:      TARMCM1.DLL V1.14.1.0
+ 
+
Project:

+D:\10IC\02IC_SPVD\DriveLibrary\trunk\Project\Puma_Series\PumaA\V85X3P_Lib_V1.1\Project_RT\template\template\MDK-ARM\template.uvprojx
+Project File Date:  05/12/2020
+
+
Output:

+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'template'
+".\Objects\template.axf" - 0 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
+                ARM.CMSIS.5.6.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.3.0
+
+Package Vendor: RealThread
+                https://www.rt-thread.org/download/mdk/RealThread.RT-Thread.3.1.3.pack
+                RealThread.RT-Thread.3.1.3
+                RT-Thread Software Components
+   * Component: kernel Version: 3.1.3
+
+Package Vendor: Vango
+                
+                Vango.V85X3P.1.1.0
+                V85X3P ARM Cortex-M0 Device Family Pack
+
+
Collection of Component include folders:

+  .\RTE\RTOS
+  .\RTE\_template
+  C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
+  C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\include
+  C:\Keil_v5\ARM\PACK\Vango\V85X3P\1.1.0\Device\Include
+
+
Collection of Component Files used:

+
+   * Component: ARM::CMSIS:CORE:5.3.0
+
+   * Component: RealThread.RT-Thread::RTOS:kernel:3.1.3
+      Include file:  bsp\rtconfig.h
+      Source file:   bsp\board.c
+      Source file:   src\clock.c
+      Source file:   src\components.c
+      Source file:   src\idle.c
+      Source file:   src\ipc.c
+      Source file:   src\irq.c
+      Source file:   src\kservice.c
+      Source file:   src\mem.c
+      Source file:   src\object.c
+      Source file:   src\scheduler.c
+      Source file:   src\thread.c
+      Source file:   src\timer.c
+      Source file:   libcpu\arm\cortex-m0\cpuport.c
+      Source file:   libcpu\arm\cortex-m0\context_rvds.S
+Build Time Elapsed:  00:00:05
+
+ + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.lnp b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.lnp new file mode 100644 index 0000000000..88003c5b4b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.lnp @@ -0,0 +1,47 @@ +--cpu Cortex-M0 +".\objects\main.o" +".\objects\target_isr.o" +".\objects\v_stdio.o" +".\objects\startup_target.o" +".\objects\system_target.o" +".\objects\lib_adc.o" +".\objects\lib_adc_tiny.o" +".\objects\lib_ana.o" +".\objects\lib_clk.o" +".\objects\lib_crypt.o" +".\objects\lib_dma.o" +".\objects\lib_flash.o" +".\objects\lib_gpio.o" +".\objects\lib_i2c.o" +".\objects\lib_iso7816.o" +".\objects\lib_lcd.o" +".\objects\lib_misc.o" +".\objects\lib_pmu.o" +".\objects\lib_pwm.o" +".\objects\lib_rtc.o" +".\objects\lib_spi.o" +".\objects\lib_tmr.o" +".\objects\lib_u32k.o" +".\objects\lib_uart.o" +".\objects\lib_version.o" +".\objects\lib_wdt.o" +".\objects\lib_cmp.o" +".\objects\lib_coderam.o" +".\objects\lib_cortex.o" +".\objects\lib_loadnvr.o" +".\objects\context_rvds.o" +".\objects\cpuport.o" +".\objects\clock.o" +".\objects\components.o" +".\objects\idle.o" +".\objects\ipc.o" +".\objects\irq.o" +".\objects\kservice.o" +".\objects\mem.o" +".\objects\object.o" +".\objects\scheduler.o" +".\objects\thread.o" +".\objects\timer.o" +".\objects\board.o" +--library_type=microlib --strict --scatter ".\Objects\template.sct" +--summary_stderr --info summarysizes -o .\Objects\template.axf \ No newline at end of file diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.sct b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.sct new file mode 100644 index 0000000000..4504d736c7 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/Objects/template.sct @@ -0,0 +1,17 @@ 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/dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/RTOS/board.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-07-24 Tanek the first version + * 2018-11-12 Ernest Chen modify copyright + */ + +#include +#include +#include + +#define _SCB_BASE (0xE000E010UL) +#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0)) +#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4)) +#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8)) +#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC)) +#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL)) + +// Updates the variable SystemCoreClock and must be called +// whenever the core clock is changed during program execution. +extern void SystemCoreClockUpdate(void); + +// Holds the system core clock, which is the system clock +// frequency supplied to the SysTick timer and the processor +// core clock. +extern uint32_t SystemCoreClock; + +static uint32_t _SysTick_Config(rt_uint32_t ticks) +{ + if ((ticks - 1) > 0xFFFFFF) + { + return 1; + } + + _SYSTICK_LOAD = ticks - 1; + _SYSTICK_PRI = 0xFF; + _SYSTICK_VAL = 0; + _SYSTICK_CTRL = 0x07; + + return 0; +} + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +#define RT_HEAP_SIZE 1024 +static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4) +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +/** + * This function will initial your board. + */ +void rt_hw_board_init() +{ + /* System Clock Update */ + SystemCoreClockUpdate(); + + /* System Tick Configuration */ + _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/RTOS/rtconfig.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/RTOS/rtconfig.h new file mode 100644 index 0000000000..cc77b2edd3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/RTOS/rtconfig.h @@ -0,0 +1,154 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +#include "RTE_Components.h" + +#if defined(RTE_USING_FINSH) +#define RT_USING_FINSH +#endif //RTE_USING_FINSH + +#endif //(__CC_ARM) || (__CLANG_ARM) + +// <<< Use Configuration Wizard in Context Menu >>> +// Basic Configuration +// Maximal level of thread priority <8-256> +// Default: 32 +#define RT_THREAD_PRIORITY_MAX 8 +// OS tick per second +// Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// Alignment size for CPU architecture data access +// Default: 4 +#define RT_ALIGN_SIZE 4 +// the max length of object name<2-16> +// Default: 8 +#define RT_NAME_MAX 8 +// Using RT-Thread components initialization +// Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// + +#define RT_USING_USER_MAIN + +// the stack size of main thread<1-4086> +// Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 256 + +// + +// Debug Configuration +// enable kernel debug configuration +// Default: enable kernel debug configuration +//#define RT_DEBUG +// +// enable components initialization debug configuration<0-1> +// Default: 0 +#define RT_DEBUG_INIT 0 +// thread stack over flow detect +// Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// +// + +// Hook Configuration +// using hook +// using hook +#define RT_USING_HOOK +// +// using idle hook +// using idle hook +//#define RT_USING_IDLE_HOOK +// +// + +// Software timers Configuration +// Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// The priority level of timer thread <0-31> +// Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// The stack size of timer thread <0-8192> +// Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// + +// IPC(Inter-process communication) Configuration +// Using Semaphore +// Using Semaphore +#define RT_USING_SEMAPHORE +// +// Using Mutex +// Using Mutex +//#define RT_USING_MUTEX +// +// Using Event +// Using Event +//#define RT_USING_EVENT +// +// Using MailBox +// Using MailBox +#define RT_USING_MAILBOX +// +// Using Message Queue +// Using Message Queue +//#define RT_USING_MESSAGEQUEUE +// +// + +// Memory Management Configuration +// Dynamic Heap Management +// Dynamic Heap Management +#define RT_USING_HEAP +// +// using small memory +// using small memory +#define RT_USING_SMALL_MEM +// +// using tiny size of memory +// using tiny size of memory +//#define RT_USING_TINY_SIZE +// +// + +// Console Configuration +// Using console +// Using console +#define RT_USING_CONSOLE +// +// the buffer size of console <1-1024> +// the buffer size of console +// Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 128 +// + +#if defined(RT_USING_FINSH) + #define FINSH_USING_MSH + #define FINSH_USING_MSH_ONLY + // Finsh Configuration + // the priority of finsh thread <1-7> + // the priority of finsh thread + // Default: 6 + #define __FINSH_THREAD_PRIORITY 5 + #define FINSH_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX / 8 * __FINSH_THREAD_PRIORITY + 1) + // the stack of finsh thread <1-4096> + // the stack of finsh thread + // Default: 4096 (4096Byte) + #define FINSH_THREAD_STACK_SIZE 512 + // the history lines of finsh thread <1-32> + // the history lines of finsh thread + // Default: 5 + #define FINSH_HISTORY_LINES 1 + + #define FINSH_USING_SYMTAB + // +#endif + +// <<< end of configuration section >>> + +#endif diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/_template/RTE_Components.h b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/_template/RTE_Components.h new file mode 100644 index 0000000000..a05068b37c --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/RTE/_template/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'template' + * Target: 'template' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "target.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/startup_target.s new file mode 100644 index 0000000000..cda8ff1a5b --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 0 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvguix.zhuxw b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvguix.zhuxw new file mode 100644 index 0000000000..82988f6928 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvguix.zhuxw @@ -0,0 +1,3691 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 0 + + ..\Src\main.c + 1 + 100 + 117 + 1 + + 0 + + + RTE\RTOS\rtconfig.h + 28 + 42 + 63 + 1 + + 0 + + + C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\include\rtdef.h + 0 + 46 + 62 + 1 + + 0 + + + C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\src\idle.c + 20 + 17 + 40 + 1 + + 0 + + + C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\src\object.c + 29 + 239 + 262 + 1 + + 0 + + + C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\src\components.c + 11 + 161 + 184 + 1 + + 0 + + + C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\include\rtdebug.h + 0 + 112 + 135 + 1 + + 0 + + + C:\Keil_v5\ARM\PACK\RealThread\RT-Thread\3.1.3\src\kservice.c + 19 + 998 + 1021 + 1 + 1197 + 0 + + + ..\Src\v_stdio.c + 0 + 14 + 27 + 1 + + 0 + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvoptx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvoptx new file mode 100644 index 0000000000..d68f6d4cc8 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvoptx @@ -0,0 +1,629 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 12 + + + + + ..\..\..\test.ini + + + + + ..\..\..\test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0Vango_V85X3P -FL080000 -FS00 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P.FLM -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM) + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK-ARM + 0 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::RTOS + 1 + 0 + 0 + 1 + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvprojx b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvprojx new file mode 100644 index 0000000000..3d8f763374 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARM/template.uvprojx @@ -0,0 +1,659 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85X3P + Generic + Vango.V85X3P.1.1.0 + IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(6553600) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 -FP0($$Device:V85X3P$FLASH\Vango_V85X3P.FLM)) + 0 + $$Device:V85X3P$Device\Include\target.h + + + + + + + + + + $$Device:V85X3P$SVD\V85X3P.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $tool\..\..\ARM\ARMCC\bin\fromelf.exe --bin --output ../template.bin Objects/template.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK-ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + 2 + 9 + 4 + 4 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + ::CMSIS + + + ::RTOS + + + + + + + + + + + + + + + + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\RTOS\board.c + + + + + + + + RTE\RTOS\rtconfig.h + + + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/startup_target.s b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/startup_target.s new file mode 100644 index 0000000000..f945da4501 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/startup_target.s @@ -0,0 +1,451 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IF (__CHIPINITIAL != 0) + IMPORT SystemInit + LDR R0, =__CHIP_INIT + BLX R0 + LDR R0, =SystemInit + BLX R0 + ENDIF + LDR R0, =__main + BX R0 + ENDP + + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvopt b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvopt new file mode 100644 index 0000000000..69cf2a9460 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvopt @@ -0,0 +1,705 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + template + 0x4 + ARM-ADS + + 6553600 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U000014A8F3A5 -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00 -FL080000 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Template/User + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 59 + 59 + 0 + ..\Src\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\target_isr.c + target_isr.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Src\v_stdio.c + v_stdio.c + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Inc\lib_conf.h + lib_conf.h + 0 + 0 + + + + + Template/MDK_ARM + 1 + 0 + 0 + 0 + + 2 + 5 + 2 + 0 + 0 + 0 + 0 + 106 + 113 + 0 + .\startup_target.s + startup_target.s + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + system_target.c + 0 + 0 + + + + + FWLib + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + lib_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + lib_ana.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + lib_clk.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + lib_crypt.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + lib_dma.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + lib_flash.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + lib_gpio.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + lib_i2c.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + lib_iso7816.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + lib_lcd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + lib_misc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + lib_pmu.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + lib_pwm.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + lib_rtc.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + lib_spi.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + lib_tmr.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + lib_u32k.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + lib_uart.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + lib_version.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + lib_wdt.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + lib_cmp.c + 0 + 0 + + + + + FWLib/Device + 1 + 0 + 0 + 0 + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + lib_CodeRAM.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + lib_cortex.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + lib_LoadNVR.c + 0 + 0 + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvproj b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvproj new file mode 100644 index 0000000000..f673bbea5e --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/MDK-ARMv4/template.uvproj @@ -0,0 +1,584 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + template + 0x4 + ARM-ADS + + + V85X3P + Vango + IRAM(0x20000000-0x2000FFFF) IROM(0x0-0x7FFFF) CLOCK(6553600) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC8000 -FN1 -FF0Vango_V85X3P -FS00000000 -FL040000) + 0 + + + + + + + + + + + SFD\Vango\V85X3P\V85X3P.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + ../../../test.ini + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + USE_TARGET_DRIVER + + ..\Inc;..\Src;..\..\..\..\Libraries\Lib_Driver\inc;..\..\..\..\Libraries\Lib_Driver\src;..\..\..\..\Libraries\CMSIS\device;..\..\..\..\Libraries\CMSIS\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Template/User + + + main.c + 1 + ..\Src\main.c + + + target_isr.c + 1 + ..\Src\target_isr.c + + + v_stdio.c + 1 + ..\Src\v_stdio.c + + + lib_conf.h + 5 + ..\Inc\lib_conf.h + + + + + Template/MDK_ARM + + + startup_target.s + 2 + .\startup_target.s + + + system_target.c + 1 + ..\..\..\..\Libraries\CMSIS\device\system_target.c + + + + + FWLib + + + lib_adc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc.c + + + lib_adc_tiny.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_adc_tiny.c + + + lib_ana.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_ana.c + + + lib_clk.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_clk.c + + + lib_crypt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_crypt.c + + + lib_dma.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_dma.c + + + lib_flash.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_flash.c + + + lib_gpio.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_gpio.c + + + lib_i2c.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_i2c.c + + + lib_iso7816.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_iso7816.c + + + lib_lcd.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_lcd.c + + + lib_misc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_misc.c + + + lib_pmu.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pmu.c + + + lib_pwm.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_pwm.c + + + lib_rtc.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_rtc.c + + + lib_spi.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_spi.c + + + lib_tmr.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_tmr.c + + + lib_u32k.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_u32k.c + + + lib_uart.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_uart.c + + + lib_version.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_version.c + + + lib_wdt.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_wdt.c + + + lib_cmp.c + 1 + ..\..\..\..\Libraries\Lib_Driver\src\lib_cmp.c + + + + + FWLib/Device + + + lib_CodeRAM.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_CodeRAM.c + + + lib_cortex.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_cortex.c + + + lib_LoadNVR.c + 1 + ..\..\..\..\Libraries\CMSIS\device\lib_LoadNVR.c + + + + + + + + diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/main.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/main.c new file mode 100644 index 0000000000..b953255528 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/main.c @@ -0,0 +1,185 @@ +/** + * @file main.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main program body. +******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "rtthread.h" + +/* Private functions ---------------------------------------------------------*/ + +volatile unsigned char test_success; + +/** + * @brief Clock_Init: + - PLLL input clock : External 32K crystal + - PLLL frequency : 26M + - AHB Clock source : PLLL + - AHB Clock frequency : 26M (PLLL divided by 1) + - APB Clock frequency : 13M (AHB Clock divided by 2) + * @param None + * @retval None + */ +void Clock_Init(void) +{ +// <<< Use Configuration Wizard in Context Menu >>> + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; +//the buffer size of console <1-1024> +//the buffer size of console +// +//AHBSource +CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; +// + + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +// <<< end of configuration section >>> +} +uint32_t SystemCoreClock=26214400; +void SystemCoreClockUpdate(void) +{ + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + + +ALIGN(RT_ALIGN_SIZE) +static char thread1_stack[512]; +static struct rt_thread thread1; +static char thread2_stack[512]; +static struct rt_thread thread2; + + +/** + * @brief Main program. + * @param None + * @retval None + */ + + +static void main1_entry(void *parameter) +{ + GPIO_InitType GPIOInitStruct; + + GPIOInitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIOInitStruct.GPIO_Pin = GPIO_Pin_5; + GPIOBToF_Init(GPIOD,&GPIOInitStruct); + + while (1) + { + GPIO_WriteBit(GPIO_D,5,1); + rt_thread_mdelay(1000); + GPIO_WriteBit(GPIO_D,5,0); +// CORTEX_Delay_nSysClock(26214400/10); + rt_thread_mdelay(1000); + } +} +static void main2_entry(void *parameter) +{ + GPIO_InitType GPIOInitStruct; + + GPIOInitStruct.GPIO_Mode = GPIO_MODE_OUTPUT_CMOS; + GPIOInitStruct.GPIO_Pin = GPIO_Pin_2; + GPIOBToF_Init(GPIOD,&GPIOInitStruct); + + while (1) + { + GPIO_WriteBit(GPIO_D,2,1); + rt_thread_mdelay(250); + GPIO_WriteBit(GPIO_D,2,0); +// CORTEX_Delay_nSysClock(26214400/10); + rt_thread_mdelay(250); + } +} + +static void hook_of_scheduler(struct rt_thread* from, struct rt_thread* to) +{ + rt_kprintf("from: %s --> to: %s \n", from->name , to->name); +} + +int main(void) +{ + GPIO_InitType GPIOInitStruct; + + test_success = 0; + + Clock_Init(); + Stdio_Init(); + LCD->CTRL = 0X84; + + /* ÉèÖõ÷¶ÈÆ÷¹³×Ó */ + rt_scheduler_sethook(hook_of_scheduler); + + rt_thread_init(&thread1, + "thread1", + main1_entry, + RT_NULL, + &thread1_stack[0], + sizeof(thread1_stack), + 4, 5); + rt_thread_startup(&thread1); + + rt_thread_init(&thread2, + "thread2", + main2_entry, + RT_NULL, + &thread2_stack[0], + sizeof(thread2_stack), + 4, 5); + rt_thread_startup(&thread2); + + +// test_success = 1; +// while (1) +// { +// WDT_Clear(); +// } +} + + + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/target_isr.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/target_isr.c new file mode 100644 index 0000000000..cfbf5c945d --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/target_isr.c @@ -0,0 +1,305 @@ +/** + * @file target_isr.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief Main Interrupt Service Routines. +******************************************************************************/ + +#include "target_isr.h" +#include "main.h" + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + while(1) + {} +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +//void HardFault_Handler(void) +//{ +// while(1) +// {} +//} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +//void PendSV_Handler(void) +//{ +//} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +//void SysTick_Handler(void) +//{ +//} + +/** + * @brief This function handles PMU interrupt request. + * @param None + * @retval None + */ +void PMU_IRQHandler(void) +{ +} + +/** + * @brief This function handles RTC interrupt request. + * @param None + * @retval None + */ +void RTC_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K0 interrupt request. + * @param None + * @retval None + */ +void U32K0_IRQHandler(void) +{ +} + +/** + * @brief This function handles U32K1 interrupt request. + * @param None + * @retval None + */ +void U32K1_IRQHandler(void) +{ +} + +/** + * @brief This function handles I2C interrupt request. + * @param None + * @retval None + */ +void I2C_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI1 interrupt request. + * @param None + * @retval None + */ +void SPI1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART0 interrupt request. + * @param None + * @retval None + */ +void UART0_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART1 interrupt request. + * @param None + * @retval None + */ +void UART1_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART2 interrupt request. + * @param None + * @retval None + */ +void UART2_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART3 interrupt request. + * @param None + * @retval None + */ +void UART3_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART4 interrupt request. + * @param None + * @retval None + */ +void UART4_IRQHandler(void) +{ +} + +/** + * @brief This function handles UART5 interrupt request. + * @param None + * @retval None + */ +void UART5_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78160 interrupt request. + * @param None + * @retval None + */ +void ISO78160_IRQHandler(void) +{ +} + +/** + * @brief This function handles ISO78161 interrupt request. + * @param None + * @retval None + */ +void ISO78161_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR0 interrupt request. + * @param None + * @retval None + */ +void TMR0_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR1 interrupt request. + * @param None + * @retval None + */ +void TMR1_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR2 interrupt request. + * @param None + * @retval None + */ +void TMR2_IRQHandler(void) +{ +} + +/** + * @brief This function handles TMR3 interrupt request. + * @param None + * @retval None + */ +void TMR3_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM0 interrupt request. + * @param None + * @retval None + */ +void PWM0_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM1 interrupt request. + * @param None + * @retval None + */ +void PWM1_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM2 interrupt request. + * @param None + * @retval None + */ +void PWM2_IRQHandler(void) +{ +} + +/** + * @brief This function handles PWM3 interrupt request. + * @param None + * @retval None + */ +void PWM3_IRQHandler(void) +{ +} + +/** + * @brief This function handles DMA interrupt request. + * @param None + * @retval None + */ +void DMA_IRQHandler(void) +{ +} + +/** + * @brief This function handles FLASH interrupt request. + * @param None + * @retval None + */ +void FLASH_IRQHandler(void) +{ +} + +/** + * @brief This function handles ANA interrupt request. + * @param None + * @retval None + */ +void ANA_IRQHandler(void) +{ +} + +/** + * @brief This function handles SPI2 interrupt request. + * @param None + * @retval None + */ +void SPI2_IRQHandler(void) +{ +} + + +/** + * @brief This function handles SPI3 interrupt request. + * @param None + * @retval None + */ +void SPI3_IRQHandler(void) +{ +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/v_stdio.c b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/v_stdio.c new file mode 100644 index 0000000000..7d100843d3 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Project_RT/template/template/Src/v_stdio.c @@ -0,0 +1,54 @@ +/** + * @file v_stdio.h + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief standard printf. +******************************************************************************/ + +#include "v_stdio.h" +#include "target.h" +#include +#ifdef __GNUC__ + #include +#endif /* __GNUC__ */ + +/** + * @brief printf init. + * @param None + * @retval None + */ +void Stdio_Init(void) +{ + UART5->BAUDDIV = CLK_GetPCLKFreq()/115200; + UART5->CTRL = UART_CTRL_TXEN; +} + +#ifdef __GNUC__ +int _write(int32_t fd, char* ptr, int32_t len) +{ + uint32_t i; + + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + { + i = 0UL; + while (i < len) + { + UART5->DATA = ptr[i++]; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + } + } + return len; +} +#else +int fputc(int ch, FILE *f) +{ + UART5->DATA = ch; + while (!(UART5->STATE&UART_STATE_TXDONE)); + UART5->STATE = UART_STATE_TXDONE; + return ch; +} +#endif /* __GNUC__ */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Tmp_Kill.bat b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Tmp_Kill.bat new file mode 100644 index 0000000000..111e1291a2 --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/Tmp_Kill.bat @@ -0,0 +1,3 @@ +@echo off +del /s /a "*.TMP" 2>nul +exit diff --git a/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/keil_Kill.bat b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/keil_Kill.bat new file mode 100644 index 0000000000..ba17d320fe --- /dev/null +++ b/bsp/Vango-V85xxp/V85X3P_Lib_V1.1/keil_Kill.bat @@ -0,0 +1,37 @@ +@echo off +set n=%USERNAME% +del *.%n% /s + +del *.hex /s +del *.bak /s +del *.ddk /s +del *.edk /s +del *.lst /s +del *.lnp /s +del *.mpf /s +del *.mpj /s +del *.obj /s +del *.omf /s +del *.plg /s +del *.rpt /s +del *.tmp /s +del *.__i /s +del *.crf /s +del *.o /s +del *.d /s +del *.axf /s +del *.tra /s +del *.dep /s +del JLinkLog.txt /s +del *.iex /s +del *.htm /s +rem del *.sct /s +del *.map /s +del *.ini /s +del *.scvd /s + +for /r %%d in (.) do rd /s /q "%%d\Listings" 2>nul +for /r %%d in (.) do rd /s /q "%%d\RTE" 2>nul +for /r %%d in (.) do rd /s /q "%%d\Objects" 2>nul + +exit -- Gitee

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